include/configs/M5235EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF5329 FireEngine board.
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M5235EVB_H
  15 #define _M5235EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21
  22 #define CONFIG_MCFUART
  23 #define CONFIG_SYS_UART_PORT            (0)
  24 #define CONFIG_BAUDRATE         115200
  25
  26 #undef CONFIG_WATCHDOG
  27 #define CONFIG_WATCHDOG_TIMEOUT 5000    /* timeout in milliseconds, max timeout is 6.71sec */
  28
  29 /*
  30  * BOOTP options
  31  */
  32 #define CONFIG_BOOTP_BOOTFILESIZE
  33 #define CONFIG_BOOTP_BOOTPATH
  34 #define CONFIG_BOOTP_GATEWAY
  35 #define CONFIG_BOOTP_HOSTNAME
  36
  37 /* Command line configuration */
  38 #define CONFIG_CMD_CACHE
  39 #define CONFIG_CMD_DHCP
  40 #define CONFIG_CMD_ELF
  41 #define CONFIG_CMD_I2C
  42 #define CONFIG_CMD_MII
  43 #define CONFIG_CMD_PCI
  44 #define CONFIG_CMD_PING
  45 #define CONFIG_CMD_REGINFO
  46
  47
  48 #define CONFIG_MCFFEC
  49 #ifdef CONFIG_MCFFEC
  50 #       define CONFIG_MII               1
  51 #       define CONFIG_MII_INIT          1
  52 #       define CONFIG_SYS_DISCOVER_PHY
  53 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  54 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  55
  56 #       define CONFIG_SYS_FEC0_PINMUX           0
  57 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  58 #       define MCFFEC_TOUT_LOOP         50000
  59 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  60 #       ifndef CONFIG_SYS_DISCOVER_PHY
  61 #               define FECDUPLEX        FULL
  62 #               define FECSPEED         _100BASET
  63 #       else
  64 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  65 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  66 #               endif
  67 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  68 #endif
  69
  70 /* Timer */
  71 #define CONFIG_MCFTMR
  72 #undef CONFIG_MCFPIT
  73
  74 /* I2C */
  75 #define CONFIG_SYS_I2C
  76 #define CONFIG_SYS_i2C_FSL
  77 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  78 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  79 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00000300
  80 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
  81 #define CONFIG_SYS_I2C_PINMUX_REG       (gpio->par_qspi)
  82 #define CONFIG_SYS_I2C_PINMUX_CLR       ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
  83 #define CONFIG_SYS_I2C_PINMUX_SET       (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
  84
  85 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  86 #define CONFIG_BOOTDELAY        1       /* autoboot after 5 seconds */
  87 #define CONFIG_BOOTFILE         "u-boot.bin"
  88 #ifdef CONFIG_MCFFEC
  89 #       define CONFIG_IPADDR    192.162.1.2
  90 #       define CONFIG_NETMASK   255.255.255.0
  91 #       define CONFIG_SERVERIP  192.162.1.1
  92 #       define CONFIG_GATEWAYIP 192.162.1.1
  93 #endif                          /* FEC_ENET */
  94
  95 #define CONFIG_HOSTNAME         M5235EVB
  96 #define CONFIG_EXTRA_ENV_SETTINGS               \
  97         "netdev=eth0\0"                         \
  98         "loadaddr=10000\0"                      \
  99         "u-boot=u-boot.bin\0"                   \
 100         "load=tftp ${loadaddr) ${u-boot}\0"     \
 101         "upd=run load; run prog\0"              \
 102         "prog=prot off ffe00000 ffe3ffff;"      \
 103         "era ffe00000 ffe3ffff;"                \
 104         "cp.b ${loadaddr} ffe00000 ${filesize};"\
 105         "save\0"                                \
 106         ""
 107
 108 #define CONFIG_PRAM             512     /* 512 KB */
 109 #define CONFIG_SYS_PROMPT               "-> "
 110 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 111
 112 #if defined(CONFIG_KGDB)
 113 #       define CONFIG_SYS_CBSIZE                1024    /* Console I/O Buffer Size */
 114 #else
 115 #       define CONFIG_SYS_CBSIZE                256     /* Console I/O Buffer Size */
 116 #endif
 117
 118 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 119 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 120 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 121 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE+0x20000)
 122
 123 #define CONFIG_SYS_CLK                  75000000
 124 #define CONFIG_SYS_CPU_CLK              CONFIG_SYS_CLK * 2
 125
 126 #define CONFIG_SYS_MBAR         0x40000000
 127
 128 /*
 129  * Low Level Configuration Settings
 130  * (address mappings, register initial values, etc.)
 131  * You should know what you are doing if you make changes here.
 132  */
 133 /*-----------------------------------------------------------------------
 134  * Definitions for initial stack pointer and data area (in DPRAM)
 135  */
 136 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 137 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM */
 138 #define CONFIG_SYS_INIT_RAM_CTRL        0x21
 139 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
 140 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 141
 142 /*-----------------------------------------------------------------------
 143  * Start addresses for the final memory configuration
 144  * (Set up by the startup code)
 145  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 146  */
 147 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 148 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 149
 150 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 151 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 152
 153 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 154 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 155
 156 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 157 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 158
 159 /*
 160  * For booting Linux, the board info and command line data
 161  * have to be in the first 8 MB of memory, since this is
 162  * the maximum mapped by the Linux kernel during initialization ??
 163  */
 164 /* Initial Memory map for Linux */
 165 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 166 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 167
 168 /*-----------------------------------------------------------------------
 169  * FLASH organization
 170  */
 171 #define CONFIG_SYS_FLASH_CFI
 172 #ifdef CONFIG_SYS_FLASH_CFI
 173 #       define CONFIG_FLASH_CFI_DRIVER  1
 174 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
 175 #ifdef NORFLASH_PS32BIT
 176 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_32BIT
 177 #else
 178 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 179 #endif
 180 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 181 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 182 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 183 #endif
 184
 185 #define CONFIG_SYS_FLASH_BASE           (CONFIG_SYS_CS0_BASE)
 186
 187 /* Configuration for environment
 188  * Environment is embedded in u-boot in the second sector of the flash
 189  */
 190 #define CONFIG_ENV_IS_IN_FLASH  1
 191
 192 #define LDS_BOARD_TEXT \
 193         . = DEFINED(env_offset) ? env_offset : .; \
 194         common/env_embedded.o (.text);
 195
 196 #ifdef NORFLASH_PS32BIT
 197 #       define CONFIG_ENV_OFFSET                (0x8000)
 198 #       define CONFIG_ENV_SIZE          0x4000
 199 #       define CONFIG_ENV_SECT_SIZE     0x4000
 200 #else
 201 #       define CONFIG_ENV_OFFSET                (0x4000)
 202 #       define CONFIG_ENV_SIZE          0x2000
 203 #       define CONFIG_ENV_SECT_SIZE     0x2000
 204 #endif
 205
 206 /*-----------------------------------------------------------------------
 207  * Cache Configuration
 208  */
 209 #define CONFIG_SYS_CACHELINE_SIZE       16
 210
 211 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 212                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 213 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 214                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 215 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV)
 216 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 217                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 218                                          CF_ACR_EN | CF_ACR_SM_ALL)
 219 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 220                                          CF_CACR_CEIB | CF_CACR_DCM | \
 221                                          CF_CACR_EUSP)
 222
 223 /*-----------------------------------------------------------------------
 224  * Chipselect bank definitions
 225  */
 226 /*
 227  * CS0 - NOR Flash 1, 2, 4, or 8MB
 228  * CS1 - Available
 229  * CS2 - Available
 230  * CS3 - Available
 231  * CS4 - Available
 232  * CS5 - Available
 233  * CS6 - Available
 234  * CS7 - Available
 235  */
 236 #ifdef NORFLASH_PS32BIT
 237 #       define CONFIG_SYS_CS0_BASE      0xFFC00000
 238 #       define CONFIG_SYS_CS0_MASK      0x003f0001
 239 #       define CONFIG_SYS_CS0_CTRL      0x00001D00
 240 #else
 241 #       define CONFIG_SYS_CS0_BASE      0xFFE00000
 242 #       define CONFIG_SYS_CS0_MASK      0x001f0001
 243 #       define CONFIG_SYS_CS0_CTRL      0x00001D80
 244 #endif
 245
 246 #endif                          /* _M5329EVB_H */