include/configs/M5249EVB.h

   1 /*
   2  * Configuation settings for the esd TASREG board.
   3  *
   4  * (C) Copyright 2004
   5  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M5249EVB_H
  15 #define _M5249EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_MCFTMR
  22
  23 #define CONFIG_MCFUART
  24 #define CONFIG_SYS_UART_PORT            (0)
  25 #define CONFIG_BAUDRATE         115200
  26
  27 #undef  CONFIG_WATCHDOG
  28
  29 #undef CONFIG_MONITOR_IS_IN_RAM         /* no pre-loader required!!! ;-) */
  30
  31 /*
  32  * BOOTP options
  33  */
  34 #undef CONFIG_BOOTP_BOOTFILESIZE
  35 #undef CONFIG_BOOTP_BOOTPATH
  36 #undef CONFIG_BOOTP_GATEWAY
  37 #undef CONFIG_BOOTP_HOSTNAME
  38
  39 /*
  40  * Command line configuration.
  41  */
  42 #include <config_cmd_default.h>
  43 #define CONFIG_CMD_CACHE
  44
  45 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
  46
  47 #if defined(CONFIG_CMD_KGDB)
  48 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size      */
  49 #else
  50 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
  51 #endif
  52 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  53 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
  54 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  55
  56 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
  57 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup        */
  58 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
  59 #define CONFIG_LOOPW            1       /* enable loopw command */
  60 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
  61
  62 #define CONFIG_SYS_LOAD_ADDR            0x200000        /* default load address */
  63
  64 #define CONFIG_SYS_MEMTEST_START        0x400
  65 #define CONFIG_SYS_MEMTEST_END          0x380000
  66
  67 /*
  68  * Clock configuration: enable only one of the following options
  69  */
  70
  71 #undef  CONFIG_SYS_PLL_BYPASS                           /* bypass PLL for test purpose */
  72 #define CONFIG_SYS_FAST_CLK             1               /* MCF5249 can run at 140MHz   */
  73 #define CONFIG_SYS_CLK                  132025600       /* MCF5249 can run at 140MHz   */
  74
  75 /*
  76  * Low Level Configuration Settings
  77  * (address mappings, register initial values, etc.)
  78  * You should know what you are doing if you make changes here.
  79  */
  80
  81 #define CONFIG_SYS_MBAR         0x10000000      /* Register Base Addrs */
  82 #define CONFIG_SYS_MBAR2                0x80000000
  83
  84 /*-----------------------------------------------------------------------
  85  * Definitions for initial stack pointer and data area (in DPRAM)
  86  */
  87 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  88 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in internal SRAM   */
  89 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  90 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  91
  92 #define CONFIG_ENV_IS_IN_FLASH  1
  93
  94 #define LDS_BOARD_TEXT \
  95         . = DEFINED(env_offset) ? env_offset : .; \
  96         common/env_embedded.o (.text);
  97
  98 #define CONFIG_ENV_OFFSET               0x4000  /* Address of Environment Sector*/
  99 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 100 #define CONFIG_ENV_SECT_SIZE    0x2000 /* see README - env sector total size    */
 101
 102 /*-----------------------------------------------------------------------
 103  * Start addresses for the final memory configuration
 104  * (Set up by the startup code)
 105  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 106  */
 107 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 108 #define CONFIG_SYS_SDRAM_SIZE           16              /* SDRAM size in MB */
 109 #define CONFIG_SYS_FLASH_BASE           (CONFIG_SYS_CS0_BASE)
 110
 111 #if 0 /* test-only */
 112 #define CONFIG_PRAM             512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
 113 #endif
 114
 115 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 116
 117 #define CONFIG_SYS_MONITOR_LEN          0x20000
 118 #define CONFIG_SYS_MALLOC_LEN           (1 * 1024*1024) /* Reserve 1 MB for malloc()    */
 119 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 120
 121 /*
 122  * For booting Linux, the board info and command line data
 123  * have to be in the first 8 MB of memory, since this is
 124  * the maximum mapped by the Linux kernel during initialization ??
 125  */
 126 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 127
 128 /*-----------------------------------------------------------------------
 129  * FLASH organization
 130  */
 131 #define CONFIG_SYS_FLASH_CFI
 132 #ifdef CONFIG_SYS_FLASH_CFI
 133
 134 #       define CONFIG_FLASH_CFI_DRIVER  1
 135 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 136 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 137 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 138 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 139 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 140 #       define CONFIG_SYS_FLASH_CHECKSUM
 141 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_FLASH_BASE }
 142 #endif
 143
 144 /*-----------------------------------------------------------------------
 145  * Cache Configuration
 146  */
 147 #define CONFIG_SYS_CACHELINE_SIZE       16
 148
 149 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 150                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 151 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 152                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 153 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_DCM)
 154 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_FLASH_BASE | \
 155                                          CF_ADDRMASK(2) | \
 156                                          CF_ACR_EN | CF_ACR_SM_ALL)
 157 #define CONFIG_SYS_CACHE_ACR1           (CONFIG_SYS_SDRAM_BASE | \
 158                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 159                                          CF_ACR_EN | CF_ACR_SM_ALL)
 160 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CEIB | \
 161                                          CF_CACR_DBWE)
 162
 163 /*-----------------------------------------------------------------------
 164  * Memory bank definitions
 165  */
 166
 167 /* CS0 - AMD Flash, address 0xffc00000 */
 168 #define CONFIG_SYS_CS0_BASE             0xffe00000
 169 #define CONFIG_SYS_CS0_CTRL             0x00001980      /* WS=0110, AA=1, PS=10         */
 170 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
 171 #define CONFIG_SYS_CS0_MASK             0x003f0021      /* 4MB, AA=0, WP=0, C/I=1, V=1  */
 172
 173 /* CS1 - FPGA, address 0xe0000000 */
 174 #define CONFIG_SYS_CS1_BASE             0xe0000000
 175 #define CONFIG_SYS_CS1_CTRL             0x00000d80      /* WS=0011, AA=1, PS=10         */
 176 #define CONFIG_SYS_CS1_MASK             0x00010001      /* 128kB, AA=0, WP=0, C/I=0, V=1*/
 177
 178 /*-----------------------------------------------------------------------
 179  * Port configuration
 180  */
 181 #define CONFIG_SYS_GPIO_FUNC            0x00000008      /* Set gpio pins: none          */
 182 #define CONFIG_SYS_GPIO1_FUNC           0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54*/
 183 #define CONFIG_SYS_GPIO_EN              0x00000008      /* Set gpio output enable       */
 184 #define CONFIG_SYS_GPIO1_EN             0x00c70000      /* Set gpio output enable       */
 185 #define CONFIG_SYS_GPIO_OUT             0x00000008      /* Set outputs to default state */
 186 #define CONFIG_SYS_GPIO1_OUT            0x00c70000      /* Set outputs to default state */
 187 #define CONFIG_SYS_GPIO1_LED            0x00400000      /* user led                     */
 188
 189 #endif  /* M5249 */