include/configs/M5253DEMO.h

   1 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   2  * Hayden Fraser (Hayden.Fraser@freescale.com)
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _M5253DEMO_H
   8 #define _M5253DEMO_H
   9
  10 #define CONFIG_MCF52x2          /* define processor family */
  11 #define CONFIG_M5253            /* define processor type */
  12 #define CONFIG_M5253DEMO        /* define board type */
  13
  14 #define CONFIG_MCFTMR
  15
  16 #define CONFIG_MCFUART
  17 #define CONFIG_SYS_UART_PORT            (0)
  18 #define CONFIG_BAUDRATE         115200
  19
  20 #undef CONFIG_WATCHDOG          /* disable watchdog */
  21
  22 #define CONFIG_BOOTDELAY        5
  23
  24 /* Configuration for environment
  25  * Environment is embedded in u-boot in the second sector of the flash
  26  */
  27 #ifdef CONFIG_MONITOR_IS_IN_RAM
  28 #       define CONFIG_ENV_OFFSET                0x4000
  29 #       define CONFIG_ENV_SECT_SIZE     0x1000
  30 #       define CONFIG_ENV_IS_IN_FLASH   1
  31 #else
  32 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x4000)
  33 #       define CONFIG_ENV_SECT_SIZE     0x1000
  34 #       define CONFIG_ENV_IS_IN_FLASH   1
  35 #endif
  36
  37 /*
  38  * Command line configuration.
  39  */
  40 #include <config_cmd_default.h>
  41
  42 #define CONFIG_CMD_CACHE
  43 #define CONFIG_CMD_LOADB
  44 #define CONFIG_CMD_LOADS
  45 #define CONFIG_CMD_EXT2
  46 #define CONFIG_CMD_FAT
  47 #define CONFIG_CMD_IDE
  48 #define CONFIG_CMD_MEMORY
  49 #define CONFIG_CMD_MISC
  50 #define CONFIG_CMD_PING
  51
  52 #ifdef CONFIG_CMD_IDE
  53 /* ATA */
  54 #       define CONFIG_DOS_PARTITION
  55 #       define CONFIG_MAC_PARTITION
  56 #       define CONFIG_IDE_RESET         1
  57 #       define CONFIG_IDE_PREINIT       1
  58 #       define CONFIG_ATAPI
  59 #       undef CONFIG_LBA48
  60
  61 #       define CONFIG_SYS_IDE_MAXBUS            1
  62 #       define CONFIG_SYS_IDE_MAXDEVICE 2
  63
  64 #       define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
  65 #       define CONFIG_SYS_ATA_IDE0_OFFSET       0
  66
  67 #       define CONFIG_SYS_ATA_DATA_OFFSET       0xA0    /* Offset for data I/O */
  68 #       define CONFIG_SYS_ATA_REG_OFFSET        0xA0    /* Offset for normal register accesses */
  69 #       define CONFIG_SYS_ATA_ALT_OFFSET        0xC0    /* Offset for alternate registers */
  70 #       define CONFIG_SYS_ATA_STRIDE            4       /* Interval between registers */
  71 #endif
  72
  73 #define CONFIG_DRIVER_DM9000
  74 #ifdef CONFIG_DRIVER_DM9000
  75 #       define CONFIG_DM9000_BASE       (CONFIG_SYS_CS1_BASE | 0x300)
  76 #       define DM9000_IO                CONFIG_DM9000_BASE
  77 #       define DM9000_DATA              (CONFIG_DM9000_BASE + 4)
  78 #       undef CONFIG_DM9000_DEBUG
  79 #       define CONFIG_DM9000_BYTE_SWAPPED
  80
  81 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
  82
  83 #       define CONFIG_EXTRA_ENV_SETTINGS                \
  84                 "netdev=eth0\0"                         \
  85                 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  86                 "loadaddr=10000\0"                      \
  87                 "u-boot=u-boot.bin\0"                   \
  88                 "load=tftp ${loadaddr) ${u-boot}\0"     \
  89                 "upd=run load; run prog\0"              \
  90                 "prog=prot off 0xff800000 0xff82ffff;"  \
  91                 "era 0xff800000 0xff82ffff;"            \
  92                 "cp.b ${loadaddr} 0xff800000 ${filesize};"      \
  93                 "save\0"                                \
  94                 ""
  95 #endif
  96
  97 #define CONFIG_HOSTNAME         M5253DEMO
  98
  99 /* I2C */
 100 #define CONFIG_SYS_I2C
 101 #define CONFIG_SYS_I2C_FSL
 102 #define CONFIG_SYS_FSL_I2C_SPEED        80000
 103 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 104 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00000280
 105 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 106 #define CONFIG_SYS_I2C_PINMUX_REG       (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
 107 #define CONFIG_SYS_I2C_PINMUX_CLR       (0xFFFFE7FF)
 108 #define CONFIG_SYS_I2C_PINMUX_SET       (0)
 109
 110 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 111
 112 #if defined(CONFIG_CMD_KGDB)
 113 #       define CONFIG_SYS_CBSIZE                1024    /* Console I/O Buffer Size */
 114 #else
 115 #       define CONFIG_SYS_CBSIZE                256     /* Console I/O Buffer Size */
 116 #endif
 117 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 118 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 119 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 120
 121 #define CONFIG_SYS_LOAD_ADDR            0x00100000
 122
 123 #define CONFIG_SYS_MEMTEST_START        0x400
 124 #define CONFIG_SYS_MEMTEST_END          0x380000
 125
 126 #undef CONFIG_SYS_PLL_BYPASS            /* bypass PLL for test purpose */
 127 #define CONFIG_SYS_FAST_CLK
 128 #ifdef CONFIG_SYS_FAST_CLK
 129 #       define CONFIG_SYS_PLLCR 0x1243E054
 130 #       define CONFIG_SYS_CLK           140000000
 131 #else
 132 #       define CONFIG_SYS_PLLCR 0x135a4140
 133 #       define CONFIG_SYS_CLK           70000000
 134 #endif
 135
 136 /*
 137  * Low Level Configuration Settings
 138  * (address mappings, register initial values, etc.)
 139  * You should know what you are doing if you make changes here.
 140  */
 141
 142 #define CONFIG_SYS_MBAR         0x10000000      /* Register Base Addrs */
 143 #define CONFIG_SYS_MBAR2                0x80000000      /* Module Base Addrs 2 */
 144
 145 /*
 146  * Definitions for initial stack pointer and data area (in DPRAM)
 147  */
 148 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 149 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM */
 150 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 151 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 152
 153 /*
 154  * Start addresses for the final memory configuration
 155  * (Set up by the startup code)
 156  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 157  */
 158 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 159 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 160
 161 #ifdef CONFIG_MONITOR_IS_IN_RAM
 162 #       define CONFIG_SYS_MONITOR_BASE  0x20000
 163 #else
 164 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 165 #endif
 166
 167 #define CONFIG_SYS_MONITOR_LEN          0x40000
 168 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 169 #define CONFIG_SYS_BOOTPARAMS_LEN       (64*1024)
 170
 171 /*
 172  * For booting Linux, the board info and command line data
 173  * have to be in the first 8 MB of memory, since this is
 174  * the maximum mapped by the Linux kernel during initialization ??
 175  */
 176 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 177 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 178
 179 /* FLASH organization */
 180 #define CONFIG_SYS_FLASH_BASE           (CONFIG_SYS_CS0_BASE)
 181 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 182 #define CONFIG_SYS_MAX_FLASH_SECT       2048    /* max number of sectors on one chip */
 183 #define CONFIG_SYS_FLASH_ERASE_TOUT     1000
 184
 185 #define FLASH_SST6401B          0x200
 186 #define SST_ID_xF6401B          0x236D236D
 187
 188 #undef CONFIG_SYS_FLASH_CFI
 189 #ifdef CONFIG_SYS_FLASH_CFI
 190 /*
 191  * Unable to use CFI driver, due to incompatible sector erase command by SST.
 192  * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
 193  * 0x30 is block erase in SST
 194  */
 195 #       define CONFIG_FLASH_CFI_DRIVER  1
 196 #       define CONFIG_SYS_FLASH_SIZE            0x800000
 197 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 198 #       define CONFIG_FLASH_CFI_LEGACY
 199 #else
 200 #       define CONFIG_SYS_SST_SECT              2048
 201 #       define CONFIG_SYS_SST_SECTSZ            0x1000
 202 #       define CONFIG_SYS_FLASH_WRITE_TOUT      500
 203 #endif
 204
 205 /* Cache Configuration */
 206 #define CONFIG_SYS_CACHELINE_SIZE       16
 207
 208 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 209                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 210 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 211                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 212 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_DCM)
 213 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_FLASH_BASE | \
 214                                          CF_ADDRMASK(8) | \
 215                                          CF_ACR_EN | CF_ACR_SM_ALL)
 216 #define CONFIG_SYS_CACHE_ACR1           (CONFIG_SYS_SDRAM_BASE | \
 217                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 218                                          CF_ACR_EN | CF_ACR_SM_ALL)
 219 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CEIB | \
 220                                          CF_CACR_DBWE)
 221
 222 /* Port configuration */
 223 #define CONFIG_SYS_FECI2C               0xF0
 224
 225 #define CONFIG_SYS_CS0_BASE             0xFF800000
 226 #define CONFIG_SYS_CS0_MASK             0x007F0021
 227 #define CONFIG_SYS_CS0_CTRL             0x00001D80
 228
 229 #define CONFIG_SYS_CS1_BASE             0xE0000000
 230 #define CONFIG_SYS_CS1_MASK             0x00000001
 231 #define CONFIG_SYS_CS1_CTRL             0x00003DD8
 232
 233 /*-----------------------------------------------------------------------
 234  * Port configuration
 235  */
 236 #define CONFIG_SYS_GPIO_FUNC            0x00000008      /* Set gpio pins: none */
 237 #define CONFIG_SYS_GPIO1_FUNC           0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54 */
 238 #define CONFIG_SYS_GPIO_EN              0x00000008      /* Set gpio output enable */
 239 #define CONFIG_SYS_GPIO1_EN             0x00c70000      /* Set gpio output enable */
 240 #define CONFIG_SYS_GPIO_OUT             0x00000008      /* Set outputs to default state */
 241 #define CONFIG_SYS_GPIO1_OUT            0x00c70000      /* Set outputs to default state */
 242 #define CONFIG_SYS_GPIO1_LED            0x00400000      /* user led */
 243
 244 #endif                          /* _M5253DEMO_H */