include/configs/M5253EVBE.h

   1 /*
   2  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  * Hayden Fraser (Hayden.Fraser@freescale.com)
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _M5253EVBE_H
   9 #define _M5253EVBE_H
  10
  11 #define CONFIG_MCFTMR
  12
  13 #define CONFIG_MCFUART
  14 #define CONFIG_SYS_UART_PORT            (0)
  15
  16 #undef CONFIG_WATCHDOG          /* disable watchdog */
  17
  18
  19 /* Configuration for environment
  20  * Environment is embedded in u-boot in the second sector of the flash
  21  */
  22 #ifndef CONFIG_MONITOR_IS_IN_RAM
  23 #define CONFIG_ENV_OFFSET               0x4000
  24 #define CONFIG_ENV_SECT_SIZE    0x2000
  25 #else
  26 #define CONFIG_ENV_ADDR         0xffe04000
  27 #define CONFIG_ENV_SECT_SIZE    0x2000
  28 #endif
  29
  30 #define LDS_BOARD_TEXT \
  31         . = DEFINED(env_offset) ? env_offset : .; \
  32         env/embedded.o(.text)
  33
  34 /*
  35  * BOOTP options
  36  */
  37 #undef CONFIG_BOOTP_BOOTFILESIZE
  38 #undef CONFIG_BOOTP_BOOTPATH
  39 #undef CONFIG_BOOTP_GATEWAY
  40 #undef CONFIG_BOOTP_HOSTNAME
  41
  42 /*
  43  * Command line configuration.
  44  */
  45
  46 /* ATA */
  47 #define CONFIG_IDE_RESET        1
  48 #define CONFIG_IDE_PREINIT      1
  49 #define CONFIG_ATAPI
  50 #undef CONFIG_LBA48
  51
  52 #define CONFIG_SYS_IDE_MAXBUS           1
  53 #define CONFIG_SYS_IDE_MAXDEVICE        2
  54
  55 #define CONFIG_SYS_ATA_BASE_ADDR        (CONFIG_SYS_MBAR2 + 0x800)
  56 #define CONFIG_SYS_ATA_IDE0_OFFSET      0
  57
  58 #define CONFIG_SYS_ATA_DATA_OFFSET      0xA0    /* Offset for data I/O */
  59 #define CONFIG_SYS_ATA_REG_OFFSET       0xA0    /* Offset for normal register accesses */
  60 #define CONFIG_SYS_ATA_ALT_OFFSET       0xC0    /* Offset for alternate registers */
  61 #define CONFIG_SYS_ATA_STRIDE           4       /* Interval between registers */
  62
  63 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
  64
  65 #define CONFIG_SYS_LOAD_ADDR            0x00100000
  66
  67 #define CONFIG_SYS_MEMTEST_START        0x400
  68 #define CONFIG_SYS_MEMTEST_END          0x380000
  69
  70 #undef CONFIG_SYS_PLL_BYPASS            /* bypass PLL for test purpose */
  71 #define CONFIG_SYS_FAST_CLK
  72 #ifdef CONFIG_SYS_FAST_CLK
  73 #       define CONFIG_SYS_PLLCR 0x1243E054
  74 #       define CONFIG_SYS_CLK           140000000
  75 #else
  76 #       define CONFIG_SYS_PLLCR 0x135a4140
  77 #       define CONFIG_SYS_CLK           70000000
  78 #endif
  79
  80 /*
  81  * Low Level Configuration Settings
  82  * (address mappings, register initial values, etc.)
  83  * You should know what you are doing if you make changes here.
  84  */
  85
  86 #define CONFIG_SYS_MBAR         0x10000000      /* Register Base Addrs */
  87 #define CONFIG_SYS_MBAR2                0x80000000      /* Module Base Addrs 2 */
  88
  89 /*
  90  * Definitions for initial stack pointer and data area (in DPRAM)
  91  */
  92 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  93 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM */
  94 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  95 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  96
  97 /*
  98  * Start addresses for the final memory configuration
  99  * (Set up by the startup code)
 100  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 101  */
 102 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 103 #define CONFIG_SYS_SDRAM_SIZE           8       /* SDRAM size in MB */
 104
 105 #ifdef CONFIG_MONITOR_IS_IN_RAM
 106 #define CONFIG_SYS_MONITOR_BASE 0x20000
 107 #else
 108 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 109 #endif
 110
 111 #define CONFIG_SYS_MONITOR_LEN          0x40000
 112 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 113 #define CONFIG_SYS_BOOTPARAMS_LEN       (64*1024)
 114
 115 /*
 116  * For booting Linux, the board info and command line data
 117  * have to be in the first 8 MB of memory, since this is
 118  * the maximum mapped by the Linux kernel during initialization ??
 119  */
 120 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 121 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 122
 123 /* FLASH organization */
 124 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 125 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 126 #define CONFIG_SYS_MAX_FLASH_SECT       35      /* max number of sectors on one chip */
 127 #define CONFIG_SYS_FLASH_ERASE_TOUT     1000
 128
 129 #define CONFIG_SYS_FLASH_CFI            1
 130 #define CONFIG_FLASH_CFI_DRIVER 1
 131 #define CONFIG_SYS_FLASH_SIZE           0x200000
 132 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 133
 134 /* Cache Configuration */
 135 #define CONFIG_SYS_CACHELINE_SIZE       16
 136
 137 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 138                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 139 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 140                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 141 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_DCM)
 142 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_FLASH_BASE | \
 143                                          CF_ADDRMASK(2) | \
 144                                          CF_ACR_EN | CF_ACR_SM_ALL)
 145 #define CONFIG_SYS_CACHE_ACR1           (CONFIG_SYS_SDRAM_BASE | \
 146                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 147                                          CF_ACR_EN | CF_ACR_SM_ALL)
 148 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CEIB | \
 149                                          CF_CACR_DBWE)
 150
 151 /* Port configuration */
 152 #define CONFIG_SYS_FECI2C               0xF0
 153
 154 #define CONFIG_SYS_CS0_BASE             0xFFE00000
 155 #define CONFIG_SYS_CS0_MASK             0x001F0021
 156 #define CONFIG_SYS_CS0_CTRL             0x00001D80
 157
 158 /*-----------------------------------------------------------------------
 159  * Port configuration
 160  */
 161 #define CONFIG_SYS_GPIO_FUNC            0x00000008      /* Set gpio pins: none */
 162 #define CONFIG_SYS_GPIO1_FUNC           0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54 */
 163 #define CONFIG_SYS_GPIO_EN              0x00000008      /* Set gpio output enable */
 164 #define CONFIG_SYS_GPIO1_EN             0x00c70000      /* Set gpio output enable */
 165 #define CONFIG_SYS_GPIO_OUT             0x00000008      /* Set outputs to default state */
 166 #define CONFIG_SYS_GPIO1_OUT            0x00c70000      /* Set outputs to default state */
 167 #define CONFIG_SYS_GPIO1_LED            0x00400000      /* user led */
 168
 169 #endif                          /* _M5253EVB_H */