include/configs/M5253EVBE.h

   1 /*
   2  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  * Hayden Fraser (Hayden.Fraser@freescale.com)
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _M5253EVBE_H
   9 #define _M5253EVBE_H
  10
  11 #define CONFIG_MCFTMR
  12
  13 #define CONFIG_MCFUART
  14 #define CONFIG_SYS_UART_PORT            (0)
  15
  16 #undef CONFIG_WATCHDOG          /* disable watchdog */
  17
  18
  19 /* Configuration for environment
  20  * Environment is embedded in u-boot in the second sector of the flash
  21  */
  22 #ifndef CONFIG_MONITOR_IS_IN_RAM
  23 #define CONFIG_ENV_OFFSET               0x4000
  24 #define CONFIG_ENV_SECT_SIZE    0x2000
  25 #else
  26 #define CONFIG_ENV_ADDR         0xffe04000
  27 #define CONFIG_ENV_SECT_SIZE    0x2000
  28 #endif
  29
  30 #define LDS_BOARD_TEXT \
  31         . = DEFINED(env_offset) ? env_offset : .; \
  32         env/embedded.o(.text)
  33
  34 /*
  35  * BOOTP options
  36  */
  37 #undef CONFIG_BOOTP_BOOTFILESIZE
  38
  39 /*
  40  * Command line configuration.
  41  */
  42
  43 /* ATA */
  44 #define CONFIG_IDE_RESET        1
  45 #define CONFIG_IDE_PREINIT      1
  46 #define CONFIG_ATAPI
  47 #undef CONFIG_LBA48
  48
  49 #define CONFIG_SYS_IDE_MAXBUS           1
  50 #define CONFIG_SYS_IDE_MAXDEVICE        2
  51
  52 #define CONFIG_SYS_ATA_BASE_ADDR        (CONFIG_SYS_MBAR2 + 0x800)
  53 #define CONFIG_SYS_ATA_IDE0_OFFSET      0
  54
  55 #define CONFIG_SYS_ATA_DATA_OFFSET      0xA0    /* Offset for data I/O */
  56 #define CONFIG_SYS_ATA_REG_OFFSET       0xA0    /* Offset for normal register accesses */
  57 #define CONFIG_SYS_ATA_ALT_OFFSET       0xC0    /* Offset for alternate registers */
  58 #define CONFIG_SYS_ATA_STRIDE           4       /* Interval between registers */
  59
  60 #define CONFIG_SYS_LOAD_ADDR            0x00100000
  61
  62 #define CONFIG_SYS_MEMTEST_START        0x400
  63 #define CONFIG_SYS_MEMTEST_END          0x380000
  64
  65 #undef CONFIG_SYS_PLL_BYPASS            /* bypass PLL for test purpose */
  66 #define CONFIG_SYS_FAST_CLK
  67 #ifdef CONFIG_SYS_FAST_CLK
  68 #       define CONFIG_SYS_PLLCR 0x1243E054
  69 #       define CONFIG_SYS_CLK           140000000
  70 #else
  71 #       define CONFIG_SYS_PLLCR 0x135a4140
  72 #       define CONFIG_SYS_CLK           70000000
  73 #endif
  74
  75 /*
  76  * Low Level Configuration Settings
  77  * (address mappings, register initial values, etc.)
  78  * You should know what you are doing if you make changes here.
  79  */
  80
  81 #define CONFIG_SYS_MBAR         0x10000000      /* Register Base Addrs */
  82 #define CONFIG_SYS_MBAR2                0x80000000      /* Module Base Addrs 2 */
  83
  84 /*
  85  * Definitions for initial stack pointer and data area (in DPRAM)
  86  */
  87 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  88 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM */
  89 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  90 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  91
  92 /*
  93  * Start addresses for the final memory configuration
  94  * (Set up by the startup code)
  95  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  96  */
  97 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  98 #define CONFIG_SYS_SDRAM_SIZE           8       /* SDRAM size in MB */
  99
 100 #ifdef CONFIG_MONITOR_IS_IN_RAM
 101 #define CONFIG_SYS_MONITOR_BASE 0x20000
 102 #else
 103 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 104 #endif
 105
 106 #define CONFIG_SYS_MONITOR_LEN          0x40000
 107 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 108 #define CONFIG_SYS_BOOTPARAMS_LEN       (64*1024)
 109
 110 /*
 111  * For booting Linux, the board info and command line data
 112  * have to be in the first 8 MB of memory, since this is
 113  * the maximum mapped by the Linux kernel during initialization ??
 114  */
 115 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 116 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 117
 118 /* FLASH organization */
 119 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 120 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 121 #define CONFIG_SYS_MAX_FLASH_SECT       35      /* max number of sectors on one chip */
 122 #define CONFIG_SYS_FLASH_ERASE_TOUT     1000
 123
 124 #define CONFIG_SYS_FLASH_CFI            1
 125 #define CONFIG_FLASH_CFI_DRIVER 1
 126 #define CONFIG_SYS_FLASH_SIZE           0x200000
 127 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 128
 129 /* Cache Configuration */
 130 #define CONFIG_SYS_CACHELINE_SIZE       16
 131
 132 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 133                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 134 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 135                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 136 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_DCM)
 137 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_FLASH_BASE | \
 138                                          CF_ADDRMASK(2) | \
 139                                          CF_ACR_EN | CF_ACR_SM_ALL)
 140 #define CONFIG_SYS_CACHE_ACR1           (CONFIG_SYS_SDRAM_BASE | \
 141                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 142                                          CF_ACR_EN | CF_ACR_SM_ALL)
 143 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CEIB | \
 144                                          CF_CACR_DBWE)
 145
 146 /* Port configuration */
 147 #define CONFIG_SYS_FECI2C               0xF0
 148
 149 #define CONFIG_SYS_CS0_BASE             0xFFE00000
 150 #define CONFIG_SYS_CS0_MASK             0x001F0021
 151 #define CONFIG_SYS_CS0_CTRL             0x00001D80
 152
 153 /*-----------------------------------------------------------------------
 154  * Port configuration
 155  */
 156 #define CONFIG_SYS_GPIO_FUNC            0x00000008      /* Set gpio pins: none */
 157 #define CONFIG_SYS_GPIO1_FUNC           0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54 */
 158 #define CONFIG_SYS_GPIO_EN              0x00000008      /* Set gpio output enable */
 159 #define CONFIG_SYS_GPIO1_EN             0x00c70000      /* Set gpio output enable */
 160 #define CONFIG_SYS_GPIO_OUT             0x00000008      /* Set outputs to default state */
 161 #define CONFIG_SYS_GPIO1_OUT            0x00c70000      /* Set outputs to default state */
 162 #define CONFIG_SYS_GPIO1_LED            0x00400000      /* user led */
 163
 164 #endif                          /* _M5253EVB_H */