include/configs/M5253EVBE.h

   1 /*
   2  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  * Hayden Fraser (Hayden.Fraser@freescale.com)
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef _M5253EVBE_H
  25 #define _M5253EVBE_H
  26
  27 #define CONFIG_MCF52x2          /* define processor family */
  28 #define CONFIG_M5253            /* define processor type */
  29 #define CONFIG_M5253EVBE        /* define board type */
  30
  31 #define CONFIG_MCFTMR
  32
  33 #define CONFIG_MCFUART
  34 #define CFG_UART_PORT           (0)
  35 #define CONFIG_BAUDRATE         19200
  36 #define CFG_BAUDRATE_TABLE      { 9600 , 19200 , 38400 , 57600, 115200 }
  37
  38 #undef CONFIG_WATCHDOG          /* disable watchdog */
  39
  40 #define CONFIG_BOOTDELAY        5
  41
  42 /* Configuration for environment
  43  * Environment is embedded in u-boot in the second sector of the flash
  44  */
  45 #ifndef CONFIG_MONITOR_IS_IN_RAM
  46 #define CFG_ENV_OFFSET          0x4000
  47 #define CFG_ENV_SECT_SIZE       0x2000
  48 #define CFG_ENV_IS_IN_FLASH     1
  49 #else
  50 #define CFG_ENV_ADDR            0xffe04000
  51 #define CFG_ENV_SECT_SIZE       0x2000
  52 #define CFG_ENV_IS_IN_FLASH     1
  53 #endif
  54
  55 /*
  56  * BOOTP options
  57  */
  58 #undef CONFIG_BOOTP_BOOTFILESIZE
  59 #undef CONFIG_BOOTP_BOOTPATH
  60 #undef CONFIG_BOOTP_GATEWAY
  61 #undef CONFIG_BOOTP_HOSTNAME
  62
  63 /*
  64  * Command line configuration.
  65  */
  66 #include <config_cmd_default.h>
  67 #undef CONFIG_CMD_NET
  68 #define CONFIG_CMD_LOADB
  69 #define CONFIG_CMD_LOADS
  70 #define CONFIG_CMD_EXT2
  71 #define CONFIG_CMD_FAT
  72 #define CONFIG_CMD_IDE
  73 #define CONFIG_CMD_MEMORY
  74 #define CONFIG_CMD_MISC
  75
  76 /* ATA */
  77 #define CONFIG_DOS_PARTITION
  78 #define CONFIG_MAC_PARTITION
  79 #define CONFIG_IDE_RESET        1
  80 #define CONFIG_IDE_PREINIT      1
  81 #define CONFIG_ATAPI
  82 #undef CONFIG_LBA48
  83
  84 #define CFG_IDE_MAXBUS          1
  85 #define CFG_IDE_MAXDEVICE       2
  86
  87 #define CFG_ATA_BASE_ADDR       (CFG_MBAR2 + 0x800)
  88 #define CFG_ATA_IDE0_OFFSET     0
  89
  90 #define CFG_ATA_DATA_OFFSET     0xA0    /* Offset for data I/O */
  91 #define CFG_ATA_REG_OFFSET      0xA0    /* Offset for normal register accesses */
  92 #define CFG_ATA_ALT_OFFSET      0xC0    /* Offset for alternate registers */
  93 #define CFG_ATA_STRIDE          4       /* Interval between registers */
  94 #define _IO_BASE                0
  95
  96 #define CFG_PROMPT              "=> "
  97 #define CFG_LONGHELP            /* undef to save memory */
  98
  99 #if defined(CONFIG_CMD_KGDB)
 100 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size */
 101 #else
 102 #define CFG_CBSIZE              256     /* Console I/O Buffer Size */
 103 #endif
 104 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 105 #define CFG_MAXARGS             16      /* max number of command args */
 106 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size */
 107
 108 #define CFG_LOAD_ADDR           0x00100000
 109
 110 #define CFG_MEMTEST_START       0x400
 111 #define CFG_MEMTEST_END         0x380000
 112
 113 #define CFG_HZ                  1000
 114
 115 #undef CFG_PLL_BYPASS           /* bypass PLL for test purpose */
 116 #define CFG_FAST_CLK
 117 #ifdef CFG_FAST_CLK
 118 #       define CFG_PLLCR        0x1243E054
 119 #       define CFG_CLK          140000000
 120 #else
 121 #       define CFG_PLLCR        0x135a4140
 122 #       define CFG_CLK          70000000
 123 #endif
 124
 125 /*
 126  * Low Level Configuration Settings
 127  * (address mappings, register initial values, etc.)
 128  * You should know what you are doing if you make changes here.
 129  */
 130
 131 #define CFG_MBAR                0x10000000      /* Register Base Addrs */
 132 #define CFG_MBAR2               0x80000000      /* Module Base Addrs 2 */
 133
 134 /*
 135  * Definitions for initial stack pointer and data area (in DPRAM)
 136  */
 137 #define CFG_INIT_RAM_ADDR       0x20000000
 138 #define CFG_INIT_RAM_END        0x10000 /* End of used area in internal SRAM */
 139 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 140 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 141 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 142
 143 /*
 144  * Start addresses for the final memory configuration
 145  * (Set up by the startup code)
 146  * Please note that CFG_SDRAM_BASE _must_ start at 0
 147  */
 148 #define CFG_SDRAM_BASE          0x00000000
 149 #define CFG_SDRAM_SIZE          16      /* SDRAM size in MB */
 150
 151 #ifdef CONFIG_MONITOR_IS_IN_RAM
 152 #define CFG_MONITOR_BASE        0x20000
 153 #else
 154 #define CFG_MONITOR_BASE        (CFG_FLASH_BASE + 0x400)
 155 #endif
 156
 157 #define CFG_MONITOR_LEN         0x40000
 158 #define CFG_MALLOC_LEN          (256 << 10)
 159 #define CFG_BOOTPARAMS_LEN      (64*1024)
 160
 161 /*
 162  * For booting Linux, the board info and command line data
 163  * have to be in the first 8 MB of memory, since this is
 164  * the maximum mapped by the Linux kernel during initialization ??
 165  */
 166 #define CFG_BOOTMAPSZ           (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
 167
 168 /* FLASH organization */
 169 #define CFG_FLASH_BASE          0xffe00000
 170 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks */
 171 #define CFG_MAX_FLASH_SECT      35      /* max number of sectors on one chip */
 172 #define CFG_FLASH_ERASE_TOUT    1000
 173
 174 #define CFG_FLASH_CFI           1
 175 #define CFG_FLASH_CFI_DRIVER    1
 176 #define CFG_FLASH_SIZE          0x200000
 177 #define CFG_FLASH_CFI_WIDTH     FLASH_CFI_16BIT
 178
 179 /* Cache Configuration */
 180 #define CFG_CACHELINE_SIZE      16
 181
 182 /* Port configuration */
 183 #define CFG_FECI2C              0xF0
 184
 185 #define CFG_CSAR0               0xFFE0
 186 #define CFG_CSMR0               0x001F0021
 187 #define CFG_CSCR0               0x1D80
 188
 189 #define CFG_CSAR1               0
 190 #define CFG_CSMR1               0
 191 #define CFG_CSCR1               0
 192
 193 #define CFG_CSAR2               0
 194 #define CFG_CSMR2               0
 195 #define CFG_CSCR2               0
 196
 197 #define CFG_CSAR3               0
 198 #define CFG_CSMR3               0
 199 #define CFG_CSCR3               0
 200
 201 /*-----------------------------------------------------------------------
 202  * Port configuration
 203  */
 204 #define CFG_GPIO_FUNC           0x00000008      /* Set gpio pins: none */
 205 #define CFG_GPIO1_FUNC          0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54 */
 206 #define CFG_GPIO_EN             0x00000008      /* Set gpio output enable */
 207 #define CFG_GPIO1_EN            0x00c70000      /* Set gpio output enable */
 208 #define CFG_GPIO_OUT            0x00000008      /* Set outputs to default state */
 209 #define CFG_GPIO1_OUT           0x00c70000      /* Set outputs to default state */
 210 #define CFG_GPIO1_LED           0x00400000      /* user led */
 211
 212 #endif                          /* _M5253EVB_H */