include/configs/M5272C3.h

   1 /*
   2  * Configuation settings for the Motorola MC5272C3 board.
   3  *
   4  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * board/config.h - configuration options, board specific
  27  */
  28
  29 #ifndef _M5272C3_H
  30 #define _M5272C3_H
  31
  32 /*
  33  * High Level Configuration Options
  34  * (easy to change)
  35  */
  36 #define CONFIG_MCF52x2          /* define processor family */
  37 #define CONFIG_M5272            /* define processor type */
  38
  39 #define CONFIG_MCFTMR
  40
  41 #define CONFIG_MCFUART
  42 #define CONFIG_SYS_UART_PORT            (0)
  43 #define CONFIG_BAUDRATE         115200
  44 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600 , 19200 , 38400 , 57600, 115200 }
  45
  46 #undef CONFIG_WATCHDOG
  47 #define CONFIG_WATCHDOG_TIMEOUT 10000   /* timeout in milliseconds */
  48
  49 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
  50
  51 /* Configuration for environment
  52  * Environment is embedded in u-boot in the second sector of the flash
  53  */
  54 #ifndef CONFIG_MONITOR_IS_IN_RAM
  55 #define CONFIG_ENV_OFFSET               0x4000
  56 #define CONFIG_ENV_SECT_SIZE    0x2000
  57 #define CONFIG_ENV_IS_IN_FLASH  1
  58 #else
  59 #define CONFIG_ENV_ADDR         0xffe04000
  60 #define CONFIG_ENV_SECT_SIZE    0x2000
  61 #define CONFIG_ENV_IS_IN_FLASH  1
  62 #endif
  63
  64 /*
  65  * BOOTP options
  66  */
  67 #define CONFIG_BOOTP_BOOTFILESIZE
  68 #define CONFIG_BOOTP_BOOTPATH
  69 #define CONFIG_BOOTP_GATEWAY
  70 #define CONFIG_BOOTP_HOSTNAME
  71
  72 /*
  73  * Command line configuration.
  74  */
  75 #include <config_cmd_default.h>
  76
  77 #define CONFIG_CMD_CACHE
  78 #define CONFIG_CMD_MII
  79 #define CONFIG_CMD_NET
  80 #define CONFIG_CMD_PING
  81 #define CONFIG_CMD_MISC
  82 #define CONFIG_CMD_ELF
  83 #define CONFIG_CMD_FLASH
  84 #define CONFIG_CMD_MEMORY
  85
  86 #undef CONFIG_CMD_LOADS
  87 #undef CONFIG_CMD_LOADB
  88
  89 #define CONFIG_BOOTDELAY        5
  90 #define CONFIG_MCFFEC
  91 #ifdef CONFIG_MCFFEC
  92 #       define CONFIG_NET_MULTI         1
  93 #       define CONFIG_MII               1
  94 #       define CONFIG_MII_INIT          1
  95 #       define CONFIG_SYS_DISCOVER_PHY
  96 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  97 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  98
  99 #       define CONFIG_SYS_FEC0_PINMUX           0
 100 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
 101 #       define MCFFEC_TOUT_LOOP         50000
 102 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
 103 #       ifndef CONFIG_SYS_DISCOVER_PHY
 104 #               define FECDUPLEX        FULL
 105 #               define FECSPEED         _100BASET
 106 #       else
 107 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 108 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 109 #               endif
 110 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
 111 #endif
 112
 113 #ifdef CONFIG_MCFFEC
 114 #       define CONFIG_ETHADDR   00:e0:0c:bc:e5:60
 115 #       define CONFIG_IPADDR    192.162.1.2
 116 #       define CONFIG_NETMASK   255.255.255.0
 117 #       define CONFIG_SERVERIP  192.162.1.1
 118 #       define CONFIG_GATEWAYIP 192.162.1.1
 119 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
 120 #endif                          /* CONFIG_MCFFEC */
 121
 122 #define CONFIG_HOSTNAME         M5272C3
 123 #define CONFIG_EXTRA_ENV_SETTINGS               \
 124         "netdev=eth0\0"                         \
 125         "loadaddr=10000\0"                      \
 126         "u-boot=u-boot.bin\0"                   \
 127         "load=tftp ${loadaddr) ${u-boot}\0"     \
 128         "upd=run load; run prog\0"              \
 129         "prog=prot off ffe00000 ffe3ffff;"      \
 130         "era ffe00000 ffe3ffff;"                \
 131         "cp.b ${loadaddr} ffe00000 ${filesize};"\
 132         "save\0"                                \
 133         ""
 134
 135 #define CONFIG_SYS_PROMPT               "-> "
 136 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 137
 138 #if defined(CONFIG_CMD_KGDB)
 139 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 140 #else
 141 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 142 #endif
 143
 144 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 145 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 146 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 147 #define CONFIG_SYS_LOAD_ADDR            0x20000
 148 #define CONFIG_SYS_MEMTEST_START        0x400
 149 #define CONFIG_SYS_MEMTEST_END          0x380000
 150 #define CONFIG_SYS_HZ                   1000
 151 #define CONFIG_SYS_CLK                  66000000
 152
 153 /*
 154  * Low Level Configuration Settings
 155  * (address mappings, register initial values, etc.)
 156  * You should know what you are doing if you make changes here.
 157  */
 158 #define CONFIG_SYS_MBAR         0x10000000      /* Register Base Addrs */
 159 #define CONFIG_SYS_SCR                  0x0003
 160 #define CONFIG_SYS_SPR                  0xffff
 161
 162 /*-----------------------------------------------------------------------
 163  * Definitions for initial stack pointer and data area (in DPRAM)
 164  */
 165 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 166 #define CONFIG_SYS_INIT_RAM_END 0x1000  /* End of used area in internal SRAM    */
 167 #define CONFIG_SYS_GBL_DATA_SIZE        64      /* size in bytes reserved for initial data */
 168 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 169 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 170
 171 /*-----------------------------------------------------------------------
 172  * Start addresses for the final memory configuration
 173  * (Set up by the startup code)
 174  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 175  */
 176 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 177 #define CONFIG_SYS_SDRAM_SIZE           4       /* SDRAM size in MB */
 178 #define CONFIG_SYS_FLASH_BASE           0xffe00000
 179
 180 #ifdef  CONFIG_MONITOR_IS_IN_RAM
 181 #define CONFIG_SYS_MONITOR_BASE 0x20000
 182 #else
 183 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 184 #endif
 185
 186 #define CONFIG_SYS_MONITOR_LEN          0x20000
 187 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 188 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 189
 190 /*
 191  * For booting Linux, the board info and command line data
 192  * have to be in the first 8 MB of memory, since this is
 193  * the maximum mapped by the Linux kernel during initialization ??
 194  */
 195 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 196
 197 /*
 198  * FLASH organization
 199  */
 200 #define CONFIG_SYS_FLASH_CFI
 201 #ifdef CONFIG_SYS_FLASH_CFI
 202 #       define CONFIG_FLASH_CFI_DRIVER  1
 203 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
 204 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 205 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 206 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 207 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 208 #endif
 209
 210 /*-----------------------------------------------------------------------
 211  * Cache Configuration
 212  */
 213 #define CONFIG_SYS_CACHELINE_SIZE       16
 214
 215 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 216                                          CONFIG_SYS_INIT_RAM_END - 8)
 217 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 218                                          CONFIG_SYS_INIT_RAM_END - 4)
 219 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 220 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 221                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 222                                          CF_ACR_EN | CF_ACR_SM_ALL)
 223 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 224                                          CF_CACR_DISD | CF_CACR_INVI | \
 225                                          CF_CACR_CEIB | CF_CACR_DCM | \
 226                                          CF_CACR_EUSP)
 227
 228 /*-----------------------------------------------------------------------
 229  * Memory bank definitions
 230  */
 231 #define CONFIG_SYS_BR0_PRELIM           0xFFE00201
 232 #define CONFIG_SYS_OR0_PRELIM           0xFFE00014
 233 #define CONFIG_SYS_BR1_PRELIM           0
 234 #define CONFIG_SYS_OR1_PRELIM           0
 235 #define CONFIG_SYS_BR2_PRELIM           0x30000001
 236 #define CONFIG_SYS_OR2_PRELIM           0xFFF80000
 237 #define CONFIG_SYS_BR3_PRELIM           0
 238 #define CONFIG_SYS_OR3_PRELIM           0
 239 #define CONFIG_SYS_BR4_PRELIM           0
 240 #define CONFIG_SYS_OR4_PRELIM           0
 241 #define CONFIG_SYS_BR5_PRELIM           0
 242 #define CONFIG_SYS_OR5_PRELIM           0
 243 #define CONFIG_SYS_BR6_PRELIM           0
 244 #define CONFIG_SYS_OR6_PRELIM           0
 245 #define CONFIG_SYS_BR7_PRELIM           0x00000701
 246 #define CONFIG_SYS_OR7_PRELIM           0xFFC0007C
 247
 248 /*-----------------------------------------------------------------------
 249  * Port configuration
 250  */
 251 #define CONFIG_SYS_PACNT                0x00000000
 252 #define CONFIG_SYS_PADDR                0x0000
 253 #define CONFIG_SYS_PADAT                0x0000
 254 #define CONFIG_SYS_PBCNT                0x55554155      /* Ethernet/UART configuration */
 255 #define CONFIG_SYS_PBDDR                0x0000
 256 #define CONFIG_SYS_PBDAT                0x0000
 257 #define CONFIG_SYS_PDCNT                0x00000000
 258 #endif                          /* _M5272C3_H */