include/configs/M5282EVB.h

   1 /*
   2  * Configuation settings for the Motorola MC5282EVB board.
   3  *
   4  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * board/config.h - configuration options, board specific
  11  */
  12
  13 #ifndef _CONFIG_M5282EVB_H
  14 #define _CONFIG_M5282EVB_H
  15
  16 /*
  17  * High Level Configuration Options
  18  * (easy to change)
  19  */
  20 #define CONFIG_MCFTMR
  21
  22 #define CONFIG_MCFUART
  23 #define CONFIG_SYS_UART_PORT            (0)
  24 #define CONFIG_BAUDRATE         115200
  25
  26 #undef  CONFIG_MONITOR_IS_IN_RAM        /* define if monitor is started from a pre-loader */
  27
  28 /* Configuration for environment
  29  * Environment is embedded in u-boot in the second sector of the flash
  30  */
  31 #define CONFIG_ENV_ADDR         0xffe04000
  32 #define CONFIG_ENV_SIZE         0x2000
  33 #define CONFIG_ENV_IS_IN_FLASH  1
  34
  35 #define LDS_BOARD_TEXT \
  36         . = DEFINED(env_offset) ? env_offset : .; \
  37         common/env_embedded.o (.text*);
  38
  39 /*
  40  * BOOTP options
  41  */
  42 #define CONFIG_BOOTP_BOOTFILESIZE
  43 #define CONFIG_BOOTP_BOOTPATH
  44 #define CONFIG_BOOTP_GATEWAY
  45 #define CONFIG_BOOTP_HOSTNAME
  46
  47 /*
  48  * Command line configuration.
  49  */
  50 #include <config_cmd_default.h>
  51 #define CONFIG_CMD_CACHE
  52 #define CONFIG_CMD_NET
  53 #define CONFIG_CMD_PING
  54 #define CONFIG_CMD_MII
  55
  56 #undef CONFIG_CMD_LOADS
  57 #undef CONFIG_CMD_LOADB
  58
  59 #define CONFIG_MCFFEC
  60 #ifdef CONFIG_MCFFEC
  61 #       define CONFIG_MII               1
  62 #       define CONFIG_MII_INIT          1
  63 #       define CONFIG_SYS_DISCOVER_PHY
  64 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  65 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  66
  67 #       define CONFIG_SYS_FEC0_PINMUX           0
  68 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  69 #       define MCFFEC_TOUT_LOOP         50000
  70 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  71 #       ifndef CONFIG_SYS_DISCOVER_PHY
  72 #               define FECDUPLEX        FULL
  73 #               define FECSPEED         _100BASET
  74 #       else
  75 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  76 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  77 #               endif
  78 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  79 #endif
  80
  81 #define CONFIG_BOOTDELAY        5
  82 #ifdef CONFIG_MCFFEC
  83 #       define CONFIG_IPADDR    192.162.1.2
  84 #       define CONFIG_NETMASK   255.255.255.0
  85 #       define CONFIG_SERVERIP  192.162.1.1
  86 #       define CONFIG_GATEWAYIP 192.162.1.1
  87 #endif                          /* CONFIG_MCFFEC */
  88
  89 #define CONFIG_HOSTNAME         M5282EVB
  90 #define CONFIG_EXTRA_ENV_SETTINGS               \
  91         "netdev=eth0\0"                         \
  92         "loadaddr=10000\0"                      \
  93         "u-boot=u-boot.bin\0"                   \
  94         "load=tftp ${loadaddr) ${u-boot}\0"     \
  95         "upd=run load; run prog\0"              \
  96         "prog=prot off ffe00000 ffe3ffff;"      \
  97         "era ffe00000 ffe3ffff;"                \
  98         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  99         "save\0"                                \
 100         ""
 101
 102 #define CONFIG_SYS_PROMPT               "-> "
 103 #define CONFIG_SYS_LONGHELP             /* undef to save memory         */
 104
 105 #if defined(CONFIG_CMD_KGDB)
 106 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 107 #else
 108 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 109 #endif
 110 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 111 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 112 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 113
 114 #define CONFIG_SYS_LOAD_ADDR            0x20000
 115
 116 #define CONFIG_SYS_MEMTEST_START        0x400
 117 #define CONFIG_SYS_MEMTEST_END          0x380000
 118
 119 #define CONFIG_SYS_CLK                  64000000
 120
 121 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
 122
 123 #define CONFIG_SYS_MFD                  0x02    /* PLL Multiplication Factor Devider */
 124 #define CONFIG_SYS_RFD                  0x00    /* PLL Reduce Frecuency Devider */
 125
 126 /*
 127  * Low Level Configuration Settings
 128  * (address mappings, register initial values, etc.)
 129  * You should know what you are doing if you make changes here.
 130  */
 131 #define CONFIG_SYS_MBAR         0x40000000
 132
 133 /*-----------------------------------------------------------------------
 134  * Definitions for initial stack pointer and data area (in DPRAM)
 135  */
 136 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 137 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM    */
 138 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 139 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 140
 141 /*-----------------------------------------------------------------------
 142  * Start addresses for the final memory configuration
 143  * (Set up by the startup code)
 144  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 145  */
 146 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 147 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 148 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 149 #define CONFIG_SYS_INT_FLASH_BASE       0xf0000000
 150 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 151
 152 /* If M5282 port is fully implemented the monitor base will be behind
 153  * the vector table. */
 154 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
 155 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 156 #else
 157 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418)  /* 24 Byte for CFM-Config */
 158 #endif
 159
 160 #define CONFIG_SYS_MONITOR_LEN          0x20000
 161 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 162 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 163
 164 /*
 165  * For booting Linux, the board info and command line data
 166  * have to be in the first 8 MB of memory, since this is
 167  * the maximum mapped by the Linux kernel during initialization ??
 168  */
 169 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 170
 171 /*-----------------------------------------------------------------------
 172  * FLASH organization
 173  */
 174 #define CONFIG_SYS_FLASH_CFI
 175 #ifdef CONFIG_SYS_FLASH_CFI
 176
 177 #       define CONFIG_FLASH_CFI_DRIVER  1
 178 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 179 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 180 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 181 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 182 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 183 #       define CONFIG_SYS_FLASH_CHECKSUM
 184 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_FLASH_BASE }
 185 #endif
 186
 187 /*-----------------------------------------------------------------------
 188  * Cache Configuration
 189  */
 190 #define CONFIG_SYS_CACHELINE_SIZE       16
 191
 192 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 193                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 194 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 195                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 196 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 197 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 198                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 199                                          CF_ACR_EN | CF_ACR_SM_ALL)
 200 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 201                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 202                                          CF_CACR_EUSP)
 203
 204 /*-----------------------------------------------------------------------
 205  * Memory bank definitions
 206  */
 207 #define CONFIG_SYS_CS0_BASE             0xFFE00000
 208 #define CONFIG_SYS_CS0_CTRL             0x00001980
 209 #define CONFIG_SYS_CS0_MASK             0x001F0001
 210
 211 /*-----------------------------------------------------------------------
 212  * Port configuration
 213  */
 214 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 215 #define CONFIG_SYS_PADDR                0x0000000
 216 #define CONFIG_SYS_PADAT                0x0000000
 217
 218 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 219 #define CONFIG_SYS_PBDDR                0x0000000
 220 #define CONFIG_SYS_PBDAT                0x0000000
 221
 222 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 223 #define CONFIG_SYS_PCDDR                0x0000000
 224 #define CONFIG_SYS_PCDAT                0x0000000
 225
 226 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 227 #define CONFIG_SYS_PCDDR                0x0000000
 228 #define CONFIG_SYS_PCDAT                0x0000000
 229
 230 #define CONFIG_SYS_PEHLPAR              0xC0
 231 #define CONFIG_SYS_PUAPAR               0x0F    /* UA0..UA3 = Uart 0 +1 */
 232 #define CONFIG_SYS_DDRUA                0x05
 233 #define CONFIG_SYS_PJPAR                0xFF
 234
 235 #endif                          /* _CONFIG_M5282EVB_H */