include/configs/M5282EVB.h

   1 /*
   2  * Configuation settings for the Motorola MC5282EVB board.
   3  *
   4  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * board/config.h - configuration options, board specific
  11  */
  12
  13 #ifndef _CONFIG_M5282EVB_H
  14 #define _CONFIG_M5282EVB_H
  15
  16 /*
  17  * High Level Configuration Options
  18  * (easy to change)
  19  */
  20 #define CONFIG_MCFTMR
  21
  22 #define CONFIG_MCFUART
  23 #define CONFIG_SYS_UART_PORT            (0)
  24 #define CONFIG_BAUDRATE         115200
  25
  26 #undef  CONFIG_MONITOR_IS_IN_RAM        /* define if monitor is started from a pre-loader */
  27
  28 /* Configuration for environment
  29  * Environment is embedded in u-boot in the second sector of the flash
  30  */
  31 #define CONFIG_ENV_ADDR         0xffe04000
  32 #define CONFIG_ENV_SIZE         0x2000
  33 #define CONFIG_ENV_IS_IN_FLASH  1
  34
  35 #define LDS_BOARD_TEXT \
  36         . = DEFINED(env_offset) ? env_offset : .; \
  37         common/env_embedded.o (.text*);
  38
  39 /*
  40  * BOOTP options
  41  */
  42 #define CONFIG_BOOTP_BOOTFILESIZE
  43 #define CONFIG_BOOTP_BOOTPATH
  44 #define CONFIG_BOOTP_GATEWAY
  45 #define CONFIG_BOOTP_HOSTNAME
  46
  47 /*
  48  * Command line configuration.
  49  */
  50
  51 #define CONFIG_MCFFEC
  52 #ifdef CONFIG_MCFFEC
  53 #       define CONFIG_MII               1
  54 #       define CONFIG_MII_INIT          1
  55 #       define CONFIG_SYS_DISCOVER_PHY
  56 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  57 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  58
  59 #       define CONFIG_SYS_FEC0_PINMUX           0
  60 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  61 #       define MCFFEC_TOUT_LOOP         50000
  62 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  63 #       ifndef CONFIG_SYS_DISCOVER_PHY
  64 #               define FECDUPLEX        FULL
  65 #               define FECSPEED         _100BASET
  66 #       else
  67 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  68 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  69 #               endif
  70 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  71 #endif
  72
  73 #ifdef CONFIG_MCFFEC
  74 #       define CONFIG_IPADDR    192.162.1.2
  75 #       define CONFIG_NETMASK   255.255.255.0
  76 #       define CONFIG_SERVERIP  192.162.1.1
  77 #       define CONFIG_GATEWAYIP 192.162.1.1
  78 #endif                          /* CONFIG_MCFFEC */
  79
  80 #define CONFIG_HOSTNAME         M5282EVB
  81 #define CONFIG_EXTRA_ENV_SETTINGS               \
  82         "netdev=eth0\0"                         \
  83         "loadaddr=10000\0"                      \
  84         "u-boot=u-boot.bin\0"                   \
  85         "load=tftp ${loadaddr) ${u-boot}\0"     \
  86         "upd=run load; run prog\0"              \
  87         "prog=prot off ffe00000 ffe3ffff;"      \
  88         "era ffe00000 ffe3ffff;"                \
  89         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  90         "save\0"                                \
  91         ""
  92
  93 #define CONFIG_SYS_LONGHELP             /* undef to save memory         */
  94
  95 #if defined(CONFIG_CMD_KGDB)
  96 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
  97 #else
  98 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
  99 #endif
 100 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 101 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 102 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 103
 104 #define CONFIG_SYS_LOAD_ADDR            0x20000
 105
 106 #define CONFIG_SYS_MEMTEST_START        0x400
 107 #define CONFIG_SYS_MEMTEST_END          0x380000
 108
 109 #define CONFIG_SYS_CLK                  64000000
 110
 111 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
 112
 113 #define CONFIG_SYS_MFD                  0x02    /* PLL Multiplication Factor Devider */
 114 #define CONFIG_SYS_RFD                  0x00    /* PLL Reduce Frecuency Devider */
 115
 116 /*
 117  * Low Level Configuration Settings
 118  * (address mappings, register initial values, etc.)
 119  * You should know what you are doing if you make changes here.
 120  */
 121 #define CONFIG_SYS_MBAR         0x40000000
 122
 123 /*-----------------------------------------------------------------------
 124  * Definitions for initial stack pointer and data area (in DPRAM)
 125  */
 126 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 127 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM    */
 128 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 129 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 130
 131 /*-----------------------------------------------------------------------
 132  * Start addresses for the final memory configuration
 133  * (Set up by the startup code)
 134  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 135  */
 136 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 137 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 138 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 139 #define CONFIG_SYS_INT_FLASH_BASE       0xf0000000
 140 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 141
 142 /* If M5282 port is fully implemented the monitor base will be behind
 143  * the vector table. */
 144 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
 145 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 146 #else
 147 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418)  /* 24 Byte for CFM-Config */
 148 #endif
 149
 150 #define CONFIG_SYS_MONITOR_LEN          0x20000
 151 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 152 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 153
 154 /*
 155  * For booting Linux, the board info and command line data
 156  * have to be in the first 8 MB of memory, since this is
 157  * the maximum mapped by the Linux kernel during initialization ??
 158  */
 159 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 160
 161 /*-----------------------------------------------------------------------
 162  * FLASH organization
 163  */
 164 #define CONFIG_SYS_FLASH_CFI
 165 #ifdef CONFIG_SYS_FLASH_CFI
 166
 167 #       define CONFIG_FLASH_CFI_DRIVER  1
 168 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 169 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 170 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 171 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 172 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 173 #       define CONFIG_SYS_FLASH_CHECKSUM
 174 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_FLASH_BASE }
 175 #endif
 176
 177 /*-----------------------------------------------------------------------
 178  * Cache Configuration
 179  */
 180 #define CONFIG_SYS_CACHELINE_SIZE       16
 181
 182 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 183                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 184 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 185                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 186 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 187 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 188                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 189                                          CF_ACR_EN | CF_ACR_SM_ALL)
 190 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 191                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 192                                          CF_CACR_EUSP)
 193
 194 /*-----------------------------------------------------------------------
 195  * Memory bank definitions
 196  */
 197 #define CONFIG_SYS_CS0_BASE             0xFFE00000
 198 #define CONFIG_SYS_CS0_CTRL             0x00001980
 199 #define CONFIG_SYS_CS0_MASK             0x001F0001
 200
 201 /*-----------------------------------------------------------------------
 202  * Port configuration
 203  */
 204 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 205 #define CONFIG_SYS_PADDR                0x0000000
 206 #define CONFIG_SYS_PADAT                0x0000000
 207
 208 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 209 #define CONFIG_SYS_PBDDR                0x0000000
 210 #define CONFIG_SYS_PBDAT                0x0000000
 211
 212 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 213 #define CONFIG_SYS_PCDDR                0x0000000
 214 #define CONFIG_SYS_PCDAT                0x0000000
 215
 216 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 217 #define CONFIG_SYS_PCDDR                0x0000000
 218 #define CONFIG_SYS_PCDAT                0x0000000
 219
 220 #define CONFIG_SYS_PEHLPAR              0xC0
 221 #define CONFIG_SYS_PUAPAR               0x0F    /* UA0..UA3 = Uart 0 +1 */
 222 #define CONFIG_SYS_DDRUA                0x05
 223 #define CONFIG_SYS_PJPAR                0xFF
 224
 225 #endif                          /* _CONFIG_M5282EVB_H */