include/configs/M53017EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF53017EVB.
   3  *
   4  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M53017EVB_H
  15 #define _M53017EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21
  22 #define CONFIG_MCFUART
  23 #define CONFIG_SYS_UART_PORT            (0)
  24 #define CONFIG_BAUDRATE                 115200
  25
  26 #undef CONFIG_WATCHDOG
  27 #define CONFIG_WATCHDOG_TIMEOUT         5000
  28
  29 /* Command line configuration */
  30 #define CONFIG_CMD_DATE
  31 #define CONFIG_CMD_REGINFO
  32
  33 #define CONFIG_SYS_UNIFY_CACHE
  34
  35 #define CONFIG_MCFFEC
  36 #ifdef CONFIG_MCFFEC
  37 #       define CONFIG_MII               1
  38 #       define CONFIG_MII_INIT          1
  39 #       define CONFIG_SYS_DISCOVER_PHY
  40 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  41 #       define CONFIG_SYS_TX_ETH_BUFFER 8
  42 #       define CONFIG_SYS_FEC_BUF_USE_SRAM
  43 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  44 #       define CONFIG_HAS_ETH1
  45
  46 #       define CONFIG_SYS_FEC0_PINMUX   0
  47 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  48 #       define CONFIG_SYS_FEC1_PINMUX   0
  49 #       define CONFIG_SYS_FEC1_MIIBASE  CONFIG_SYS_FEC1_IOBASE
  50 #       define MCFFEC_TOUT_LOOP         50000
  51
  52 #       define CONFIG_BOOTARGS          "root=/dev/mtdblock3 rw rootfstype=jffs2"
  53
  54 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  55 #       ifndef CONFIG_SYS_DISCOVER_PHY
  56 #               define FECDUPLEX        FULL
  57 #               define FECSPEED         _100BASET
  58 #       else
  59 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  60 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  61 #               endif
  62 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  63 #endif
  64
  65 #define CONFIG_MCFRTC
  66 #undef RTC_DEBUG
  67 #define CONFIG_SYS_RTC_CNT              (0x8000)
  68 #define CONFIG_SYS_RTC_SETUP            (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
  69
  70 /* Timer */
  71 #define CONFIG_MCFTMR
  72 #undef CONFIG_MCFPIT
  73
  74 /* I2C */
  75 #define CONFIG_SYS_I2C
  76 #define CONFIG_SYS_I2C_FSL
  77 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  78 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  79 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
  80 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
  81
  82 #define CONFIG_UDP_CHECKSUM
  83
  84 #ifdef CONFIG_MCFFEC
  85 #       define CONFIG_IPADDR    192.162.1.2
  86 #       define CONFIG_NETMASK   255.255.255.0
  87 #       define CONFIG_SERVERIP  192.162.1.1
  88 #       define CONFIG_GATEWAYIP 192.162.1.1
  89 #endif                          /* FEC_ENET */
  90
  91 #define CONFIG_HOSTNAME         M53017
  92 #define CONFIG_EXTRA_ENV_SETTINGS               \
  93         "netdev=eth0\0"                         \
  94         "loadaddr=40010000\0"                   \
  95         "u-boot=u-boot.bin\0"                   \
  96         "load=tftp ${loadaddr) ${u-boot}\0"     \
  97         "upd=run load; run prog\0"              \
  98         "prog=prot off 0 3ffff;"                \
  99         "era 0 3ffff;"                          \
 100         "cp.b ${loadaddr} 0 ${filesize};"       \
 101         "save\0"                                \
 102         ""
 103
 104 #define CONFIG_PRAM             512     /* 512 KB */
 105 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
 106
 107 #ifdef CONFIG_CMD_KGDB
 108 #       define CONFIG_SYS_CBSIZE        1024    /* Console I/O Buffer Size */
 109 #else
 110 #       define CONFIG_SYS_CBSIZE        256     /* Console I/O Buffer Size */
 111 #endif
 112
 113 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 114 #define CONFIG_SYS_MAXARGS      16              /* max number of cmd args */
 115 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Arg Buf Sz */
 116 #define CONFIG_SYS_LOAD_ADDR    0x40010000
 117
 118 #define CONFIG_SYS_CLK          80000000
 119 #define CONFIG_SYS_CPU_CLK      CONFIG_SYS_CLK * 3
 120
 121 #define CONFIG_SYS_MBAR         0xFC000000
 122
 123 /*
 124  * Low Level Configuration Settings
 125  * (address mappings, register initial values, etc.)
 126  * You should know what you are doing if you make changes here.
 127  */
 128 /*
 129  * Definitions for initial stack pointer and data area (in DPRAM)
 130  */
 131 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 132 #define CONFIG_SYS_INIT_RAM_SIZE                0x20000 /* Size of used area in internal SRAM */
 133 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 134 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 135 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 136
 137 /*
 138  * Start addresses for the final memory configuration
 139  * (Set up by the startup code)
 140  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 141  */
 142 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 143 #define CONFIG_SYS_SDRAM_SIZE           64      /* SDRAM size in MB */
 144 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
 145 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 146 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
 147 #define CONFIG_SYS_SDRAM_EMOD           0x80010000
 148 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 149
 150 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 151 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 152
 153 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_FLASH_BASE + 0x400)
 154 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 155
 156 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 157 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 158
 159 /*
 160  * For booting Linux, the board info and command line data
 161  * have to be in the first 8 MB of memory, since this is
 162  * the maximum mapped by the Linux kernel during initialization ??
 163  */
 164 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 165 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 166
 167 /*-----------------------------------------------------------------------
 168  * FLASH organization
 169  */
 170 #define CONFIG_SYS_FLASH_CFI
 171 #ifdef CONFIG_SYS_FLASH_CFI
 172 #       define CONFIG_FLASH_CFI_DRIVER          1
 173 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 174 #       define CONFIG_FLASH_SPANSION_S29WS_N    1
 175 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 176 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 177 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 178 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 179 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 180 #endif
 181
 182 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 183
 184 /* Configuration for environment
 185  * Environment is embedded in u-boot in the second sector of the flash
 186  */
 187 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_FLASH_BASE + 0x40000)
 188 #define CONFIG_ENV_SIZE                 0x1000
 189 #define CONFIG_ENV_SECT_SIZE            0x8000
 190 #define CONFIG_ENV_IS_IN_FLASH          1
 191
 192 #define LDS_BOARD_TEXT \
 193         . = DEFINED(env_offset) ? env_offset : .; \
 194         common/env_embedded.o       (.text*)
 195
 196 /*-----------------------------------------------------------------------
 197  * Cache Configuration
 198  */
 199 #define CONFIG_SYS_CACHELINE_SIZE       16
 200
 201 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 202                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 203 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 204                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 205 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
 206 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 207                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 208                                          CF_ACR_EN | CF_ACR_SM_ALL)
 209 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_EC | CF_CACR_CINVA | \
 210                                          CF_CACR_DCM_P)
 211
 212 /*-----------------------------------------------------------------------
 213  * Chipselect bank definitions
 214  */
 215 /*
 216  * CS0 - NOR Flash
 217  * CS1 - Ext SRAM
 218  * CS2 - Available
 219  * CS3 - Available
 220  * CS4 - Available
 221  * CS5 - Available
 222  */
 223 #define CONFIG_SYS_CS0_BASE             0
 224 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 225 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 226
 227 #define CONFIG_SYS_CS1_BASE             0xC0000000
 228 #define CONFIG_SYS_CS1_MASK             0x00070001
 229 #define CONFIG_SYS_CS1_CTRL             0x00001FA0
 230
 231 #endif                          /* _M53017EVB_H */