include/configs/M53017EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF53017EVB.
   3  *
   4  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M53017EVB_H
  15 #define _M53017EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21
  22 #define CONFIG_MCFUART
  23 #define CONFIG_SYS_UART_PORT            (0)
  24 #define CONFIG_BAUDRATE                 115200
  25
  26 #undef CONFIG_WATCHDOG
  27 #define CONFIG_WATCHDOG_TIMEOUT         5000
  28
  29 /* Command line configuration */
  30 #define CONFIG_CMD_CACHE
  31 #define CONFIG_CMD_DATE
  32 #undef CONFIG_CMD_I2C
  33 #define CONFIG_CMD_MII
  34 #define CONFIG_CMD_PING
  35 #define CONFIG_CMD_REGINFO
  36
  37 #define CONFIG_SYS_UNIFY_CACHE
  38
  39 #define CONFIG_MCFFEC
  40 #ifdef CONFIG_MCFFEC
  41 #       define CONFIG_MII               1
  42 #       define CONFIG_MII_INIT          1
  43 #       define CONFIG_SYS_DISCOVER_PHY
  44 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  45 #       define CONFIG_SYS_TX_ETH_BUFFER 8
  46 #       define CONFIG_SYS_FEC_BUF_USE_SRAM
  47 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  48 #       define CONFIG_HAS_ETH1
  49
  50 #       define CONFIG_SYS_FEC0_PINMUX   0
  51 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  52 #       define CONFIG_SYS_FEC1_PINMUX   0
  53 #       define CONFIG_SYS_FEC1_MIIBASE  CONFIG_SYS_FEC1_IOBASE
  54 #       define MCFFEC_TOUT_LOOP         50000
  55
  56 #       define CONFIG_BOOTARGS          "root=/dev/mtdblock3 rw rootfstype=jffs2"
  57
  58 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  59 #       ifndef CONFIG_SYS_DISCOVER_PHY
  60 #               define FECDUPLEX        FULL
  61 #               define FECSPEED         _100BASET
  62 #       else
  63 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  64 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  65 #               endif
  66 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  67 #endif
  68
  69 #define CONFIG_MCFRTC
  70 #undef RTC_DEBUG
  71 #define CONFIG_SYS_RTC_CNT              (0x8000)
  72 #define CONFIG_SYS_RTC_SETUP            (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
  73
  74 /* Timer */
  75 #define CONFIG_MCFTMR
  76 #undef CONFIG_MCFPIT
  77
  78 /* I2C */
  79 #define CONFIG_SYS_I2C
  80 #define CONFIG_SYS_I2C_FSL
  81 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  82 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  83 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
  84 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
  85
  86 #define CONFIG_BOOTDELAY                1       /* autoboot after 5 seconds */
  87 #define CONFIG_UDP_CHECKSUM
  88
  89 #ifdef CONFIG_MCFFEC
  90 #       define CONFIG_IPADDR    192.162.1.2
  91 #       define CONFIG_NETMASK   255.255.255.0
  92 #       define CONFIG_SERVERIP  192.162.1.1
  93 #       define CONFIG_GATEWAYIP 192.162.1.1
  94 #endif                          /* FEC_ENET */
  95
  96 #define CONFIG_HOSTNAME         M53017
  97 #define CONFIG_EXTRA_ENV_SETTINGS               \
  98         "netdev=eth0\0"                         \
  99         "loadaddr=40010000\0"                   \
 100         "u-boot=u-boot.bin\0"                   \
 101         "load=tftp ${loadaddr) ${u-boot}\0"     \
 102         "upd=run load; run prog\0"              \
 103         "prog=prot off 0 3ffff;"                \
 104         "era 0 3ffff;"                          \
 105         "cp.b ${loadaddr} 0 ${filesize};"       \
 106         "save\0"                                \
 107         ""
 108
 109 #define CONFIG_PRAM             512     /* 512 KB */
 110 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
 111
 112 #ifdef CONFIG_CMD_KGDB
 113 #       define CONFIG_SYS_CBSIZE        1024    /* Console I/O Buffer Size */
 114 #else
 115 #       define CONFIG_SYS_CBSIZE        256     /* Console I/O Buffer Size */
 116 #endif
 117
 118 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 119 #define CONFIG_SYS_MAXARGS      16              /* max number of cmd args */
 120 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Arg Buf Sz */
 121 #define CONFIG_SYS_LOAD_ADDR    0x40010000
 122
 123 #define CONFIG_SYS_CLK          80000000
 124 #define CONFIG_SYS_CPU_CLK      CONFIG_SYS_CLK * 3
 125
 126 #define CONFIG_SYS_MBAR         0xFC000000
 127
 128 /*
 129  * Low Level Configuration Settings
 130  * (address mappings, register initial values, etc.)
 131  * You should know what you are doing if you make changes here.
 132  */
 133 /*
 134  * Definitions for initial stack pointer and data area (in DPRAM)
 135  */
 136 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 137 #define CONFIG_SYS_INIT_RAM_SIZE                0x20000 /* Size of used area in internal SRAM */
 138 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 139 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 140 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 141
 142 /*
 143  * Start addresses for the final memory configuration
 144  * (Set up by the startup code)
 145  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 146  */
 147 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 148 #define CONFIG_SYS_SDRAM_SIZE           64      /* SDRAM size in MB */
 149 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
 150 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 151 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
 152 #define CONFIG_SYS_SDRAM_EMOD           0x80010000
 153 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 154
 155 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 156 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 157
 158 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_FLASH_BASE + 0x400)
 159 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 160
 161 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 162 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 163
 164 /*
 165  * For booting Linux, the board info and command line data
 166  * have to be in the first 8 MB of memory, since this is
 167  * the maximum mapped by the Linux kernel during initialization ??
 168  */
 169 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 170 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 171
 172 /*-----------------------------------------------------------------------
 173  * FLASH organization
 174  */
 175 #define CONFIG_SYS_FLASH_CFI
 176 #ifdef CONFIG_SYS_FLASH_CFI
 177 #       define CONFIG_FLASH_CFI_DRIVER          1
 178 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 179 #       define CONFIG_FLASH_SPANSION_S29WS_N    1
 180 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 181 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 182 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 183 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 184 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 185 #endif
 186
 187 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 188
 189 /* Configuration for environment
 190  * Environment is embedded in u-boot in the second sector of the flash
 191  */
 192 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_FLASH_BASE + 0x40000)
 193 #define CONFIG_ENV_SIZE                 0x1000
 194 #define CONFIG_ENV_SECT_SIZE            0x8000
 195 #define CONFIG_ENV_IS_IN_FLASH          1
 196
 197 #define LDS_BOARD_TEXT \
 198         . = DEFINED(env_offset) ? env_offset : .; \
 199         common/env_embedded.o       (.text*)
 200
 201 /*-----------------------------------------------------------------------
 202  * Cache Configuration
 203  */
 204 #define CONFIG_SYS_CACHELINE_SIZE       16
 205
 206 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 207                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 208 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 209                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 210 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
 211 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 212                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 213                                          CF_ACR_EN | CF_ACR_SM_ALL)
 214 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_EC | CF_CACR_CINVA | \
 215                                          CF_CACR_DCM_P)
 216
 217 /*-----------------------------------------------------------------------
 218  * Chipselect bank definitions
 219  */
 220 /*
 221  * CS0 - NOR Flash
 222  * CS1 - Ext SRAM
 223  * CS2 - Available
 224  * CS3 - Available
 225  * CS4 - Available
 226  * CS5 - Available
 227  */
 228 #define CONFIG_SYS_CS0_BASE             0
 229 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 230 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 231
 232 #define CONFIG_SYS_CS1_BASE             0xC0000000
 233 #define CONFIG_SYS_CS1_MASK             0x00070001
 234 #define CONFIG_SYS_CS1_CTRL             0x00001FA0
 235
 236 #endif                          /* _M53017EVB_H */