include/configs/M53017EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF53017EVB.
   3  *
   4  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M53017EVB_H
  15 #define _M53017EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21
  22 #define CONFIG_MCFUART
  23 #define CONFIG_SYS_UART_PORT            (0)
  24 #define CONFIG_BAUDRATE                 115200
  25
  26 #undef CONFIG_WATCHDOG
  27 #define CONFIG_WATCHDOG_TIMEOUT         5000
  28
  29 /* Command line configuration */
  30 #include <config_cmd_default.h>
  31
  32 #define CONFIG_CMD_CACHE
  33 #define CONFIG_CMD_DATE
  34 #define CONFIG_CMD_ELF
  35 #define CONFIG_CMD_FLASH
  36 #undef CONFIG_CMD_I2C
  37 #define CONFIG_CMD_MEMORY
  38 #define CONFIG_CMD_MISC
  39 #define CONFIG_CMD_MII
  40 #define CONFIG_CMD_NET
  41 #define CONFIG_CMD_PING
  42 #define CONFIG_CMD_REGINFO
  43
  44 #define CONFIG_SYS_UNIFY_CACHE
  45
  46 #define CONFIG_MCFFEC
  47 #ifdef CONFIG_MCFFEC
  48 #       define CONFIG_MII               1
  49 #       define CONFIG_MII_INIT          1
  50 #       define CONFIG_SYS_DISCOVER_PHY
  51 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  52 #       define CONFIG_SYS_TX_ETH_BUFFER 8
  53 #       define CONFIG_SYS_FEC_BUF_USE_SRAM
  54 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  55 #       define CONFIG_HAS_ETH1
  56
  57 #       define CONFIG_SYS_FEC0_PINMUX   0
  58 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  59 #       define CONFIG_SYS_FEC1_PINMUX   0
  60 #       define CONFIG_SYS_FEC1_MIIBASE  CONFIG_SYS_FEC1_IOBASE
  61 #       define MCFFEC_TOUT_LOOP         50000
  62
  63 #       define CONFIG_BOOTARGS          "root=/dev/mtdblock3 rw rootfstype=jffs2"
  64
  65 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  66 #       ifndef CONFIG_SYS_DISCOVER_PHY
  67 #               define FECDUPLEX        FULL
  68 #               define FECSPEED         _100BASET
  69 #       else
  70 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  71 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  72 #               endif
  73 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  74 #endif
  75
  76 #define CONFIG_MCFRTC
  77 #undef RTC_DEBUG
  78 #define CONFIG_SYS_RTC_CNT              (0x8000)
  79 #define CONFIG_SYS_RTC_SETUP            (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
  80
  81 /* Timer */
  82 #define CONFIG_MCFTMR
  83 #undef CONFIG_MCFPIT
  84
  85 /* I2C */
  86 #define CONFIG_SYS_I2C
  87 #define CONFIG_SYS_I2C_FSL
  88 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  89 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  90 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
  91 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
  92
  93 #define CONFIG_BOOTDELAY                1       /* autoboot after 5 seconds */
  94 #define CONFIG_UDP_CHECKSUM
  95
  96 #ifdef CONFIG_MCFFEC
  97 #       define CONFIG_ETHADDR   00:e0:0c:bc:e5:60
  98 #       define CONFIG_ETH1ADDR  00:e0:0c:bc:e5:61
  99 #       define CONFIG_IPADDR    192.162.1.2
 100 #       define CONFIG_NETMASK   255.255.255.0
 101 #       define CONFIG_SERVERIP  192.162.1.1
 102 #       define CONFIG_GATEWAYIP 192.162.1.1
 103 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
 104 #endif                          /* FEC_ENET */
 105
 106 #define CONFIG_HOSTNAME         M53017
 107 #define CONFIG_EXTRA_ENV_SETTINGS               \
 108         "netdev=eth0\0"                         \
 109         "loadaddr=40010000\0"                   \
 110         "u-boot=u-boot.bin\0"                   \
 111         "load=tftp ${loadaddr) ${u-boot}\0"     \
 112         "upd=run load; run prog\0"              \
 113         "prog=prot off 0 3ffff;"                \
 114         "era 0 3ffff;"                          \
 115         "cp.b ${loadaddr} 0 ${filesize};"       \
 116         "save\0"                                \
 117         ""
 118
 119 #define CONFIG_PRAM             512     /* 512 KB */
 120 #define CONFIG_SYS_PROMPT       "-> "
 121 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
 122
 123 #ifdef CONFIG_CMD_KGDB
 124 #       define CONFIG_SYS_CBSIZE        1024    /* Console I/O Buffer Size */
 125 #else
 126 #       define CONFIG_SYS_CBSIZE        256     /* Console I/O Buffer Size */
 127 #endif
 128
 129 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 130 #define CONFIG_SYS_MAXARGS      16              /* max number of cmd args */
 131 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Arg Buf Sz */
 132 #define CONFIG_SYS_LOAD_ADDR    0x40010000
 133
 134 #define CONFIG_SYS_CLK          80000000
 135 #define CONFIG_SYS_CPU_CLK      CONFIG_SYS_CLK * 3
 136
 137 #define CONFIG_SYS_MBAR         0xFC000000
 138
 139 /*
 140  * Low Level Configuration Settings
 141  * (address mappings, register initial values, etc.)
 142  * You should know what you are doing if you make changes here.
 143  */
 144 /*
 145  * Definitions for initial stack pointer and data area (in DPRAM)
 146  */
 147 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 148 #define CONFIG_SYS_INIT_RAM_SIZE                0x20000 /* Size of used area in internal SRAM */
 149 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 150 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 151 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 152
 153 /*
 154  * Start addresses for the final memory configuration
 155  * (Set up by the startup code)
 156  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 157  */
 158 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 159 #define CONFIG_SYS_SDRAM_SIZE           64      /* SDRAM size in MB */
 160 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
 161 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 162 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
 163 #define CONFIG_SYS_SDRAM_EMOD           0x80010000
 164 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 165
 166 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 167 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 168
 169 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_FLASH_BASE + 0x400)
 170 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 171
 172 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 173 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 174
 175 /*
 176  * For booting Linux, the board info and command line data
 177  * have to be in the first 8 MB of memory, since this is
 178  * the maximum mapped by the Linux kernel during initialization ??
 179  */
 180 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 181 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 182
 183 /*-----------------------------------------------------------------------
 184  * FLASH organization
 185  */
 186 #define CONFIG_SYS_FLASH_CFI
 187 #ifdef CONFIG_SYS_FLASH_CFI
 188 #       define CONFIG_FLASH_CFI_DRIVER          1
 189 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 190 #       define CONFIG_FLASH_SPANSION_S29WS_N    1
 191 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 192 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 193 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 194 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 195 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 196 #endif
 197
 198 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 199
 200 /* Configuration for environment
 201  * Environment is embedded in u-boot in the second sector of the flash
 202  */
 203 #define CONFIG_ENV_OFFSET               0x8000
 204 #define CONFIG_ENV_SIZE                 0x1000
 205 #define CONFIG_ENV_SECT_SIZE            0x8000
 206 #define CONFIG_ENV_IS_IN_FLASH          1
 207
 208 /*-----------------------------------------------------------------------
 209  * Cache Configuration
 210  */
 211 #define CONFIG_SYS_CACHELINE_SIZE       16
 212
 213 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 214                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 215 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 216                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 217 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
 218 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 219                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 220                                          CF_ACR_EN | CF_ACR_SM_ALL)
 221 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_EC | CF_CACR_CINVA | \
 222                                          CF_CACR_DCM_P)
 223
 224 /*-----------------------------------------------------------------------
 225  * Chipselect bank definitions
 226  */
 227 /*
 228  * CS0 - NOR Flash
 229  * CS1 - Ext SRAM
 230  * CS2 - Available
 231  * CS3 - Available
 232  * CS4 - Available
 233  * CS5 - Available
 234  */
 235 #define CONFIG_SYS_CS0_BASE             0
 236 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 237 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 238
 239 #define CONFIG_SYS_CS1_BASE             0xC0000000
 240 #define CONFIG_SYS_CS1_MASK             0x00070001
 241 #define CONFIG_SYS_CS1_CTRL             0x00001FA0
 242
 243 #endif                          /* _M53017EVB_H */