include/configs/M53017EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF53017EVB.
   3  *
   4  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M53017EVB_H
  15 #define _M53017EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_MCF5301x         /* define processor family */
  22 #define CONFIG_M53015           /* define processor type */
  23
  24 #define CONFIG_MCFUART
  25 #define CONFIG_SYS_UART_PORT            (0)
  26 #define CONFIG_BAUDRATE                 115200
  27
  28 #undef CONFIG_WATCHDOG
  29 #define CONFIG_WATCHDOG_TIMEOUT         5000
  30
  31 /* Command line configuration */
  32 #include <config_cmd_default.h>
  33
  34 #define CONFIG_CMD_CACHE
  35 #define CONFIG_CMD_DATE
  36 #define CONFIG_CMD_ELF
  37 #define CONFIG_CMD_FLASH
  38 #undef CONFIG_CMD_I2C
  39 #define CONFIG_CMD_MEMORY
  40 #define CONFIG_CMD_MISC
  41 #define CONFIG_CMD_MII
  42 #define CONFIG_CMD_NET
  43 #define CONFIG_CMD_PING
  44 #define CONFIG_CMD_REGINFO
  45
  46 #define CONFIG_SYS_UNIFY_CACHE
  47
  48 #define CONFIG_MCFFEC
  49 #ifdef CONFIG_MCFFEC
  50 #       define CONFIG_MII               1
  51 #       define CONFIG_MII_INIT          1
  52 #       define CONFIG_SYS_DISCOVER_PHY
  53 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  54 #       define CONFIG_SYS_TX_ETH_BUFFER 8
  55 #       define CONFIG_SYS_FEC_BUF_USE_SRAM
  56 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  57 #       define CONFIG_HAS_ETH1
  58
  59 #       define CONFIG_SYS_FEC0_PINMUX   0
  60 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  61 #       define CONFIG_SYS_FEC1_PINMUX   0
  62 #       define CONFIG_SYS_FEC1_MIIBASE  CONFIG_SYS_FEC1_IOBASE
  63 #       define MCFFEC_TOUT_LOOP         50000
  64
  65 #       define CONFIG_BOOTARGS          "root=/dev/mtdblock3 rw rootfstype=jffs2"
  66
  67 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  68 #       ifndef CONFIG_SYS_DISCOVER_PHY
  69 #               define FECDUPLEX        FULL
  70 #               define FECSPEED         _100BASET
  71 #       else
  72 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  73 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  74 #               endif
  75 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  76 #endif
  77
  78 #define CONFIG_MCFRTC
  79 #undef RTC_DEBUG
  80 #define CONFIG_SYS_RTC_CNT              (0x8000)
  81 #define CONFIG_SYS_RTC_SETUP            (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
  82
  83 /* Timer */
  84 #define CONFIG_MCFTMR
  85 #undef CONFIG_MCFPIT
  86
  87 /* I2C */
  88 #define CONFIG_FSL_I2C
  89 #define CONFIG_HARD_I2C                 /* I2C with hw support */
  90 #undef CONFIG_SOFT_I2C                  /* I2C bit-banged */
  91 #define CONFIG_SYS_I2C_SPEED            80000
  92 #define CONFIG_SYS_I2C_SLAVE            0x7F
  93 #define CONFIG_SYS_I2C_OFFSET           0x58000
  94 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
  95
  96 #define CONFIG_BOOTDELAY                1       /* autoboot after 5 seconds */
  97 #define CONFIG_UDP_CHECKSUM
  98
  99 #ifdef CONFIG_MCFFEC
 100 #       define CONFIG_ETHADDR   00:e0:0c:bc:e5:60
 101 #       define CONFIG_ETH1ADDR  00:e0:0c:bc:e5:61
 102 #       define CONFIG_IPADDR    192.162.1.2
 103 #       define CONFIG_NETMASK   255.255.255.0
 104 #       define CONFIG_SERVERIP  192.162.1.1
 105 #       define CONFIG_GATEWAYIP 192.162.1.1
 106 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
 107 #endif                          /* FEC_ENET */
 108
 109 #define CONFIG_HOSTNAME         M53017
 110 #define CONFIG_EXTRA_ENV_SETTINGS               \
 111         "netdev=eth0\0"                         \
 112         "loadaddr=40010000\0"                   \
 113         "u-boot=u-boot.bin\0"                   \
 114         "load=tftp ${loadaddr) ${u-boot}\0"     \
 115         "upd=run load; run prog\0"              \
 116         "prog=prot off 0 3ffff;"                \
 117         "era 0 3ffff;"                          \
 118         "cp.b ${loadaddr} 0 ${filesize};"       \
 119         "save\0"                                \
 120         ""
 121
 122 #define CONFIG_PRAM             512     /* 512 KB */
 123 #define CONFIG_SYS_PROMPT       "-> "
 124 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
 125
 126 #ifdef CONFIG_CMD_KGDB
 127 #       define CONFIG_SYS_CBSIZE        1024    /* Console I/O Buffer Size */
 128 #else
 129 #       define CONFIG_SYS_CBSIZE        256     /* Console I/O Buffer Size */
 130 #endif
 131
 132 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 133 #define CONFIG_SYS_MAXARGS      16              /* max number of cmd args */
 134 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Arg Buf Sz */
 135 #define CONFIG_SYS_LOAD_ADDR    0x40010000
 136
 137 #define CONFIG_SYS_HZ           1000
 138 #define CONFIG_SYS_CLK          80000000
 139 #define CONFIG_SYS_CPU_CLK      CONFIG_SYS_CLK * 3
 140
 141 #define CONFIG_SYS_MBAR         0xFC000000
 142
 143 /*
 144  * Low Level Configuration Settings
 145  * (address mappings, register initial values, etc.)
 146  * You should know what you are doing if you make changes here.
 147  */
 148 /*
 149  * Definitions for initial stack pointer and data area (in DPRAM)
 150  */
 151 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 152 #define CONFIG_SYS_INIT_RAM_SIZE                0x20000 /* Size of used area in internal SRAM */
 153 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 154 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 155 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 156
 157 /*
 158  * Start addresses for the final memory configuration
 159  * (Set up by the startup code)
 160  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 161  */
 162 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 163 #define CONFIG_SYS_SDRAM_SIZE           64      /* SDRAM size in MB */
 164 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
 165 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 166 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
 167 #define CONFIG_SYS_SDRAM_EMOD           0x80010000
 168 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 169
 170 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 171 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 172
 173 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_FLASH_BASE + 0x400)
 174 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 175
 176 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 177 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 178
 179 /*
 180  * For booting Linux, the board info and command line data
 181  * have to be in the first 8 MB of memory, since this is
 182  * the maximum mapped by the Linux kernel during initialization ??
 183  */
 184 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 185 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 186
 187 /*-----------------------------------------------------------------------
 188  * FLASH organization
 189  */
 190 #define CONFIG_SYS_FLASH_CFI
 191 #ifdef CONFIG_SYS_FLASH_CFI
 192 #       define CONFIG_FLASH_CFI_DRIVER          1
 193 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 194 #       define CONFIG_FLASH_SPANSION_S29WS_N    1
 195 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 196 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 197 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 198 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 199 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 200 #endif
 201
 202 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 203
 204 /* Configuration for environment
 205  * Environment is embedded in u-boot in the second sector of the flash
 206  */
 207 #define CONFIG_ENV_OFFSET               0x8000
 208 #define CONFIG_ENV_SIZE                 0x1000
 209 #define CONFIG_ENV_SECT_SIZE            0x8000
 210 #define CONFIG_ENV_IS_IN_FLASH          1
 211
 212 /*-----------------------------------------------------------------------
 213  * Cache Configuration
 214  */
 215 #define CONFIG_SYS_CACHELINE_SIZE       16
 216
 217 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 218                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 219 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 220                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 221 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
 222 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 223                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 224                                          CF_ACR_EN | CF_ACR_SM_ALL)
 225 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_EC | CF_CACR_CINVA | \
 226                                          CF_CACR_DCM_P)
 227
 228 /*-----------------------------------------------------------------------
 229  * Chipselect bank definitions
 230  */
 231 /*
 232  * CS0 - NOR Flash
 233  * CS1 - Ext SRAM
 234  * CS2 - Available
 235  * CS3 - Available
 236  * CS4 - Available
 237  * CS5 - Available
 238  */
 239 #define CONFIG_SYS_CS0_BASE             0
 240 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 241 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 242
 243 #define CONFIG_SYS_CS1_BASE             0xC0000000
 244 #define CONFIG_SYS_CS1_MASK             0x00070001
 245 #define CONFIG_SYS_CS1_CTRL             0x00001FA0
 246
 247 #endif                          /* _M53017EVB_H */