include/configs/M5373EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF5373 FireEngine board.
   3  *
   4  * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M5373EVB_H
  15 #define _M5373EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21
  22 #define CONFIG_MCFUART
  23 #define CONFIG_SYS_UART_PORT            (0)
  24 #define CONFIG_BAUDRATE         115200
  25
  26 #undef CONFIG_WATCHDOG
  27 #define CONFIG_WATCHDOG_TIMEOUT 3360    /* timeout in ms, max is 3.36 sec */
  28
  29 /* Command line configuration */
  30 #define CONFIG_CMD_CACHE
  31 #define CONFIG_CMD_DATE
  32 #define CONFIG_CMD_MII
  33 #define CONFIG_CMD_REGINFO
  34
  35 #ifdef CONFIG_NANDFLASH_SIZE
  36 #      define CONFIG_CMD_NAND
  37 #endif
  38
  39 #define CONFIG_SYS_UNIFY_CACHE
  40
  41 #define CONFIG_MCFFEC
  42 #ifdef CONFIG_MCFFEC
  43 #       define CONFIG_MII               1
  44 #       define CONFIG_MII_INIT          1
  45 #       define CONFIG_SYS_DISCOVER_PHY
  46 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  47 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  48
  49 #       define CONFIG_SYS_FEC0_PINMUX           0
  50 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  51 #       define MCFFEC_TOUT_LOOP         50000
  52 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  53 #       ifndef CONFIG_SYS_DISCOVER_PHY
  54 #               define FECDUPLEX        FULL
  55 #               define FECSPEED         _100BASET
  56 #       else
  57 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  58 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  59 #               endif
  60 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  61 #endif
  62
  63 #define CONFIG_MCFRTC
  64 #undef RTC_DEBUG
  65
  66 /* Timer */
  67 #define CONFIG_MCFTMR
  68 #undef CONFIG_MCFPIT
  69
  70 /* I2C */
  71 #define CONFIG_SYS_I2C
  72 #define CONFIG_SYS_I2C_FSL
  73 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  74 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  75 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
  76 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
  77
  78 #define CONFIG_BOOTDELAY        1       /* autoboot after 5 seconds */
  79 #define CONFIG_UDP_CHECKSUM
  80
  81 #ifdef CONFIG_MCFFEC
  82 #       define CONFIG_IPADDR    192.162.1.2
  83 #       define CONFIG_NETMASK   255.255.255.0
  84 #       define CONFIG_SERVERIP  192.162.1.1
  85 #       define CONFIG_GATEWAYIP 192.162.1.1
  86 #endif                          /* FEC_ENET */
  87
  88 #define CONFIG_HOSTNAME         M5373EVB
  89 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  90         "netdev=eth0\0"                 \
  91         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0"      \
  92         "u-boot=u-boot.bin\0"   \
  93         "load=tftp ${loadaddr) ${u-boot}\0"     \
  94         "upd=run load; run prog\0"      \
  95         "prog=prot off 0 3ffff;"        \
  96         "era 0 3ffff;"  \
  97         "cp.b ${loadaddr} 0 ${filesize};"       \
  98         "save\0"        \
  99         ""
 100
 101 #define CONFIG_PRAM             512     /* 512 KB */
 102 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 103
 104 #ifdef CONFIG_CMD_KGDB
 105 #       define CONFIG_SYS_CBSIZE        1024    /* Console I/O Buffer Size */
 106 #else
 107 #       define CONFIG_SYS_CBSIZE        256     /* Console I/O Buffer Size */
 108 #endif
 109
 110 #define CONFIG_SYS_PBSIZE                       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 111 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 112 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 113 #define CONFIG_SYS_LOAD_ADDR            0x40010000
 114
 115 #define CONFIG_SYS_CLK                  80000000
 116 #define CONFIG_SYS_CPU_CLK              CONFIG_SYS_CLK * 3
 117
 118 #define CONFIG_SYS_MBAR         0xFC000000
 119
 120 #define CONFIG_SYS_LATCH_ADDR           (CONFIG_SYS_CS1_BASE + 0x80000)
 121
 122 /*
 123  * Low Level Configuration Settings
 124  * (address mappings, register initial values, etc.)
 125  * You should know what you are doing if you make changes here.
 126  */
 127 /*-----------------------------------------------------------------------
 128  * Definitions for initial stack pointer and data area (in DPRAM)
 129  */
 130 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 131 #define CONFIG_SYS_INIT_RAM_SIZE        0x8000  /* Size of used area in internal SRAM */
 132 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 133 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 134 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 135
 136 /*-----------------------------------------------------------------------
 137  * Start addresses for the final memory configuration
 138  * (Set up by the startup code)
 139  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 140  */
 141 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 142 #define CONFIG_SYS_SDRAM_SIZE           32      /* SDRAM size in MB */
 143 #define CONFIG_SYS_SDRAM_CFG1           0x53722730
 144 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 145 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
 146 #define CONFIG_SYS_SDRAM_EMOD           0x40010000
 147 #define CONFIG_SYS_SDRAM_MODE           0x018D0000
 148
 149 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 150 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 151
 152 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 153 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 154
 155 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 156 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 157
 158 /*
 159  * For booting Linux, the board info and command line data
 160  * have to be in the first 8 MB of memory, since this is
 161  * the maximum mapped by the Linux kernel during initialization ??
 162  */
 163 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 164 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 165
 166 /*-----------------------------------------------------------------------
 167  * FLASH organization
 168  */
 169 #define CONFIG_SYS_FLASH_CFI
 170 #ifdef CONFIG_SYS_FLASH_CFI
 171 #       define CONFIG_FLASH_CFI_DRIVER  1
 172 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
 173 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 174 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 175 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 176 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 177 #endif
 178
 179 #ifdef CONFIG_NANDFLASH_SIZE
 180 #       define CONFIG_SYS_MAX_NAND_DEVICE       1
 181 #       define CONFIG_SYS_NAND_BASE             CONFIG_SYS_CS2_BASE
 182 #       define CONFIG_SYS_NAND_SIZE             1
 183 #       define CONFIG_SYS_NAND_BASE_LIST        { CONFIG_SYS_NAND_BASE }
 184 #       define NAND_ALLOW_ERASE_ALL     1
 185 #       define CONFIG_JFFS2_NAND        1
 186 #       define CONFIG_JFFS2_DEV         "nand0"
 187 #       define CONFIG_JFFS2_PART_SIZE   (CONFIG_SYS_CS2_MASK & ~1)
 188 #       define CONFIG_JFFS2_PART_OFFSET 0x00000000
 189 #endif
 190
 191 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 192
 193 /* Configuration for environment
 194  * Environment is embedded in u-boot in the second sector of the flash
 195  */
 196 #define CONFIG_ENV_OFFSET               0x4000
 197 #define CONFIG_ENV_SECT_SIZE    0x2000
 198 #define CONFIG_ENV_IS_IN_FLASH  1
 199
 200 #define LDS_BOARD_TEXT \
 201         . = DEFINED(env_offset) ? env_offset : .; \
 202         common/env_embedded.o (.text*);
 203
 204 /*-----------------------------------------------------------------------
 205  * Cache Configuration
 206  */
 207 #define CONFIG_SYS_CACHELINE_SIZE       16
 208
 209 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 210                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 211 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 212                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 213 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
 214 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 215                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 216                                          CF_ACR_EN | CF_ACR_SM_ALL)
 217 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_EC | CF_CACR_CINVA | \
 218                                          CF_CACR_DCM_P)
 219
 220 /*-----------------------------------------------------------------------
 221  * Chipselect bank definitions
 222  */
 223 /*
 224  * CS0 - NOR Flash 1, 2, 4, or 8MB
 225  * CS1 - CompactFlash and registers
 226  * CS2 - NAND Flash 16, 32, or 64MB
 227  * CS3 - Available
 228  * CS4 - Available
 229  * CS5 - Available
 230  */
 231 #define CONFIG_SYS_CS0_BASE             0
 232 #define CONFIG_SYS_CS0_MASK             0x007f0001
 233 #define CONFIG_SYS_CS0_CTRL             0x00001fa0
 234
 235 #define CONFIG_SYS_CS1_BASE             0x10000000
 236 #define CONFIG_SYS_CS1_MASK             0x001f0001
 237 #define CONFIG_SYS_CS1_CTRL             0x002A3780
 238
 239 #ifdef CONFIG_NANDFLASH_SIZE
 240 #define CONFIG_SYS_CS2_BASE             0x20000000
 241 #define CONFIG_SYS_CS2_MASK             ((CONFIG_NANDFLASH_SIZE << 20) | 1)
 242 #define CONFIG_SYS_CS2_CTRL             0x00001f60
 243 #endif
 244
 245 #endif                          /* _M5373EVB_H */