include/configs/M5373EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF5373 FireEngine board.
   3  *
   4  * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M5373EVB_H
  15 #define _M5373EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_MCF532x          /* define processor family */
  22 #define CONFIG_M5373            /* define processor type */
  23
  24 #define CONFIG_MCFUART
  25 #define CONFIG_SYS_UART_PORT            (0)
  26 #define CONFIG_BAUDRATE         115200
  27
  28 #undef CONFIG_WATCHDOG
  29 #define CONFIG_WATCHDOG_TIMEOUT 3360    /* timeout in ms, max is 3.36 sec */
  30
  31 /* Command line configuration */
  32 #include <config_cmd_default.h>
  33
  34 #define CONFIG_CMD_CACHE
  35 #define CONFIG_CMD_DATE
  36 #define CONFIG_CMD_ELF
  37 #define CONFIG_CMD_FLASH
  38 #define CONFIG_CMD_I2C
  39 #define CONFIG_CMD_MEMORY
  40 #define CONFIG_CMD_MISC
  41 #define CONFIG_CMD_MII
  42 #define CONFIG_CMD_NET
  43 #define CONFIG_CMD_PING
  44 #define CONFIG_CMD_REGINFO
  45
  46 #ifdef CONFIG_NANDFLASH_SIZE
  47 #      define CONFIG_CMD_NAND
  48 #endif
  49
  50 #define CONFIG_SYS_UNIFY_CACHE
  51
  52 #define CONFIG_MCFFEC
  53 #ifdef CONFIG_MCFFEC
  54 #       define CONFIG_MII               1
  55 #       define CONFIG_MII_INIT          1
  56 #       define CONFIG_SYS_DISCOVER_PHY
  57 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  58 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  59
  60 #       define CONFIG_SYS_FEC0_PINMUX           0
  61 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  62 #       define MCFFEC_TOUT_LOOP         50000
  63 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  64 #       ifndef CONFIG_SYS_DISCOVER_PHY
  65 #               define FECDUPLEX        FULL
  66 #               define FECSPEED         _100BASET
  67 #       else
  68 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  69 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  70 #               endif
  71 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  72 #endif
  73
  74 #define CONFIG_MCFRTC
  75 #undef RTC_DEBUG
  76
  77 /* Timer */
  78 #define CONFIG_MCFTMR
  79 #undef CONFIG_MCFPIT
  80
  81 /* I2C */
  82 #define CONFIG_SYS_I2C
  83 #define CONFIG_SYS_I2C_FSL
  84 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  85 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  86 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
  87 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
  88
  89 #define CONFIG_BOOTDELAY        1       /* autoboot after 5 seconds */
  90 #define CONFIG_UDP_CHECKSUM
  91
  92 #ifdef CONFIG_MCFFEC
  93 #       define CONFIG_ETHADDR   00:e0:0c:bc:e5:60
  94 #       define CONFIG_IPADDR    192.162.1.2
  95 #       define CONFIG_NETMASK   255.255.255.0
  96 #       define CONFIG_SERVERIP  192.162.1.1
  97 #       define CONFIG_GATEWAYIP 192.162.1.1
  98 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
  99 #endif                          /* FEC_ENET */
 100
 101 #define CONFIG_HOSTNAME         M5373EVB
 102 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 103         "netdev=eth0\0"                 \
 104         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0"      \
 105         "u-boot=u-boot.bin\0"   \
 106         "load=tftp ${loadaddr) ${u-boot}\0"     \
 107         "upd=run load; run prog\0"      \
 108         "prog=prot off 0 3ffff;"        \
 109         "era 0 3ffff;"  \
 110         "cp.b ${loadaddr} 0 ${filesize};"       \
 111         "save\0"        \
 112         ""
 113
 114 #define CONFIG_PRAM             512     /* 512 KB */
 115 #define CONFIG_SYS_PROMPT               "-> "
 116 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 117
 118 #ifdef CONFIG_CMD_KGDB
 119 #       define CONFIG_SYS_CBSIZE        1024    /* Console I/O Buffer Size */
 120 #else
 121 #       define CONFIG_SYS_CBSIZE        256     /* Console I/O Buffer Size */
 122 #endif
 123
 124 #define CONFIG_SYS_PBSIZE                       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 125 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 126 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 127 #define CONFIG_SYS_LOAD_ADDR            0x40010000
 128
 129 #define CONFIG_SYS_HZ                   1000
 130 #define CONFIG_SYS_CLK                  80000000
 131 #define CONFIG_SYS_CPU_CLK              CONFIG_SYS_CLK * 3
 132
 133 #define CONFIG_SYS_MBAR         0xFC000000
 134
 135 #define CONFIG_SYS_LATCH_ADDR           (CONFIG_SYS_CS1_BASE + 0x80000)
 136
 137 /*
 138  * Low Level Configuration Settings
 139  * (address mappings, register initial values, etc.)
 140  * You should know what you are doing if you make changes here.
 141  */
 142 /*-----------------------------------------------------------------------
 143  * Definitions for initial stack pointer and data area (in DPRAM)
 144  */
 145 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 146 #define CONFIG_SYS_INIT_RAM_SIZE        0x8000  /* Size of used area in internal SRAM */
 147 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 148 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 149 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 150
 151 /*-----------------------------------------------------------------------
 152  * Start addresses for the final memory configuration
 153  * (Set up by the startup code)
 154  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 155  */
 156 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 157 #define CONFIG_SYS_SDRAM_SIZE           32      /* SDRAM size in MB */
 158 #define CONFIG_SYS_SDRAM_CFG1           0x53722730
 159 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 160 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
 161 #define CONFIG_SYS_SDRAM_EMOD           0x40010000
 162 #define CONFIG_SYS_SDRAM_MODE           0x018D0000
 163
 164 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 165 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 166
 167 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 168 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 169
 170 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 171 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 172
 173 /*
 174  * For booting Linux, the board info and command line data
 175  * have to be in the first 8 MB of memory, since this is
 176  * the maximum mapped by the Linux kernel during initialization ??
 177  */
 178 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 179 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 180
 181 /*-----------------------------------------------------------------------
 182  * FLASH organization
 183  */
 184 #define CONFIG_SYS_FLASH_CFI
 185 #ifdef CONFIG_SYS_FLASH_CFI
 186 #       define CONFIG_FLASH_CFI_DRIVER  1
 187 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
 188 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 189 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 190 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 191 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 192 #endif
 193
 194 #ifdef CONFIG_NANDFLASH_SIZE
 195 #       define CONFIG_SYS_MAX_NAND_DEVICE       1
 196 #       define CONFIG_SYS_NAND_BASE             CONFIG_SYS_CS2_BASE
 197 #       define CONFIG_SYS_NAND_SIZE             1
 198 #       define CONFIG_SYS_NAND_BASE_LIST        { CONFIG_SYS_NAND_BASE }
 199 #       define NAND_ALLOW_ERASE_ALL     1
 200 #       define CONFIG_JFFS2_NAND        1
 201 #       define CONFIG_JFFS2_DEV         "nand0"
 202 #       define CONFIG_JFFS2_PART_SIZE   (CONFIG_SYS_CS2_MASK & ~1)
 203 #       define CONFIG_JFFS2_PART_OFFSET 0x00000000
 204 #endif
 205
 206 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 207
 208 /* Configuration for environment
 209  * Environment is embedded in u-boot in the second sector of the flash
 210  */
 211 #define CONFIG_ENV_OFFSET               0x4000
 212 #define CONFIG_ENV_SECT_SIZE    0x2000
 213 #define CONFIG_ENV_IS_IN_FLASH  1
 214
 215 /*-----------------------------------------------------------------------
 216  * Cache Configuration
 217  */
 218 #define CONFIG_SYS_CACHELINE_SIZE       16
 219
 220 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 221                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 222 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 223                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 224 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
 225 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 226                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 227                                          CF_ACR_EN | CF_ACR_SM_ALL)
 228 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_EC | CF_CACR_CINVA | \
 229                                          CF_CACR_DCM_P)
 230
 231 /*-----------------------------------------------------------------------
 232  * Chipselect bank definitions
 233  */
 234 /*
 235  * CS0 - NOR Flash 1, 2, 4, or 8MB
 236  * CS1 - CompactFlash and registers
 237  * CS2 - NAND Flash 16, 32, or 64MB
 238  * CS3 - Available
 239  * CS4 - Available
 240  * CS5 - Available
 241  */
 242 #define CONFIG_SYS_CS0_BASE             0
 243 #define CONFIG_SYS_CS0_MASK             0x007f0001
 244 #define CONFIG_SYS_CS0_CTRL             0x00001fa0
 245
 246 #define CONFIG_SYS_CS1_BASE             0x10000000
 247 #define CONFIG_SYS_CS1_MASK             0x001f0001
 248 #define CONFIG_SYS_CS1_CTRL             0x002A3780
 249
 250 #ifdef CONFIG_NANDFLASH_SIZE
 251 #define CONFIG_SYS_CS2_BASE             0x20000000
 252 #define CONFIG_SYS_CS2_MASK             ((CONFIG_NANDFLASH_SIZE << 20) | 1)
 253 #define CONFIG_SYS_CS2_CTRL             0x00001f60
 254 #endif
 255
 256 #endif                          /* _M5373EVB_H */