include/configs/M54451EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF54451 EVB board.
   3  *
   4  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M54451EVB_H
  15 #define _M54451EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_M54451EVB        /* M54451EVB board */
  22
  23 #define CONFIG_MCFUART
  24 #define CONFIG_SYS_UART_PORT            (0)
  25
  26 #undef CONFIG_WATCHDOG
  27
  28 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  29
  30 /*
  31  * BOOTP options
  32  */
  33 #define CONFIG_BOOTP_BOOTFILESIZE
  34 #define CONFIG_BOOTP_BOOTPATH
  35 #define CONFIG_BOOTP_GATEWAY
  36 #define CONFIG_BOOTP_HOSTNAME
  37
  38 /* Command line configuration */
  39 #undef CONFIG_CMD_JFFS2
  40 #define CONFIG_CMD_REGINFO
  41
  42 /* Network configuration */
  43 #define CONFIG_MCFFEC
  44 #ifdef CONFIG_MCFFEC
  45 #       define CONFIG_MII               1
  46 #       define CONFIG_MII_INIT          1
  47 #       define CONFIG_SYS_DISCOVER_PHY
  48 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  49 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  50
  51 #       define CONFIG_SYS_FEC0_PINMUX   0
  52 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  53 #       define MCFFEC_TOUT_LOOP 50000
  54
  55 #       define CONFIG_BOOTARGS          "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
  56 #       define CONFIG_ETHPRIME          "FEC0"
  57 #       define CONFIG_IPADDR            192.162.1.2
  58 #       define CONFIG_NETMASK           255.255.255.0
  59 #       define CONFIG_SERVERIP          192.162.1.1
  60 #       define CONFIG_GATEWAYIP         192.162.1.1
  61
  62 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  63 #       ifndef CONFIG_SYS_DISCOVER_PHY
  64 #               define FECDUPLEX        FULL
  65 #               define FECSPEED         _100BASET
  66 #       else
  67 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  68 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  69 #               endif
  70 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  71 #endif
  72
  73 #define CONFIG_HOSTNAME         M54451EVB
  74 #ifdef CONFIG_SYS_STMICRO_BOOT
  75 /* ST Micro serial flash */
  76 #define CONFIG_SYS_LOAD_ADDR2           0x40010007
  77 #define CONFIG_EXTRA_ENV_SETTINGS               \
  78         "netdev=eth0\0"                         \
  79         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  80         "loadaddr=0x40010000\0"                 \
  81         "sbfhdr=sbfhdr.bin\0"                   \
  82         "uboot=u-boot.bin\0"                    \
  83         "load=tftp ${loadaddr} ${sbfhdr};"      \
  84         "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"       \
  85         "upd=run load; run prog\0"              \
  86         "prog=sf probe 0:1 1000000 3;"          \
  87         "sf erase 0 30000;"                     \
  88         "sf write ${loadaddr} 0 30000;"         \
  89         "save\0"                                \
  90         ""
  91 #else
  92 #define CONFIG_SYS_UBOOT_END    0x3FFFF
  93 #define CONFIG_EXTRA_ENV_SETTINGS               \
  94         "netdev=eth0\0"                         \
  95         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  96         "loadaddr=40010000\0"                   \
  97         "u-boot=u-boot.bin\0"                   \
  98         "load=tftp ${loadaddr) ${u-boot}\0"     \
  99         "upd=run load; run prog\0"              \
 100         "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END)    \
 101         "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;"       \
 102         "cp.b ${loadaddr} 0 ${filesize};"       \
 103         "save\0"                                \
 104         ""
 105 #endif
 106
 107 /* Realtime clock */
 108 #define CONFIG_MCFRTC
 109 #undef RTC_DEBUG
 110 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
 111
 112 /* Timer */
 113 #define CONFIG_MCFTMR
 114 #undef CONFIG_MCFPIT
 115
 116 /* I2c */
 117 #define CONFIG_SYS_I2C
 118 #define CONFIG_SYS_I2C_FSL
 119 #define CONFIG_SYS_FSL_I2C_SPEED        80000
 120 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 121 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
 122 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 123
 124 /* DSPI and Serial Flash */
 125 #define CONFIG_CF_SPI
 126 #define CONFIG_CF_DSPI
 127 #define CONFIG_SERIAL_FLASH
 128 #define CONFIG_HARD_SPI
 129 #define CONFIG_SYS_SBFHDR_SIZE          0x7
 130 #ifdef CONFIG_CMD_SPI
 131
 132 #       define CONFIG_SYS_DSPI_CTAR0    (DSPI_CTAR_TRSZ(7) | \
 133                                          DSPI_CTAR_PCSSCK_1CLK | \
 134                                          DSPI_CTAR_PASC(0) | \
 135                                          DSPI_CTAR_PDT(0) | \
 136                                          DSPI_CTAR_CSSCK(0) | \
 137                                          DSPI_CTAR_ASC(0) | \
 138                                          DSPI_CTAR_DT(1))
 139 #       define CONFIG_SYS_DSPI_CTAR1    (CONFIG_SYS_DSPI_CTAR0)
 140 #       define CONFIG_SYS_DSPI_CTAR2    (CONFIG_SYS_DSPI_CTAR0)
 141 #endif
 142
 143 /* Input, PCI, Flexbus, and VCO */
 144 #define CONFIG_EXTRA_CLOCK
 145
 146 #define CONFIG_PRAM                     2048    /* 2048 KB */
 147
 148 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 149
 150 #if defined(CONFIG_CMD_KGDB)
 151 #define CONFIG_SYS_CBSIZE                       1024    /* Console I/O Buffer Size */
 152 #else
 153 #define CONFIG_SYS_CBSIZE                       256     /* Console I/O Buffer Size */
 154 #endif
 155 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 156 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 157 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 158
 159 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x10000)
 160
 161 #define CONFIG_SYS_MBAR                 0xFC000000
 162
 163 /*
 164  * Low Level Configuration Settings
 165  * (address mappings, register initial values, etc.)
 166  * You should know what you are doing if you make changes here.
 167  */
 168
 169 /*-----------------------------------------------------------------------
 170  * Definitions for initial stack pointer and data area (in DPRAM)
 171  */
 172 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 173 #define CONFIG_SYS_INIT_RAM_SIZE        0x8000  /* Size of used area in internal SRAM */
 174 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 175 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 176 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 177 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 178
 179 /*-----------------------------------------------------------------------
 180  * Start addresses for the final memory configuration
 181  * (Set up by the startup code)
 182  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 183  */
 184 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 185 #define CONFIG_SYS_SDRAM_SIZE           128     /* SDRAM size in MB */
 186 #define CONFIG_SYS_SDRAM_CFG1           0x33633F30
 187 #define CONFIG_SYS_SDRAM_CFG2           0x57670000
 188 #define CONFIG_SYS_SDRAM_CTRL           0xE20D2C00
 189 #define CONFIG_SYS_SDRAM_EMOD           0x80810000
 190 #define CONFIG_SYS_SDRAM_MODE           0x008D0000
 191 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0x44
 192
 193 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 194 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 195
 196 #ifdef CONFIG_CF_SBF
 197 #       define CONFIG_SERIAL_BOOT
 198 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 199 #else
 200 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 201 #endif
 202 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 203 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 204
 205 /* Reserve 256 kB for malloc() */
 206 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 207 /*
 208  * For booting Linux, the board info and command line data
 209  * have to be in the first 8 MB of memory, since this is
 210  * the maximum mapped by the Linux kernel during initialization ??
 211  */
 212 /* Initial Memory map for Linux */
 213 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 214
 215 /* Configuration for environment
 216  * Environment is not embedded in u-boot. First time runing may have env
 217  * crc error warning if there is no correct environment on the flash.
 218  */
 219 #if defined(CONFIG_SYS_STMICRO_BOOT)
 220 #       define CONFIG_ENV_IS_IN_SPI_FLASH       1
 221 #       define CONFIG_ENV_SPI_CS                1
 222 #       define CONFIG_ENV_OFFSET                0x20000
 223 #       define CONFIG_ENV_SIZE          0x2000
 224 #       define CONFIG_ENV_SECT_SIZE     0x10000
 225 #else
 226 #       define CONFIG_ENV_IS_IN_FLASH   1
 227 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 228 #       define CONFIG_ENV_SIZE          0x2000
 229 #       define CONFIG_ENV_SECT_SIZE     0x20000
 230 #endif
 231 #undef CONFIG_ENV_OVERWRITE
 232
 233 /* FLASH organization */
 234 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 235
 236 #define CONFIG_SYS_FLASH_CFI
 237 #ifdef CONFIG_SYS_FLASH_CFI
 238
 239 #       define CONFIG_FLASH_CFI_DRIVER  1
 240 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 241 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 242 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 243 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 244 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 245 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 246 #       define CONFIG_SYS_FLASH_CHECKSUM
 247 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE }
 248
 249 #endif
 250
 251 /*
 252  * This is setting for JFFS2 support in u-boot.
 253  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 254  */
 255 #ifdef CONFIG_CMD_JFFS2
 256 #       define CONFIG_JFFS2_DEV         "nor0"
 257 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 258 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
 259 #endif
 260
 261 /* Cache Configuration */
 262 #define CONFIG_SYS_CACHELINE_SIZE               16
 263
 264 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 265                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 266 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 267                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 268 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA)
 269 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 270 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 271                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 272                                          CF_ACR_EN | CF_ACR_SM_ALL)
 273 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_IEC | \
 274                                          CF_CACR_ICINVA | CF_CACR_EUSP)
 275 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 276                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 277                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 278
 279 /*-----------------------------------------------------------------------
 280  * Memory bank definitions
 281  */
 282 /*
 283  * CS0 - NOR Flash 16MB
 284  * CS1 - Available
 285  * CS2 - Available
 286  * CS3 - Available
 287  * CS4 - Available
 288  * CS5 - Available
 289  */
 290
 291  /* Flash */
 292 #define CONFIG_SYS_CS0_BASE             0x00000000
 293 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 294 #define CONFIG_SYS_CS0_CTRL             0x00004D80
 295
 296 #define CONFIG_SYS_SPANSION_BASE        CONFIG_SYS_CS0_BASE
 297
 298 #endif                          /* _M54451EVB_H */