include/configs/M54451EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF54451 EVB board.
   3  *
   4  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /*
  27  * board/config.h - configuration options, board specific
  28  */
  29
  30 #ifndef _M54451EVB_H
  31 #define _M54451EVB_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37 #define CONFIG_MCF5445x         /* define processor family */
  38 #define CONFIG_M54451           /* define processor type */
  39 #define CONFIG_M54451EVB        /* M54451EVB board */
  40
  41 #define CONFIG_MCFUART
  42 #define CONFIG_SYS_UART_PORT            (0)
  43 #define CONFIG_BAUDRATE         115200
  44 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600 , 19200 , 38400 , 57600, 115200 }
  45
  46 #undef CONFIG_WATCHDOG
  47
  48 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  49
  50 /*
  51  * BOOTP options
  52  */
  53 #define CONFIG_BOOTP_BOOTFILESIZE
  54 #define CONFIG_BOOTP_BOOTPATH
  55 #define CONFIG_BOOTP_GATEWAY
  56 #define CONFIG_BOOTP_HOSTNAME
  57
  58 /* Command line configuration */
  59 #include <config_cmd_default.h>
  60
  61 #define CONFIG_CMD_BOOTD
  62 #define CONFIG_CMD_CACHE
  63 #define CONFIG_CMD_DATE
  64 #define CONFIG_CMD_DHCP
  65 #define CONFIG_CMD_ELF
  66 #define CONFIG_CMD_FLASH
  67 #define CONFIG_CMD_I2C
  68 #undef CONFIG_CMD_JFFS2
  69 #define CONFIG_CMD_MEMORY
  70 #define CONFIG_CMD_MISC
  71 #define CONFIG_CMD_MII
  72 #define CONFIG_CMD_NET
  73 #define CONFIG_CMD_NFS
  74 #define CONFIG_CMD_PING
  75 #define CONFIG_CMD_REGINFO
  76 #define CONFIG_CMD_SPI
  77 #define CONFIG_CMD_SF
  78
  79 #undef CONFIG_CMD_LOADB
  80 #undef CONFIG_CMD_LOADS
  81
  82 /* Network configuration */
  83 #define CONFIG_MCFFEC
  84 #ifdef CONFIG_MCFFEC
  85 #       define CONFIG_NET_MULTI         1
  86 #       define CONFIG_MII               1
  87 #       define CONFIG_MII_INIT          1
  88 #       define CONFIG_SYS_DISCOVER_PHY
  89 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  90 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  91
  92 #       define CONFIG_SYS_FEC0_PINMUX   0
  93 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  94 #       define MCFFEC_TOUT_LOOP 50000
  95
  96 #       define CONFIG_BOOTDELAY 1       /* autoboot after 5 seconds */
  97 #       define CONFIG_BOOTARGS          "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
  98 #       define CONFIG_ETHADDR           00:e0:0c:bc:e5:60
  99 #       define CONFIG_ETHPRIME          "FEC0"
 100 #       define CONFIG_IPADDR            192.162.1.2
 101 #       define CONFIG_NETMASK           255.255.255.0
 102 #       define CONFIG_SERVERIP          192.162.1.1
 103 #       define CONFIG_GATEWAYIP         192.162.1.1
 104 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
 105
 106 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
 107 #       ifndef CONFIG_SYS_DISCOVER_PHY
 108 #               define FECDUPLEX        FULL
 109 #               define FECSPEED         _100BASET
 110 #       else
 111 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 112 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 113 #               endif
 114 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
 115 #endif
 116
 117 #define CONFIG_HOSTNAME         M54451EVB
 118 #ifdef CONFIG_SYS_STMICRO_BOOT
 119 /* ST Micro serial flash */
 120 #define CONFIG_SYS_LOAD_ADDR2           0x40010007
 121 #define CONFIG_EXTRA_ENV_SETTINGS               \
 122         "netdev=eth0\0"                         \
 123         "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"  \
 124         "loadaddr=0x40010000\0"                 \
 125         "sbfhdr=sbfhdr.bin\0"                   \
 126         "uboot=u-boot.bin\0"                    \
 127         "load=tftp ${loadaddr} ${sbfhdr};"      \
 128         "tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"    \
 129         "upd=run load; run prog\0"              \
 130         "prog=sf probe 0:1 10000 1;"            \
 131         "sf erase 0 30000;"                     \
 132         "sf write ${loadaddr} 0 30000;"         \
 133         "save\0"                                \
 134         ""
 135 #else
 136 #define CONFIG_SYS_UBOOT_END    0x3FFFF
 137 #define CONFIG_EXTRA_ENV_SETTINGS               \
 138         "netdev=eth0\0"                         \
 139         "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"  \
 140         "loadaddr=40010000\0"                   \
 141         "u-boot=u-boot.bin\0"                   \
 142         "load=tftp ${loadaddr) ${u-boot}\0"     \
 143         "upd=run load; run prog\0"              \
 144         "prog=prot off 0 " MK_STR(CONFIG_SYS_UBOOT_END) \
 145         "; era 0 " MK_STR(CONFIG_SYS_UBOOT_END) " ;"    \
 146         "cp.b ${loadaddr} 0 ${filesize};"       \
 147         "save\0"                                \
 148         ""
 149 #endif
 150
 151 /* Realtime clock */
 152 #define CONFIG_MCFRTC
 153 #undef RTC_DEBUG
 154 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
 155
 156 /* Timer */
 157 #define CONFIG_MCFTMR
 158 #undef CONFIG_MCFPIT
 159
 160 /* I2c */
 161 #define CONFIG_FSL_I2C
 162 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 163 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged               */
 164 #define CONFIG_SYS_I2C_SPEED            80000   /* I2C speed and slave address  */
 165 #define CONFIG_SYS_I2C_SLAVE            0x7F
 166 #define CONFIG_SYS_I2C_OFFSET           0x58000
 167 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 168
 169 /* DSPI and Serial Flash */
 170 #define CONFIG_CF_SPI
 171 #define CONFIG_CF_DSPI
 172 #define CONFIG_SERIAL_FLASH
 173 #define CONFIG_HARD_SPI
 174 #define CONFIG_SYS_SBFHDR_SIZE          0x7
 175 #ifdef CONFIG_CMD_SPI
 176 #       define CONFIG_SPI_FLASH
 177 #       define CONFIG_SPI_FLASH_STMICRO
 178
 179 #       define CONFIG_SYS_DSPI_CTAR0    (DSPI_CTAR_TRSZ(7) | \
 180                                          DSPI_CTAR_PCSSCK_1CLK | \
 181                                          DSPI_CTAR_PASC(0) | \
 182                                          DSPI_CTAR_PDT(0) | \
 183                                          DSPI_CTAR_CSSCK(0) | \
 184                                          DSPI_CTAR_ASC(0) | \
 185                                          DSPI_CTAR_DT(1))
 186 #       define CONFIG_SYS_DSPI_CTAR1    (CONFIG_SYS_DSPI_CTAR0)
 187 #       define CONFIG_SYS_DSPI_CTAR2    (CONFIG_SYS_DSPI_CTAR0)
 188 #endif
 189
 190 /* Input, PCI, Flexbus, and VCO */
 191 #define CONFIG_EXTRA_CLOCK
 192
 193 #define CONFIG_PRAM                     2048    /* 2048 KB */
 194
 195 #define CONFIG_SYS_PROMPT               "-> "
 196 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 197
 198 #if defined(CONFIG_CMD_KGDB)
 199 #define CONFIG_SYS_CBSIZE                       1024    /* Console I/O Buffer Size */
 200 #else
 201 #define CONFIG_SYS_CBSIZE                       256     /* Console I/O Buffer Size */
 202 #endif
 203 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 204 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 205 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 206
 207 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x10000)
 208
 209 #define CONFIG_SYS_HZ                   1000
 210
 211 #define CONFIG_SYS_MBAR                 0xFC000000
 212
 213 /*
 214  * Low Level Configuration Settings
 215  * (address mappings, register initial values, etc.)
 216  * You should know what you are doing if you make changes here.
 217  */
 218
 219 /*-----------------------------------------------------------------------
 220  * Definitions for initial stack pointer and data area (in DPRAM)
 221  */
 222 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 223 #define CONFIG_SYS_INIT_RAM_END 0x8000  /* End of used area in internal SRAM */
 224 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 225 #define CONFIG_SYS_GBL_DATA_SIZE        256     /* size in bytes reserved for initial data */
 226 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
 227 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 228 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_END - 32)
 229
 230 /*-----------------------------------------------------------------------
 231  * Start addresses for the final memory configuration
 232  * (Set up by the startup code)
 233  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 234  */
 235 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 236 #define CONFIG_SYS_SDRAM_SIZE           128     /* SDRAM size in MB */
 237 #define CONFIG_SYS_SDRAM_CFG1           0x33633F30
 238 #define CONFIG_SYS_SDRAM_CFG2           0x57670000
 239 #define CONFIG_SYS_SDRAM_CTRL           0xE20D2C00
 240 #define CONFIG_SYS_SDRAM_EMOD           0x80810000
 241 #define CONFIG_SYS_SDRAM_MODE           0x008D0000
 242 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0x44
 243
 244 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 245 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 246
 247 #ifdef CONFIG_CF_SBF
 248 #       define CONFIG_SYS_MONITOR_BASE  (TEXT_BASE + 0x400)
 249 #else
 250 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 251 #endif
 252 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 253 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 254 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 255
 256 /*
 257  * For booting Linux, the board info and command line data
 258  * have to be in the first 8 MB of memory, since this is
 259  * the maximum mapped by the Linux kernel during initialization ??
 260  */
 261 /* Initial Memory map for Linux */
 262 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 263
 264 /* Configuration for environment
 265  * Environment is embedded in u-boot in the second sector of the flash
 266  */
 267 #if defined(CONFIG_SYS_STMICRO_BOOT)
 268 #       define CONFIG_ENV_IS_IN_SPI_FLASH       1
 269 #       define CONFIG_ENV_SPI_CS                1
 270 #       define CONFIG_ENV_OFFSET                0x20000
 271 #       define CONFIG_ENV_SIZE          0x2000
 272 #       define CONFIG_ENV_SECT_SIZE     0x10000
 273 #else
 274 #       define CONFIG_ENV_IS_IN_FLASH   1
 275 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x8000)
 276 #       define CONFIG_ENV_SIZE          0x2000
 277 #       define CONFIG_ENV_SECT_SIZE     0x8000
 278 #endif
 279 #undef CONFIG_ENV_OVERWRITE
 280
 281 /* FLASH organization */
 282 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 283
 284 #define CONFIG_SYS_FLASH_CFI
 285 #ifdef CONFIG_SYS_FLASH_CFI
 286
 287 #       define CONFIG_FLASH_CFI_DRIVER  1
 288 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 289 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 290 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 291 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 292 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 293 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 294 #       define CONFIG_SYS_FLASH_CHECKSUM
 295 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE }
 296
 297 #endif
 298
 299 /*
 300  * This is setting for JFFS2 support in u-boot.
 301  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 302  */
 303 #ifdef CONFIG_CMD_JFFS2
 304 #       define CONFIG_JFFS2_DEV         "nor0"
 305 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 306 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
 307 #endif
 308
 309 /* Cache Configuration */
 310 #define CONFIG_SYS_CACHELINE_SIZE               16
 311
 312 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 313                                          CONFIG_SYS_INIT_RAM_END - 8)
 314 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 315                                          CONFIG_SYS_INIT_RAM_END - 4)
 316 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA)
 317 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 318 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 319                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 320                                          CF_ACR_EN | CF_ACR_SM_ALL)
 321 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_IEC | \
 322                                          CF_CACR_ICINVA | CF_CACR_EUSP)
 323 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 324                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 325                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 326
 327 /*-----------------------------------------------------------------------
 328  * Memory bank definitions
 329  */
 330 /*
 331  * CS0 - NOR Flash 16MB
 332  * CS1 - Available
 333  * CS2 - Available
 334  * CS3 - Available
 335  * CS4 - Available
 336  * CS5 - Available
 337  */
 338
 339  /* Flash */
 340 #define CONFIG_SYS_CS0_BASE             0x00000000
 341 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 342 #define CONFIG_SYS_CS0_CTRL             0x00004D80
 343
 344 #define CONFIG_SYS_SPANSION_BASE        CONFIG_SYS_CS0_BASE
 345
 346 #endif                          /* _M54451EVB_H */