include/configs/M54455EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF54455 EVB board.
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M54455EVB_H
  15 #define _M54455EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_M54455EVB        /* M54455EVB board */
  22
  23 #define CONFIG_MCFUART
  24 #define CONFIG_SYS_UART_PORT            (0)
  25
  26 #undef CONFIG_WATCHDOG
  27
  28 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  29
  30 /*
  31  * BOOTP options
  32  */
  33 #define CONFIG_BOOTP_BOOTFILESIZE
  34 #define CONFIG_BOOTP_BOOTPATH
  35 #define CONFIG_BOOTP_GATEWAY
  36 #define CONFIG_BOOTP_HOSTNAME
  37
  38 /* Network configuration */
  39 #define CONFIG_MCFFEC
  40 #ifdef CONFIG_MCFFEC
  41 #       define CONFIG_MII               1
  42 #       define CONFIG_MII_INIT          1
  43 #       define CONFIG_SYS_DISCOVER_PHY
  44 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  45 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  46
  47 #       define CONFIG_SYS_FEC0_PINMUX   0
  48 #       define CONFIG_SYS_FEC1_PINMUX   0
  49 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  50 #       define CONFIG_SYS_FEC1_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  51 #       define MCFFEC_TOUT_LOOP 50000
  52 #       define CONFIG_HAS_ETH1
  53
  54 #       define CONFIG_BOOTARGS          "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
  55 #       define CONFIG_ETHPRIME          "FEC0"
  56 #       define CONFIG_IPADDR            192.162.1.2
  57 #       define CONFIG_NETMASK           255.255.255.0
  58 #       define CONFIG_SERVERIP          192.162.1.1
  59 #       define CONFIG_GATEWAYIP         192.162.1.1
  60
  61 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  62 #       ifndef CONFIG_SYS_DISCOVER_PHY
  63 #               define FECDUPLEX        FULL
  64 #               define FECSPEED         _100BASET
  65 #       else
  66 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  67 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  68 #               endif
  69 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  70 #endif
  71
  72 #define CONFIG_HOSTNAME         M54455EVB
  73 #ifdef CONFIG_SYS_STMICRO_BOOT
  74 /* ST Micro serial flash */
  75 #define CONFIG_SYS_LOAD_ADDR2           0x40010013
  76 #define CONFIG_EXTRA_ENV_SETTINGS               \
  77         "netdev=eth0\0"                         \
  78         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  79         "loadaddr=0x40010000\0"                 \
  80         "sbfhdr=sbfhdr.bin\0"                   \
  81         "uboot=u-boot.bin\0"                    \
  82         "load=tftp ${loadaddr} ${sbfhdr};"      \
  83         "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"       \
  84         "upd=run load; run prog\0"              \
  85         "prog=sf probe 0:1 1000000 3;"          \
  86         "sf erase 0 30000;"                     \
  87         "sf write ${loadaddr} 0 0x30000;"       \
  88         "save\0"                                \
  89         ""
  90 #else
  91 /* Atmel and Intel */
  92 #ifdef CONFIG_SYS_ATMEL_BOOT
  93 #       define CONFIG_SYS_UBOOT_END     0x0403FFFF
  94 #elif defined(CONFIG_SYS_INTEL_BOOT)
  95 #       define CONFIG_SYS_UBOOT_END     0x3FFFF
  96 #endif
  97 #define CONFIG_EXTRA_ENV_SETTINGS               \
  98         "netdev=eth0\0"                         \
  99         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 100         "loadaddr=0x40010000\0"                 \
 101         "uboot=u-boot.bin\0"                    \
 102         "load=tftp ${loadaddr} ${uboot}\0"      \
 103         "upd=run load; run prog\0"              \
 104         "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)     \
 105         " " __stringify(CONFIG_SYS_UBOOT_END) ";"               \
 106         "era " __stringify(CONFIG_SYS_FLASH_BASE) " "           \
 107         __stringify(CONFIG_SYS_UBOOT_END) ";"                   \
 108         "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)  \
 109         " ${filesize}; save\0"                  \
 110         ""
 111 #endif
 112
 113 /* ATA configuration */
 114 #define CONFIG_IDE_RESET        1
 115 #define CONFIG_IDE_PREINIT      1
 116 #define CONFIG_ATAPI
 117 #undef CONFIG_LBA48
 118
 119 #define CONFIG_SYS_IDE_MAXBUS           1
 120 #define CONFIG_SYS_IDE_MAXDEVICE        2
 121
 122 #define CONFIG_SYS_ATA_BASE_ADDR        0x90000000
 123 #define CONFIG_SYS_ATA_IDE0_OFFSET      0
 124
 125 #define CONFIG_SYS_ATA_DATA_OFFSET      0xA0    /* Offset for data I/O                            */
 126 #define CONFIG_SYS_ATA_REG_OFFSET       0xA0    /* Offset for normal register accesses */
 127 #define CONFIG_SYS_ATA_ALT_OFFSET       0xC0    /* Offset for alternate registers           */
 128 #define CONFIG_SYS_ATA_STRIDE           4       /* Interval between registers                 */
 129
 130 /* Realtime clock */
 131 #define CONFIG_MCFRTC
 132 #undef RTC_DEBUG
 133 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
 134
 135 /* Timer */
 136 #define CONFIG_MCFTMR
 137 #undef CONFIG_MCFPIT
 138
 139 /* I2c */
 140 #define CONFIG_SYS_I2C
 141 #define CONFIG_SYS_I2C_FSL
 142 #define CONFIG_SYS_FSL_I2C_SPEED        80000
 143 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 144 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
 145 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 146
 147 /* DSPI and Serial Flash */
 148 #define CONFIG_CF_SPI
 149 #define CONFIG_CF_DSPI
 150 #define CONFIG_HARD_SPI
 151 #define CONFIG_SYS_SBFHDR_SIZE          0x13
 152 #ifdef CONFIG_CMD_SPI
 153
 154 #       define CONFIG_SYS_DSPI_CTAR0            (DSPI_CTAR_TRSZ(7) | \
 155                                          DSPI_CTAR_PCSSCK_1CLK | \
 156                                          DSPI_CTAR_PASC(0) | \
 157                                          DSPI_CTAR_PDT(0) | \
 158                                          DSPI_CTAR_CSSCK(0) | \
 159                                          DSPI_CTAR_ASC(0) | \
 160                                          DSPI_CTAR_DT(1))
 161 #endif
 162
 163 /* PCI */
 164 #ifdef CONFIG_CMD_PCI
 165 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
 166
 167 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  4
 168
 169 #define CONFIG_SYS_PCI_MEM_BUS          0xA0000000
 170 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
 171 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
 172
 173 #define CONFIG_SYS_PCI_IO_BUS           0xB1000000
 174 #define CONFIG_SYS_PCI_IO_PHYS          CONFIG_SYS_PCI_IO_BUS
 175 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000
 176
 177 #define CONFIG_SYS_PCI_CFG_BUS          0xB0000000
 178 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
 179 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
 180 #endif
 181
 182 /* FPGA - Spartan 2 */
 183 /* experiment
 184 #define CONFIG_FPGA
 185 #define CONFIG_FPGA_COUNT       1
 186 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 187 #define CONFIG_SYS_FPGA_CHECK_CTRLC
 188 */
 189
 190 /* Input, PCI, Flexbus, and VCO */
 191 #define CONFIG_EXTRA_CLOCK
 192
 193 #define CONFIG_PRAM             2048    /* 2048 KB */
 194
 195 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 196
 197 #if defined(CONFIG_CMD_KGDB)
 198 #define CONFIG_SYS_CBSIZE                       1024    /* Console I/O Buffer Size */
 199 #else
 200 #define CONFIG_SYS_CBSIZE                       256     /* Console I/O Buffer Size */
 201 #endif
 202 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 203 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 204 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 205
 206 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x10000)
 207
 208 #define CONFIG_SYS_MBAR         0xFC000000
 209
 210 /*
 211  * Low Level Configuration Settings
 212  * (address mappings, register initial values, etc.)
 213  * You should know what you are doing if you make changes here.
 214  */
 215
 216 /*-----------------------------------------------------------------------
 217  * Definitions for initial stack pointer and data area (in DPRAM)
 218  */
 219 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 220 #define CONFIG_SYS_INIT_RAM_SIZE                0x8000  /* Size of used area in internal SRAM */
 221 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 222 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 223 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 224 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 225
 226 /*-----------------------------------------------------------------------
 227  * Start addresses for the final memory configuration
 228  * (Set up by the startup code)
 229  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 230  */
 231 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 232 #define CONFIG_SYS_SDRAM_BASE1          0x48000000
 233 #define CONFIG_SYS_SDRAM_SIZE           256     /* SDRAM size in MB */
 234 #define CONFIG_SYS_SDRAM_CFG1           0x65311610
 235 #define CONFIG_SYS_SDRAM_CFG2           0x59670000
 236 #define CONFIG_SYS_SDRAM_CTRL           0xEA0B2000
 237 #define CONFIG_SYS_SDRAM_EMOD           0x40010000
 238 #define CONFIG_SYS_SDRAM_MODE           0x00010033
 239 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0xAA
 240
 241 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 242 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 243
 244 #ifdef CONFIG_CF_SBF
 245 #       define CONFIG_SERIAL_BOOT
 246 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 247 #else
 248 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 249 #endif
 250 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 251 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 252
 253 /* Reserve 256 kB for malloc() */
 254 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 255
 256 /*
 257  * For booting Linux, the board info and command line data
 258  * have to be in the first 8 MB of memory, since this is
 259  * the maximum mapped by the Linux kernel during initialization ??
 260  */
 261 /* Initial Memory map for Linux */
 262 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 263
 264 /*
 265  * Configuration for environment
 266  * Environment is not embedded in u-boot. First time runing may have env
 267  * crc error warning if there is no correct environment on the flash.
 268  */
 269 #ifdef CONFIG_CF_SBF
 270 #       define CONFIG_ENV_SPI_CS                1
 271 #endif
 272 #undef CONFIG_ENV_OVERWRITE
 273
 274 /*-----------------------------------------------------------------------
 275  * FLASH organization
 276  */
 277 #ifdef CONFIG_SYS_STMICRO_BOOT
 278 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 279 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS1_BASE
 280 #       define CONFIG_ENV_OFFSET                0x30000
 281 #       define CONFIG_ENV_SIZE          0x2000
 282 #       define CONFIG_ENV_SECT_SIZE     0x10000
 283 #endif
 284 #ifdef CONFIG_SYS_ATMEL_BOOT
 285 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 286 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
 287 #       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS1_BASE
 288 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 289 #       define CONFIG_ENV_SIZE          0x2000
 290 #       define CONFIG_ENV_SECT_SIZE     0x10000
 291 #endif
 292 #ifdef CONFIG_SYS_INTEL_BOOT
 293 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 294 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
 295 #       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS1_BASE
 296 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 297 #       define CONFIG_ENV_SIZE          0x2000
 298 #       define CONFIG_ENV_SECT_SIZE     0x20000
 299 #endif
 300
 301 #define CONFIG_SYS_FLASH_CFI
 302 #ifdef CONFIG_SYS_FLASH_CFI
 303
 304 #       define CONFIG_FLASH_CFI_DRIVER  1
 305 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 306 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 307 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_8BIT
 308 #       define CONFIG_SYS_MAX_FLASH_BANKS       2       /* max number of memory banks */
 309 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 310 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 311 #       define CONFIG_SYS_FLASH_CHECKSUM
 312 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
 313 #       define CONFIG_FLASH_CFI_LEGACY
 314
 315 #ifdef CONFIG_FLASH_CFI_LEGACY
 316 #       define CONFIG_SYS_ATMEL_REGION          4
 317 #       define CONFIG_SYS_ATMEL_TOTALSECT       11
 318 #       define CONFIG_SYS_ATMEL_SECT            {1, 2, 1, 7}
 319 #       define CONFIG_SYS_ATMEL_SECTSZ          {0x4000, 0x2000, 0x8000, 0x10000}
 320 #endif
 321 #endif
 322
 323 /*
 324  * This is setting for JFFS2 support in u-boot.
 325  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 326  */
 327 #ifdef CONFIG_CMD_JFFS2
 328 #ifdef CF_STMICRO_BOOT
 329 #       define CONFIG_JFFS2_DEV         "nor1"
 330 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 331 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
 332 #endif
 333 #ifdef CONFIG_SYS_ATMEL_BOOT
 334 #       define CONFIG_JFFS2_DEV         "nor1"
 335 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 336 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
 337 #endif
 338 #ifdef CONFIG_SYS_INTEL_BOOT
 339 #       define CONFIG_JFFS2_DEV         "nor0"
 340 #       define CONFIG_JFFS2_PART_SIZE   (0x01000000 - 0x500000)
 341 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
 342 #endif
 343 #endif
 344
 345 /*-----------------------------------------------------------------------
 346  * Cache Configuration
 347  */
 348 #define CONFIG_SYS_CACHELINE_SIZE               16
 349
 350 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 351                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 352 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 353                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 354 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA)
 355 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 356 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 357                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 358                                          CF_ACR_EN | CF_ACR_SM_ALL)
 359 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_IEC | \
 360                                          CF_CACR_ICINVA | CF_CACR_EUSP)
 361 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 362                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 363                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 364
 365 /*-----------------------------------------------------------------------
 366  * Memory bank definitions
 367  */
 368 /*
 369  * CS0 - NOR Flash 1, 2, 4, or 8MB
 370  * CS1 - CompactFlash and registers
 371  * CS2 - CPLD
 372  * CS3 - FPGA
 373  * CS4 - Available
 374  * CS5 - Available
 375  */
 376
 377 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
 378  /* Atmel Flash */
 379 #define CONFIG_SYS_CS0_BASE             0x04000000
 380 #define CONFIG_SYS_CS0_MASK             0x00070001
 381 #define CONFIG_SYS_CS0_CTRL             0x00001140
 382 /* Intel Flash */
 383 #define CONFIG_SYS_CS1_BASE             0x00000000
 384 #define CONFIG_SYS_CS1_MASK             0x01FF0001
 385 #define CONFIG_SYS_CS1_CTRL             0x00000D60
 386
 387 #define CONFIG_SYS_ATMEL_BASE           CONFIG_SYS_CS0_BASE
 388 #else
 389 /* Intel Flash */
 390 #define CONFIG_SYS_CS0_BASE             0x00000000
 391 #define CONFIG_SYS_CS0_MASK             0x01FF0001
 392 #define CONFIG_SYS_CS0_CTRL             0x00000D60
 393  /* Atmel Flash */
 394 #define CONFIG_SYS_CS1_BASE             0x04000000
 395 #define CONFIG_SYS_CS1_MASK             0x00070001
 396 #define CONFIG_SYS_CS1_CTRL             0x00001140
 397
 398 #define CONFIG_SYS_ATMEL_BASE           CONFIG_SYS_CS1_BASE
 399 #endif
 400
 401 /* CPLD */
 402 #define CONFIG_SYS_CS2_BASE             0x08000000
 403 #define CONFIG_SYS_CS2_MASK             0x00070001
 404 #define CONFIG_SYS_CS2_CTRL             0x003f1140
 405
 406 /* FPGA */
 407 #define CONFIG_SYS_CS3_BASE             0x09000000
 408 #define CONFIG_SYS_CS3_MASK             0x00070001
 409 #define CONFIG_SYS_CS3_CTRL             0x00000020
 410
 411 #endif                          /* _M54455EVB_H */