include/configs/M54455EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF54455 EVB board.
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M54455EVB_H
  15 #define _M54455EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_M54455EVB        /* M54455EVB board */
  22
  23 #define CONFIG_DISPLAY_BOARDINFO
  24
  25 #define CONFIG_MCFUART
  26 #define CONFIG_SYS_UART_PORT            (0)
  27 #define CONFIG_BAUDRATE         115200
  28
  29 #undef CONFIG_WATCHDOG
  30
  31 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  32
  33 /*
  34  * BOOTP options
  35  */
  36 #define CONFIG_BOOTP_BOOTFILESIZE
  37 #define CONFIG_BOOTP_BOOTPATH
  38 #define CONFIG_BOOTP_GATEWAY
  39 #define CONFIG_BOOTP_HOSTNAME
  40
  41 /* Command line configuration */
  42 #include <config_cmd_default.h>
  43
  44 #define CONFIG_CMD_BOOTD
  45 #define CONFIG_CMD_CACHE
  46 #define CONFIG_CMD_DATE
  47 #define CONFIG_CMD_DHCP
  48 #define CONFIG_CMD_ELF
  49 #define CONFIG_CMD_EXT2
  50 #define CONFIG_CMD_FAT
  51 #define CONFIG_CMD_FLASH
  52 #define CONFIG_CMD_I2C
  53 #define CONFIG_CMD_IDE
  54 #define CONFIG_CMD_JFFS2
  55 #define CONFIG_CMD_MEMORY
  56 #define CONFIG_CMD_MISC
  57 #define CONFIG_CMD_MII
  58 #undef CONFIG_CMD_PCI
  59 #define CONFIG_CMD_PING
  60 #define CONFIG_CMD_REGINFO
  61 #define CONFIG_CMD_SPI
  62 #define CONFIG_CMD_SF
  63
  64 #undef CONFIG_CMD_LOADB
  65 #undef CONFIG_CMD_LOADS
  66
  67 /* Network configuration */
  68 #define CONFIG_MCFFEC
  69 #ifdef CONFIG_MCFFEC
  70 #       define CONFIG_MII               1
  71 #       define CONFIG_MII_INIT          1
  72 #       define CONFIG_SYS_DISCOVER_PHY
  73 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  74 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  75
  76 #       define CONFIG_SYS_FEC0_PINMUX   0
  77 #       define CONFIG_SYS_FEC1_PINMUX   0
  78 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  79 #       define CONFIG_SYS_FEC1_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  80 #       define MCFFEC_TOUT_LOOP 50000
  81 #       define CONFIG_HAS_ETH1
  82
  83 #       define CONFIG_BOOTDELAY 1       /* autoboot after 5 seconds */
  84 #       define CONFIG_BOOTARGS          "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
  85 #       define CONFIG_ETHPRIME          "FEC0"
  86 #       define CONFIG_IPADDR            192.162.1.2
  87 #       define CONFIG_NETMASK           255.255.255.0
  88 #       define CONFIG_SERVERIP          192.162.1.1
  89 #       define CONFIG_GATEWAYIP         192.162.1.1
  90
  91 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  92 #       ifndef CONFIG_SYS_DISCOVER_PHY
  93 #               define FECDUPLEX        FULL
  94 #               define FECSPEED         _100BASET
  95 #       else
  96 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  97 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  98 #               endif
  99 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
 100 #endif
 101
 102 #define CONFIG_HOSTNAME         M54455EVB
 103 #ifdef CONFIG_SYS_STMICRO_BOOT
 104 /* ST Micro serial flash */
 105 #define CONFIG_SYS_LOAD_ADDR2           0x40010013
 106 #define CONFIG_EXTRA_ENV_SETTINGS               \
 107         "netdev=eth0\0"                         \
 108         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 109         "loadaddr=0x40010000\0"                 \
 110         "sbfhdr=sbfhdr.bin\0"                   \
 111         "uboot=u-boot.bin\0"                    \
 112         "load=tftp ${loadaddr} ${sbfhdr};"      \
 113         "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"       \
 114         "upd=run load; run prog\0"              \
 115         "prog=sf probe 0:1 1000000 3;"          \
 116         "sf erase 0 30000;"                     \
 117         "sf write ${loadaddr} 0 0x30000;"       \
 118         "save\0"                                \
 119         ""
 120 #else
 121 /* Atmel and Intel */
 122 #ifdef CONFIG_SYS_ATMEL_BOOT
 123 #       define CONFIG_SYS_UBOOT_END     0x0403FFFF
 124 #elif defined(CONFIG_SYS_INTEL_BOOT)
 125 #       define CONFIG_SYS_UBOOT_END     0x3FFFF
 126 #endif
 127 #define CONFIG_EXTRA_ENV_SETTINGS               \
 128         "netdev=eth0\0"                         \
 129         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 130         "loadaddr=0x40010000\0"                 \
 131         "uboot=u-boot.bin\0"                    \
 132         "load=tftp ${loadaddr} ${uboot}\0"      \
 133         "upd=run load; run prog\0"              \
 134         "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)     \
 135         " " __stringify(CONFIG_SYS_UBOOT_END) ";"               \
 136         "era " __stringify(CONFIG_SYS_FLASH_BASE) " "           \
 137         __stringify(CONFIG_SYS_UBOOT_END) ";"                   \
 138         "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)  \
 139         " ${filesize}; save\0"                  \
 140         ""
 141 #endif
 142
 143 /* ATA configuration */
 144 #define CONFIG_ISO_PARTITION
 145 #define CONFIG_DOS_PARTITION
 146 #define CONFIG_IDE_RESET        1
 147 #define CONFIG_IDE_PREINIT      1
 148 #define CONFIG_ATAPI
 149 #undef CONFIG_LBA48
 150
 151 #define CONFIG_SYS_IDE_MAXBUS           1
 152 #define CONFIG_SYS_IDE_MAXDEVICE        2
 153
 154 #define CONFIG_SYS_ATA_BASE_ADDR        0x90000000
 155 #define CONFIG_SYS_ATA_IDE0_OFFSET      0
 156
 157 #define CONFIG_SYS_ATA_DATA_OFFSET      0xA0    /* Offset for data I/O                            */
 158 #define CONFIG_SYS_ATA_REG_OFFSET       0xA0    /* Offset for normal register accesses */
 159 #define CONFIG_SYS_ATA_ALT_OFFSET       0xC0    /* Offset for alternate registers           */
 160 #define CONFIG_SYS_ATA_STRIDE           4       /* Interval between registers                 */
 161
 162 /* Realtime clock */
 163 #define CONFIG_MCFRTC
 164 #undef RTC_DEBUG
 165 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
 166
 167 /* Timer */
 168 #define CONFIG_MCFTMR
 169 #undef CONFIG_MCFPIT
 170
 171 /* I2c */
 172 #define CONFIG_SYS_I2C
 173 #define CONFIG_SYS_I2C_FSL
 174 #define CONFIG_SYS_FSL_I2C_SPEED        80000
 175 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 176 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
 177 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 178
 179 /* DSPI and Serial Flash */
 180 #define CONFIG_CF_SPI
 181 #define CONFIG_CF_DSPI
 182 #define CONFIG_HARD_SPI
 183 #define CONFIG_SYS_SBFHDR_SIZE          0x13
 184 #ifdef CONFIG_CMD_SPI
 185 #       define CONFIG_SPI_FLASH_STMICRO
 186
 187 #       define CONFIG_SYS_DSPI_CTAR0            (DSPI_CTAR_TRSZ(7) | \
 188                                          DSPI_CTAR_PCSSCK_1CLK | \
 189                                          DSPI_CTAR_PASC(0) | \
 190                                          DSPI_CTAR_PDT(0) | \
 191                                          DSPI_CTAR_CSSCK(0) | \
 192                                          DSPI_CTAR_ASC(0) | \
 193                                          DSPI_CTAR_DT(1))
 194 #endif
 195
 196 /* PCI */
 197 #ifdef CONFIG_CMD_PCI
 198 #define CONFIG_PCI              1
 199 #define CONFIG_PCI_PNP          1
 200 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
 201
 202 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  4
 203
 204 #define CONFIG_SYS_PCI_MEM_BUS          0xA0000000
 205 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
 206 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
 207
 208 #define CONFIG_SYS_PCI_IO_BUS           0xB1000000
 209 #define CONFIG_SYS_PCI_IO_PHYS          CONFIG_SYS_PCI_IO_BUS
 210 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000
 211
 212 #define CONFIG_SYS_PCI_CFG_BUS          0xB0000000
 213 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
 214 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
 215 #endif
 216
 217 /* FPGA - Spartan 2 */
 218 /* experiment
 219 #define CONFIG_FPGA
 220 #define CONFIG_FPGA_COUNT       1
 221 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 222 #define CONFIG_SYS_FPGA_CHECK_CTRLC
 223 */
 224
 225 /* Input, PCI, Flexbus, and VCO */
 226 #define CONFIG_EXTRA_CLOCK
 227
 228 #define CONFIG_PRAM             2048    /* 2048 KB */
 229
 230 #define CONFIG_SYS_PROMPT               "-> "
 231 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 232
 233 #if defined(CONFIG_CMD_KGDB)
 234 #define CONFIG_SYS_CBSIZE                       1024    /* Console I/O Buffer Size */
 235 #else
 236 #define CONFIG_SYS_CBSIZE                       256     /* Console I/O Buffer Size */
 237 #endif
 238 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 239 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 240 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 241
 242 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x10000)
 243
 244 #define CONFIG_SYS_MBAR         0xFC000000
 245
 246 /*
 247  * Low Level Configuration Settings
 248  * (address mappings, register initial values, etc.)
 249  * You should know what you are doing if you make changes here.
 250  */
 251
 252 /*-----------------------------------------------------------------------
 253  * Definitions for initial stack pointer and data area (in DPRAM)
 254  */
 255 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 256 #define CONFIG_SYS_INIT_RAM_SIZE                0x8000  /* Size of used area in internal SRAM */
 257 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 258 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 259 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 260 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 261
 262 /*-----------------------------------------------------------------------
 263  * Start addresses for the final memory configuration
 264  * (Set up by the startup code)
 265  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 266  */
 267 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 268 #define CONFIG_SYS_SDRAM_BASE1          0x48000000
 269 #define CONFIG_SYS_SDRAM_SIZE           256     /* SDRAM size in MB */
 270 #define CONFIG_SYS_SDRAM_CFG1           0x65311610
 271 #define CONFIG_SYS_SDRAM_CFG2           0x59670000
 272 #define CONFIG_SYS_SDRAM_CTRL           0xEA0B2000
 273 #define CONFIG_SYS_SDRAM_EMOD           0x40010000
 274 #define CONFIG_SYS_SDRAM_MODE           0x00010033
 275 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0xAA
 276
 277 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 278 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 279
 280 #ifdef CONFIG_CF_SBF
 281 #       define CONFIG_SERIAL_BOOT
 282 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 283 #else
 284 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 285 #endif
 286 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 287 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 288
 289 /* Reserve 256 kB for malloc() */
 290 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 291
 292 /*
 293  * For booting Linux, the board info and command line data
 294  * have to be in the first 8 MB of memory, since this is
 295  * the maximum mapped by the Linux kernel during initialization ??
 296  */
 297 /* Initial Memory map for Linux */
 298 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 299
 300 /*
 301  * Configuration for environment
 302  * Environment is not embedded in u-boot. First time runing may have env
 303  * crc error warning if there is no correct environment on the flash.
 304  */
 305 #ifdef CONFIG_CF_SBF
 306 #       define CONFIG_ENV_IS_IN_SPI_FLASH
 307 #       define CONFIG_ENV_SPI_CS                1
 308 #else
 309 #       define CONFIG_ENV_IS_IN_FLASH   1
 310 #endif
 311 #undef CONFIG_ENV_OVERWRITE
 312
 313 /*-----------------------------------------------------------------------
 314  * FLASH organization
 315  */
 316 #ifdef CONFIG_SYS_STMICRO_BOOT
 317 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 318 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS1_BASE
 319 #       define CONFIG_ENV_OFFSET                0x30000
 320 #       define CONFIG_ENV_SIZE          0x2000
 321 #       define CONFIG_ENV_SECT_SIZE     0x10000
 322 #endif
 323 #ifdef CONFIG_SYS_ATMEL_BOOT
 324 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 325 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
 326 #       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS1_BASE
 327 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 328 #       define CONFIG_ENV_SIZE          0x2000
 329 #       define CONFIG_ENV_SECT_SIZE     0x10000
 330 #endif
 331 #ifdef CONFIG_SYS_INTEL_BOOT
 332 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 333 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
 334 #       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS1_BASE
 335 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 336 #       define CONFIG_ENV_SIZE          0x2000
 337 #       define CONFIG_ENV_SECT_SIZE     0x20000
 338 #endif
 339
 340 #define CONFIG_SYS_FLASH_CFI
 341 #ifdef CONFIG_SYS_FLASH_CFI
 342
 343 #       define CONFIG_FLASH_CFI_DRIVER  1
 344 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 345 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 346 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_8BIT
 347 #       define CONFIG_SYS_MAX_FLASH_BANKS       2       /* max number of memory banks */
 348 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 349 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 350 #       define CONFIG_SYS_FLASH_CHECKSUM
 351 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
 352 #       define CONFIG_FLASH_CFI_LEGACY
 353
 354 #ifdef CONFIG_FLASH_CFI_LEGACY
 355 #       define CONFIG_SYS_ATMEL_REGION          4
 356 #       define CONFIG_SYS_ATMEL_TOTALSECT       11
 357 #       define CONFIG_SYS_ATMEL_SECT            {1, 2, 1, 7}
 358 #       define CONFIG_SYS_ATMEL_SECTSZ          {0x4000, 0x2000, 0x8000, 0x10000}
 359 #endif
 360 #endif
 361
 362 /*
 363  * This is setting for JFFS2 support in u-boot.
 364  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 365  */
 366 #ifdef CONFIG_CMD_JFFS2
 367 #ifdef CF_STMICRO_BOOT
 368 #       define CONFIG_JFFS2_DEV         "nor1"
 369 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 370 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
 371 #endif
 372 #ifdef CONFIG_SYS_ATMEL_BOOT
 373 #       define CONFIG_JFFS2_DEV         "nor1"
 374 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 375 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
 376 #endif
 377 #ifdef CONFIG_SYS_INTEL_BOOT
 378 #       define CONFIG_JFFS2_DEV         "nor0"
 379 #       define CONFIG_JFFS2_PART_SIZE   (0x01000000 - 0x500000)
 380 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
 381 #endif
 382 #endif
 383
 384 /*-----------------------------------------------------------------------
 385  * Cache Configuration
 386  */
 387 #define CONFIG_SYS_CACHELINE_SIZE               16
 388
 389 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 390                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 391 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 392                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 393 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA)
 394 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 395 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 396                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 397                                          CF_ACR_EN | CF_ACR_SM_ALL)
 398 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_IEC | \
 399                                          CF_CACR_ICINVA | CF_CACR_EUSP)
 400 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 401                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 402                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 403
 404 /*-----------------------------------------------------------------------
 405  * Memory bank definitions
 406  */
 407 /*
 408  * CS0 - NOR Flash 1, 2, 4, or 8MB
 409  * CS1 - CompactFlash and registers
 410  * CS2 - CPLD
 411  * CS3 - FPGA
 412  * CS4 - Available
 413  * CS5 - Available
 414  */
 415
 416 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
 417  /* Atmel Flash */
 418 #define CONFIG_SYS_CS0_BASE             0x04000000
 419 #define CONFIG_SYS_CS0_MASK             0x00070001
 420 #define CONFIG_SYS_CS0_CTRL             0x00001140
 421 /* Intel Flash */
 422 #define CONFIG_SYS_CS1_BASE             0x00000000
 423 #define CONFIG_SYS_CS1_MASK             0x01FF0001
 424 #define CONFIG_SYS_CS1_CTRL             0x00000D60
 425
 426 #define CONFIG_SYS_ATMEL_BASE           CONFIG_SYS_CS0_BASE
 427 #else
 428 /* Intel Flash */
 429 #define CONFIG_SYS_CS0_BASE             0x00000000
 430 #define CONFIG_SYS_CS0_MASK             0x01FF0001
 431 #define CONFIG_SYS_CS0_CTRL             0x00000D60
 432  /* Atmel Flash */
 433 #define CONFIG_SYS_CS1_BASE             0x04000000
 434 #define CONFIG_SYS_CS1_MASK             0x00070001
 435 #define CONFIG_SYS_CS1_CTRL             0x00001140
 436
 437 #define CONFIG_SYS_ATMEL_BASE           CONFIG_SYS_CS1_BASE
 438 #endif
 439
 440 /* CPLD */
 441 #define CONFIG_SYS_CS2_BASE             0x08000000
 442 #define CONFIG_SYS_CS2_MASK             0x00070001
 443 #define CONFIG_SYS_CS2_CTRL             0x003f1140
 444
 445 /* FPGA */
 446 #define CONFIG_SYS_CS3_BASE             0x09000000
 447 #define CONFIG_SYS_CS3_MASK             0x00070001
 448 #define CONFIG_SYS_CS3_CTRL             0x00000020
 449
 450 #endif                          /* _M54455EVB_H */