include/configs/M5485EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF5485 FireEngine board.
   3  *
   4  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M5485EVB_H
  15 #define _M5485EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21
  22 #define CONFIG_MCFUART
  23 #define CONFIG_SYS_UART_PORT            (0)
  24
  25 #undef CONFIG_HW_WATCHDOG
  26 #define CONFIG_WATCHDOG_TIMEOUT 5000    /* timeout in milliseconds, max timeout is 6.71sec */
  27
  28 /* Command line configuration */
  29 #undef CONFIG_CMD_DATE
  30 #define CONFIG_CMD_PCI
  31 #define CONFIG_CMD_REGINFO
  32
  33 #define CONFIG_SLTTMR
  34
  35 #define CONFIG_FSLDMAFEC
  36 #ifdef CONFIG_FSLDMAFEC
  37 #       define CONFIG_MII               1
  38 #       define CONFIG_MII_INIT          1
  39 #       define CONFIG_HAS_ETH1
  40
  41 #       define CONFIG_SYS_DMA_USE_INTSRAM       1
  42 #       define CONFIG_SYS_DISCOVER_PHY
  43 #       define CONFIG_SYS_RX_ETH_BUFFER 32
  44 #       define CONFIG_SYS_TX_ETH_BUFFER 48
  45 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  46
  47 #       define CONFIG_SYS_FEC0_PINMUX           0
  48 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  49 #       define CONFIG_SYS_FEC1_PINMUX           0
  50 #       define CONFIG_SYS_FEC1_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  51
  52 #       define MCFFEC_TOUT_LOOP         50000
  53 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  54 #       ifndef CONFIG_SYS_DISCOVER_PHY
  55 #               define FECDUPLEX        FULL
  56 #               define FECSPEED         _100BASET
  57 #       else
  58 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  59 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  60 #               endif
  61 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  62
  63 #       define CONFIG_IPADDR    192.162.1.2
  64 #       define CONFIG_NETMASK   255.255.255.0
  65 #       define CONFIG_SERVERIP  192.162.1.1
  66 #       define CONFIG_GATEWAYIP 192.162.1.1
  67
  68 #endif
  69
  70 #ifdef CONFIG_CMD_USB
  71 #       define CONFIG_USB_OHCI_NEW
  72 #       ifndef CONFIG_CMD_PCI
  73 #               define CONFIG_CMD_PCI
  74 #       endif
  75 /*#     define CONFIG_PCI_OHCI*/
  76 #       define CONFIG_SYS_USB_OHCI_REGS_BASE            0x80041000
  77 #       define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS       15
  78 #       define CONFIG_SYS_USB_OHCI_SLOT_NAME            "isp1561"
  79 #       define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
  80 #endif
  81
  82 /* I2C */
  83 #define CONFIG_SYS_I2C
  84 #define CONFIG_SYS_I2C_FSL
  85 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  86 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  87 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00008F00
  88 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
  89
  90 /* PCI */
  91 #ifdef CONFIG_CMD_PCI
  92 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  93
  94 #define CONFIG_SYS_PCI_MEM_BUS          0x80000000
  95 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
  96 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
  97
  98 #define CONFIG_SYS_PCI_IO_BUS           0x71000000
  99 #define CONFIG_SYS_PCI_IO_PHYS          CONFIG_SYS_PCI_IO_BUS
 100 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000
 101
 102 #define CONFIG_SYS_PCI_CFG_BUS          0x70000000
 103 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
 104 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
 105 #endif
 106
 107 #define CONFIG_UDP_CHECKSUM
 108
 109 #define CONFIG_HOSTNAME         M548xEVB
 110 #define CONFIG_EXTRA_ENV_SETTINGS               \
 111         "netdev=eth0\0"                         \
 112         "loadaddr=10000\0"                      \
 113         "u-boot=u-boot.bin\0"                   \
 114         "load=tftp ${loadaddr) ${u-boot}\0"     \
 115         "upd=run load; run prog\0"              \
 116         "prog=prot off bank 1;"                 \
 117         "era ff800000 ff83ffff;"                \
 118         "cp.b ${loadaddr} ff800000 ${filesize};"\
 119         "save\0"                                \
 120         ""
 121
 122 #define CONFIG_PRAM             512     /* 512 KB */
 123 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 124
 125 #ifdef CONFIG_CMD_KGDB
 126 #       define CONFIG_SYS_CBSIZE        1024    /* Console I/O Buffer Size */
 127 #else
 128 #       define CONFIG_SYS_CBSIZE        256     /* Console I/O Buffer Size */
 129 #endif
 130
 131 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 132 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 133 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 134 #define CONFIG_SYS_LOAD_ADDR            0x00010000
 135
 136 #define CONFIG_SYS_CLK                  CONFIG_SYS_BUSCLK
 137 #define CONFIG_SYS_CPU_CLK              CONFIG_SYS_CLK * 2
 138
 139 #define CONFIG_SYS_MBAR         0xF0000000
 140 #define CONFIG_SYS_INTSRAM              (CONFIG_SYS_MBAR + 0x10000)
 141 #define CONFIG_SYS_INTSRAMSZ            0x8000
 142
 143 /*#define CONFIG_SYS_LATCH_ADDR         (CONFIG_SYS_CS1_BASE + 0x80000)*/
 144
 145 /*
 146  * Low Level Configuration Settings
 147  * (address mappings, register initial values, etc.)
 148  * You should know what you are doing if you make changes here.
 149  */
 150 /*-----------------------------------------------------------------------
 151  * Definitions for initial stack pointer and data area (in DPRAM)
 152  */
 153 #define CONFIG_SYS_INIT_RAM_ADDR        0xF2000000
 154 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in internal SRAM */
 155 #define CONFIG_SYS_INIT_RAM_CTRL        0x21
 156 #define CONFIG_SYS_INIT_RAM1_ADDR       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
 157 #define CONFIG_SYS_INIT_RAM1_END        0x1000  /* End of used area in internal SRAM */
 158 #define CONFIG_SYS_INIT_RAM1_CTRL       0x21
 159 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 160 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 161
 162 /*-----------------------------------------------------------------------
 163  * Start addresses for the final memory configuration
 164  * (Set up by the startup code)
 165  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 166  */
 167 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 168 #define CONFIG_SYS_SDRAM_CFG1           0x73711630
 169 #define CONFIG_SYS_SDRAM_CFG2           0x46770000
 170 #define CONFIG_SYS_SDRAM_CTRL           0xE10B0000
 171 #define CONFIG_SYS_SDRAM_EMOD           0x40010000
 172 #define CONFIG_SYS_SDRAM_MODE           0x018D0000
 173 #define CONFIG_SYS_SDRAM_DRVSTRENGTH    0x000002AA
 174 #ifdef CONFIG_SYS_DRAMSZ1
 175 #       define CONFIG_SYS_SDRAM_SIZE    (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
 176 #else
 177 #       define CONFIG_SYS_SDRAM_SIZE    CONFIG_SYS_DRAMSZ
 178 #endif
 179
 180 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 181 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 182
 183 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 184 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 185
 186 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 187
 188 /* Reserve 256 kB for malloc() */
 189 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 190 /*
 191  * For booting Linux, the board info and command line data
 192  * have to be in the first 8 MB of memory, since this is
 193  * the maximum mapped by the Linux kernel during initialization ??
 194  */
 195 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 196
 197 /*-----------------------------------------------------------------------
 198  * FLASH organization
 199  */
 200 #define CONFIG_SYS_FLASH_CFI
 201 #ifdef CONFIG_SYS_FLASH_CFI
 202 #       define CONFIG_SYS_FLASH_BASE            (CONFIG_SYS_CS0_BASE)
 203 #       define CONFIG_FLASH_CFI_DRIVER  1
 204 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 205 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 206 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 207 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 208 #ifdef CONFIG_SYS_NOR1SZ
 209 #       define CONFIG_SYS_MAX_FLASH_BANKS       2       /* max number of memory banks */
 210 #       define CONFIG_SYS_FLASH_SIZE            ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
 211 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
 212 #else
 213 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 214 #       define CONFIG_SYS_FLASH_SIZE            (CONFIG_SYS_BOOTSZ << 20)
 215 #endif
 216 #endif
 217
 218 /* Configuration for environment
 219  * Environment is not embedded in u-boot. First time runing may have env
 220  * crc error warning if there is no correct environment on the flash.
 221  */
 222 #define CONFIG_ENV_OFFSET               0x40000
 223 #define CONFIG_ENV_SECT_SIZE    0x10000
 224 #define CONFIG_ENV_IS_IN_FLASH  1
 225
 226 /*-----------------------------------------------------------------------
 227  * Cache Configuration
 228  */
 229 #define CONFIG_SYS_CACHELINE_SIZE       16
 230
 231 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 232                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 233 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 234                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 235 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA + \
 236                                          CF_CACR_IDCM)
 237 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 238 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 239                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 240                                          CF_ACR_EN | CF_ACR_SM_ALL)
 241 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_BCINVA | \
 242                                          CF_CACR_IEC | CF_CACR_ICINVA)
 243 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 244                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 245                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 246
 247 /*-----------------------------------------------------------------------
 248  * Chipselect bank definitions
 249  */
 250 /*
 251  * CS0 - NOR Flash 1, 2, 4, or 8MB
 252  * CS1 - NOR Flash
 253  * CS2 - Available
 254  * CS3 - Available
 255  * CS4 - Available
 256  * CS5 - Available
 257  */
 258 #define CONFIG_SYS_CS0_BASE             0xFF800000
 259 #define CONFIG_SYS_CS0_MASK             (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
 260 #define CONFIG_SYS_CS0_CTRL             0x00101980
 261
 262 #ifdef CONFIG_SYS_NOR1SZ
 263 #define CONFIG_SYS_CS1_BASE             0xE0000000
 264 #define CONFIG_SYS_CS1_MASK             (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
 265 #define CONFIG_SYS_CS1_CTRL             0x00101D80
 266 #endif
 267
 268 #endif                          /* _M5485EVB_H */