include/configs/M5485EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF5485 FireEngine board.
   3  *
   4  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /*
  27  * board/config.h - configuration options, board specific
  28  */
  29
  30 #ifndef _M5485EVB_H
  31 #define _M5485EVB_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37 #define CONFIG_MCF547x_8x       /* define processor family */
  38 #define CONFIG_M548x            /* define processor type */
  39 #define CONFIG_M5485            /* define processor type */
  40
  41 #define CONFIG_MCFUART
  42 #define CONFIG_SYS_UART_PORT            (0)
  43 #define CONFIG_BAUDRATE         115200
  44 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600 , 19200 , 38400 , 57600, 115200 }
  45
  46 #define CONFIG_HW_WATCHDOG
  47 #define CONFIG_WATCHDOG_TIMEOUT 5000    /* timeout in milliseconds, max timeout is 6.71sec */
  48
  49 /* Command line configuration */
  50 #include <config_cmd_default.h>
  51
  52 #define CONFIG_CMD_CACHE
  53 #undef CONFIG_CMD_DATE
  54 #define CONFIG_CMD_ELF
  55 #define CONFIG_CMD_FLASH
  56 #define CONFIG_CMD_I2C
  57 #define CONFIG_CMD_MEMORY
  58 #define CONFIG_CMD_MISC
  59 #define CONFIG_CMD_MII
  60 #define CONFIG_CMD_NET
  61 #define CONFIG_CMD_PCI
  62 #define CONFIG_CMD_PING
  63 #define CONFIG_CMD_REGINFO
  64 #define CONFIG_CMD_USB
  65
  66 #define CONFIG_SLTTMR
  67
  68 #define CONFIG_FSLDMAFEC
  69 #ifdef CONFIG_FSLDMAFEC
  70 #       define CONFIG_MII               1
  71 #       define CONFIG_MII_INIT          1
  72 #       define CONFIG_HAS_ETH1
  73
  74 #       define CONFIG_SYS_DMA_USE_INTSRAM       1
  75 #       define CONFIG_SYS_DISCOVER_PHY
  76 #       define CONFIG_SYS_RX_ETH_BUFFER 32
  77 #       define CONFIG_SYS_TX_ETH_BUFFER 48
  78 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  79
  80 #       define CONFIG_SYS_FEC0_PINMUX           0
  81 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  82 #       define CONFIG_SYS_FEC1_PINMUX           0
  83 #       define CONFIG_SYS_FEC1_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  84
  85 #       define MCFFEC_TOUT_LOOP         50000
  86 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  87 #       ifndef CONFIG_SYS_DISCOVER_PHY
  88 #               define FECDUPLEX        FULL
  89 #               define FECSPEED         _100BASET
  90 #       else
  91 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  92 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  93 #               endif
  94 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  95
  96 #       define CONFIG_ETHADDR   00:e0:0c:bc:e5:60
  97 #       define CONFIG_ETH1ADDR  00:e0:0c:bc:e5:61
  98 #       define CONFIG_IPADDR    192.162.1.2
  99 #       define CONFIG_NETMASK   255.255.255.0
 100 #       define CONFIG_SERVERIP  192.162.1.1
 101 #       define CONFIG_GATEWAYIP 192.162.1.1
 102 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
 103
 104 #endif
 105
 106 #ifdef CONFIG_CMD_USB
 107 #       define CONFIG_USB_STORAGE
 108 #       define CONFIG_DOS_PARTITION
 109 #       define CONFIG_USB_OHCI_NEW
 110 #       ifndef CONFIG_CMD_PCI
 111 #               define CONFIG_CMD_PCI
 112 #       endif
 113 /*#     define CONFIG_PCI_OHCI*/
 114 #       define CONFIG_SYS_USB_OHCI_REGS_BASE            0x80041000
 115 #       define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS       15
 116 #       define CONFIG_SYS_USB_OHCI_SLOT_NAME            "isp1561"
 117 #       define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 118 #endif
 119
 120 /* I2C */
 121 #define CONFIG_FSL_I2C
 122 #define CONFIG_HARD_I2C         /* I2C with hw support */
 123 #undef CONFIG_SOFT_I2C          /* I2C bit-banged */
 124 #define CONFIG_SYS_I2C_SPEED            80000
 125 #define CONFIG_SYS_I2C_SLAVE            0x7F
 126 #define CONFIG_SYS_I2C_OFFSET           0x00008F00
 127 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 128
 129 /* PCI */
 130 #ifdef CONFIG_CMD_PCI
 131 #define CONFIG_PCI              1
 132 #define CONFIG_PCI_PNP          1
 133 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
 134
 135 #define CONFIG_SYS_PCI_MEM_BUS          0x80000000
 136 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
 137 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
 138
 139 #define CONFIG_SYS_PCI_IO_BUS           0x71000000
 140 #define CONFIG_SYS_PCI_IO_PHYS          CONFIG_SYS_PCI_IO_BUS
 141 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000
 142
 143 #define CONFIG_SYS_PCI_CFG_BUS          0x70000000
 144 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
 145 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
 146 #endif
 147
 148 #define CONFIG_BOOTDELAY        1       /* autoboot after 5 seconds */
 149 #define CONFIG_UDP_CHECKSUM
 150
 151 #define CONFIG_HOSTNAME         M548xEVB
 152 #define CONFIG_EXTRA_ENV_SETTINGS               \
 153         "netdev=eth0\0"                         \
 154         "loadaddr=10000\0"                      \
 155         "u-boot=u-boot.bin\0"                   \
 156         "load=tftp ${loadaddr) ${u-boot}\0"     \
 157         "upd=run load; run prog\0"              \
 158         "prog=prot off bank 1;"                 \
 159         "era ff800000 ff83ffff;"                \
 160         "cp.b ${loadaddr} ff800000 ${filesize};"\
 161         "save\0"                                \
 162         ""
 163
 164 #define CONFIG_PRAM             512     /* 512 KB */
 165 #define CONFIG_SYS_PROMPT               "-> "
 166 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 167
 168 #ifdef CONFIG_CMD_KGDB
 169 #       define CONFIG_SYS_CBSIZE        1024    /* Console I/O Buffer Size */
 170 #else
 171 #       define CONFIG_SYS_CBSIZE        256     /* Console I/O Buffer Size */
 172 #endif
 173
 174 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 175 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 176 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 177 #define CONFIG_SYS_LOAD_ADDR            0x00010000
 178
 179 #define CONFIG_SYS_HZ                   1000
 180 #define CONFIG_SYS_CLK                  CONFIG_SYS_BUSCLK
 181 #define CONFIG_SYS_CPU_CLK              CONFIG_SYS_CLK * 2
 182
 183 #define CONFIG_SYS_MBAR         0xF0000000
 184 #define CONFIG_SYS_INTSRAM              (CONFIG_SYS_MBAR + 0x10000)
 185 #define CONFIG_SYS_INTSRAMSZ            0x8000
 186
 187 /*#define CONFIG_SYS_LATCH_ADDR         (CONFIG_SYS_CS1_BASE + 0x80000)*/
 188
 189 /*
 190  * Low Level Configuration Settings
 191  * (address mappings, register initial values, etc.)
 192  * You should know what you are doing if you make changes here.
 193  */
 194 /*-----------------------------------------------------------------------
 195  * Definitions for initial stack pointer and data area (in DPRAM)
 196  */
 197 #define CONFIG_SYS_INIT_RAM_ADDR        0xF2000000
 198 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in internal SRAM */
 199 #define CONFIG_SYS_INIT_RAM_CTRL        0x21
 200 #define CONFIG_SYS_INIT_RAM1_ADDR       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
 201 #define CONFIG_SYS_INIT_RAM1_END        0x1000  /* End of used area in internal SRAM */
 202 #define CONFIG_SYS_INIT_RAM1_CTRL       0x21
 203 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 204 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 205
 206 /*-----------------------------------------------------------------------
 207  * Start addresses for the final memory configuration
 208  * (Set up by the startup code)
 209  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 210  */
 211 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 212 #define CONFIG_SYS_SDRAM_CFG1           0x73711630
 213 #define CONFIG_SYS_SDRAM_CFG2           0x46770000
 214 #define CONFIG_SYS_SDRAM_CTRL           0xE10B0000
 215 #define CONFIG_SYS_SDRAM_EMOD           0x40010000
 216 #define CONFIG_SYS_SDRAM_MODE           0x018D0000
 217 #define CONFIG_SYS_SDRAM_DRVSTRENGTH    0x000002AA
 218 #ifdef CONFIG_SYS_DRAMSZ1
 219 #       define CONFIG_SYS_SDRAM_SIZE    (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
 220 #else
 221 #       define CONFIG_SYS_SDRAM_SIZE    CONFIG_SYS_DRAMSZ
 222 #endif
 223
 224 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 225 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 226
 227 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 228 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 229
 230 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 231
 232 /* Reserve 256 kB for malloc() */
 233 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 234 /*
 235  * For booting Linux, the board info and command line data
 236  * have to be in the first 8 MB of memory, since this is
 237  * the maximum mapped by the Linux kernel during initialization ??
 238  */
 239 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 240
 241 /*-----------------------------------------------------------------------
 242  * FLASH organization
 243  */
 244 #define CONFIG_SYS_FLASH_CFI
 245 #ifdef CONFIG_SYS_FLASH_CFI
 246 #       define CONFIG_SYS_FLASH_BASE            (CONFIG_SYS_CS0_BASE)
 247 #       define CONFIG_FLASH_CFI_DRIVER  1
 248 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 249 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 250 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 251 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 252 #ifdef CONFIG_SYS_NOR1SZ
 253 #       define CONFIG_SYS_MAX_FLASH_BANKS       2       /* max number of memory banks */
 254 #       define CONFIG_SYS_FLASH_SIZE            ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
 255 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
 256 #else
 257 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 258 #       define CONFIG_SYS_FLASH_SIZE            (CONFIG_SYS_BOOTSZ << 20)
 259 #endif
 260 #endif
 261
 262 /* Configuration for environment
 263  * Environment is not embedded in u-boot. First time runing may have env
 264  * crc error warning if there is no correct environment on the flash.
 265  */
 266 #define CONFIG_ENV_OFFSET               0x40000
 267 #define CONFIG_ENV_SECT_SIZE    0x10000
 268 #define CONFIG_ENV_IS_IN_FLASH  1
 269
 270 /*-----------------------------------------------------------------------
 271  * Cache Configuration
 272  */
 273 #define CONFIG_SYS_CACHELINE_SIZE       16
 274
 275 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 276                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 277 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 278                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 279 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA + \
 280                                          CF_CACR_IDCM)
 281 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 282 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 283                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 284                                          CF_ACR_EN | CF_ACR_SM_ALL)
 285 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_BCINVA | \
 286                                          CF_CACR_IEC | CF_CACR_ICINVA)
 287 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 288                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 289                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 290
 291 /*-----------------------------------------------------------------------
 292  * Chipselect bank definitions
 293  */
 294 /*
 295  * CS0 - NOR Flash 1, 2, 4, or 8MB
 296  * CS1 - NOR Flash
 297  * CS2 - Available
 298  * CS3 - Available
 299  * CS4 - Available
 300  * CS5 - Available
 301  */
 302 #define CONFIG_SYS_CS0_BASE             0xFF800000
 303 #define CONFIG_SYS_CS0_MASK             (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
 304 #define CONFIG_SYS_CS0_CTRL             0x00101980
 305
 306 #ifdef CONFIG_SYS_NOR1SZ
 307 #define CONFIG_SYS_CS1_BASE             0xE0000000
 308 #define CONFIG_SYS_CS1_MASK             (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
 309 #define CONFIG_SYS_CS1_CTRL             0x00101D80
 310 #endif
 311
 312 #endif                          /* _M5485EVB_H */