include/configs/MBX860T.h

   1  /*
   2   * A collection of structures, addresses, and values associated with
   3   * the Motorola 860T MBX board.
   4   * Copied from the FADS stuff, which was originally copied from the MBX stuff!
   5   * Magnus Damm added defines for 8xxrom and extended bd_info.
   6   * Helmut Buchsbaum added bitvalues for BCSRx
   7   * Rob Taylor coverted it back to MBX
   8   *
   9   * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
  10   */
  11
  12 /* ------------------------------------------------------------------------- */
  13
  14 /*
  15  * board/config.h - configuration options, board specific
  16  */
  17
  18 #ifndef __CONFIG_H
  19 #define __CONFIG_H
  20
  21 /*
  22  * High Level Configuration Options
  23  * (easy to change)
  24  */
  25 #include <mpc8xx_irq.h>
  26
  27 #define CONFIG_MPC860           1
  28 #define CONFIG_MPC860T          1
  29 #define CONFIG_MBX              1
  30
  31 #define CONFIG_SYS_TEXT_BASE    0xfe000000
  32
  33 #define CONFIG_8xx_CPUCLOCK     40
  34 #define CONFIG_8xx_BUSCLOCK     (CONFIG_8xx_CPUCLOCK)
  35 #define TARGET_SYSTEM_FREQUENCY 40
  36
  37 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  38 #undef  CONFIG_8xx_CONS_SMC2
  39 #define CONFIG_BAUDRATE         9600
  40
  41 #define MPC8XX_FACT     10                              /* Multiply by 10               */
  42 #define MPC8XX_XIN      40000000                /* 50 MHz in    */
  43 #define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
  44
  45 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  46
  47 #if 1
  48 #define CONFIG_8xx_BOOTDELAY    -1      /* autoboot disabled            */
  49 #define CONFIG_8xx_TFTP_MODE
  50 #else
  51 #define CONFIG_8xx_BOOTDELAY    5       /* autoboot after 5 seconds     */
  52 #undef  CONFIG_8xx_TFTP_MODE
  53 #endif
  54
  55 #define CONFIG_MISC_INIT_R
  56
  57 #define CONFIG_DRAM_SPEED       (CONFIG_8xx_BUSCLOCK)   /* MHz          */
  58 #define CONFIG_BOOTCOMMAND      "bootm FE020000"        /* autoboot command */
  59 #define CONFIG_BOOTARGS         " "
  60 /*
  61  * Miscellaneous configurable options
  62  */
  63 #undef  CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  64 #define CONFIG_SYS_PROMPT               ":>"            /* Monitor Command Prompt       */
  65 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
  66 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  67 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  68 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  69
  70 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
  71 #define CONFIG_SYS_MEMTEST_END          0x0800000       /* 4 ... 8 MB in DRAM   */
  72
  73 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
  74
  75 /*
  76  * Low Level Configuration Settings
  77  * (address mappings, register initial values, etc.)
  78  * You should know what you are doing if you make changes here.
  79  */
  80 /*-----------------------------------------------------------------------
  81  * Internal Memory Mapped Register
  82  */
  83 #define CONFIG_SYS_IMMR                 0xFFA00000
  84 #define CONFIG_SYS_IMMR_SIZE            ((uint)(64 * 1024))
  85 #define CONFIG_SYS_NVRAM_BASE           0xFA000000 /* NVRAM                          */
  86 #define CONFIG_SYS_NVRAM_OR             0xffe00000 /* w/o speed dependent flags!!    */
  87 #define CONFIG_SYS_CSR_BASE             0xFA100000 /* Control/Status Registers       */
  88 #define CONFIG_SYS_PCIMEM_BASE          0x80000000 /* PCI I/O and Memory Spaces      */
  89 #define CONFIG_SYS_PCIMEM_OR            0xA0000108
  90 #define CONFIG_SYS_PCIBRIDGE_BASE       0xFA210000 /* PCI-Bus Bridge Registers       */
  91 #define CONFIG_SYS_PCIBRIDGE_OR 0xFFFF0108
  92
  93 /*-----------------------------------------------------------------------
  94  * Definitions for initial stack pointer and data area (in DPRAM)
  95  */
  96 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
  97 #define CONFIG_SYS_INIT_RAM_SIZE        0x2f00  /* Size of used area in DPRAM   */
  98 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  99 #define CONFIG_SYS_INIT_VPD_SIZE        256 /* size in bytes reserved for vpd buffer */
 100 #define CONFIG_SYS_INIT_VPD_OFFSET      (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
 101 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_VPD_OFFSET-8)
 102
 103 /*-----------------------------------------------------------------------
 104  * Offset in DPMEM where we keep the VPD data
 105  */
 106 #define CONFIG_SYS_DPRAMVPD             (CONFIG_SYS_INIT_VPD_OFFSET - 0x2000)
 107
 108 /*-----------------------------------------------------------------------
 109  * Start addresses for the final memory configuration
 110  * (Set up by the startup code)
 111  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 112  */
 113 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 114 #define CONFIG_SYS_FLASH_BASE           0x00000000
 115 /*0xFE000000*/
 116 #define CONFIG_SYS_FLASH_SIZE           ((uint)(8 * 1024 * 1024))       /* max 8Mbyte */
 117 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 118 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 119 #define CONFIG_SYS_HWINFO_ADDR          (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_SYS_HWINFO_LEN)
 120 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 256 kB for malloc()  */
 121
 122 /*
 123  * For booting Linux, the board info and command line data
 124  * have to be in the first 8 MB of memory, since this is
 125  * the maximum mapped by the Linux kernel during initialization.
 126  */
 127 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 128
 129 /*-----------------------------------------------------------------------
 130  * FLASH organization
 131  */
 132 #define CONFIG_SYS_MAX_FLASH_BANKS      4       /* max number of memory banks           */
 133 #define CONFIG_SYS_MAX_FLASH_SECT       16      /* max number of sectors on one chip    */
 134
 135 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 136 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 137
 138 /*-----------------------------------------------------------------------
 139  * NVRAM Configuration
 140  *
 141  * Note: the MBX is special because there is already a firmware on this
 142  * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
 143  * access the NVRAM at the offset 0x1000.
 144  */
 145 #define CONFIG_ENV_IS_IN_NVRAM  1       /* turn on NVRAM env feature */
 146 #define CONFIG_ENV_ADDR         (CONFIG_SYS_NVRAM_BASE + 0x1000)
 147 #define CONFIG_ENV_SIZE         0x1000
 148
 149 /*-----------------------------------------------------------------------
 150  * Cache Configuration
 151  */
 152 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 153 #if defined(CONFIG_CMD_KGDB)
 154 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 155 #endif
 156
 157 /*-----------------------------------------------------------------------
 158  * SYPCR - System Protection Control                            11-9
 159  * SYPCR can only be written once after reset!
 160  *-----------------------------------------------------------------------
 161  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 162  */
 163 #if defined(CONFIG_WATCHDOG)
 164 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 165                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 166 #else
 167 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
 168 #endif
 169
 170 /*-----------------------------------------------------------------------
 171  * SIUMCR - SIU Module Configuration                            11-6
 172  *-----------------------------------------------------------------------
 173  * PCMCIA config., multi-function pin tri-state
 174  */
 175 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME)
 176
 177 /*-----------------------------------------------------------------------
 178  * TBSCR - Time Base Status and Control                         11-26
 179  *-----------------------------------------------------------------------
 180  * Clear Reference Interrupt Status, Timebase freezing enabled
 181  */
 182 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 183
 184 /*-----------------------------------------------------------------------
 185  * PISCR - Periodic Interrupt Status and Control                11-31
 186  *-----------------------------------------------------------------------
 187  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 188  */
 189 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF | PISCR_PTE)
 190
 191 /*-----------------------------------------------------------------------
 192  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 193  *-----------------------------------------------------------------------
 194  * Reset PLL lock status sticky bit, timer expired status bit and timer
 195  * interrupt status bit - leave PLL multiplication factor unchanged !
 196  */
 197 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 198
 199 /*-----------------------------------------------------------------------
 200  * SCCR - System Clock and reset Control Register               15-27
 201  *-----------------------------------------------------------------------
 202  * Set clock output, timebase and RTC source and divider,
 203  * power management and some other internal clocks
 204  */
 205 #define SCCR_MASK       (SCCR_RTDIV | SCCR_RTSEL)
 206 #define CONFIG_SYS_SCCR SCCR_TBS
 207
 208  /*-----------------------------------------------------------------------
 209  *
 210  *-----------------------------------------------------------------------
 211  *
 212  */
 213 #define CONFIG_SYS_DER          0
 214
 215 /* Because of the way the 860 starts up and assigns CS0 the
 216 * entire address space, we have to set the memory controller
 217 * differently.  Normally, you write the option register
 218 * first, and then enable the chip select by writing the
 219 * base register.  For CS0, you must write the base register
 220 * first, followed by the option register.
 221 */
 222
 223 /*
 224  * Init Memory Controller:
 225  *
 226  * BR0/1 and OR0/1 (FLASH)
 227  */
 228 /* the other CS:s are determined by looking at parameters in BCSRx */
 229
 230
 231 #define BCSR_ADDR               ((uint) 0xFF010000)
 232 #define BCSR_SIZE               ((uint)(64 * 1024))
 233
 234 #define FLASH_BASE0_PRELIM      0xFE000000      /* FLASH bank #0        */
 235 #define FLASH_BASE1_PRELIM      0xFF010000      /* FLASH bank #0        */
 236
 237 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 238 #define CONFIG_SYS_PRELIM_OR_AM 0xFFF00000      /* OR addr mask */
 239
 240 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0        */
 241 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 242
 243 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 244 #define CONFIG_SYS_OR0_PRELIM   (0xFF800000 | OR_CSNT_SAM | OR_BI | OR_SCY_3_CLK)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
 245 #define CONFIG_SYS_BR0_PRELIM   (0xFE000000 | BR_V )
 246
 247 /* BCSRx - Board Control and Status Registers */
 248 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 249 #define CONFIG_SYS_OR1_PRELIM   0xFFC00000 | OR_ACS_DIV4
 250 #define CONFIG_SYS_BR1_PRELIM   (0x00000000 | BR_MS_UPMA | BR_V )
 251
 252
 253 /*
 254  * Memory Periodic Timer Prescaler
 255  */
 256
 257 /* periodic timer for refresh */
 258 #define CONFIG_SYS_MAMR_PTA             97              /* start with divider for 100 MHz       */
 259
 260 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 261 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 262 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 263
 264 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 265 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 266 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 267
 268 /*
 269  * MAMR settings for SDRAM
 270  */
 271
 272 /* 8 column SDRAM */
 273 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 274                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 275                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 276 /* 9 column SDRAM */
 277 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 278                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 279                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 280
 281 #define CONFIG_SYS_MAMR         0x13821000
 282
 283 /* values according to the manual */
 284
 285
 286 #define PCMCIA_MEM_ADDR         ((uint)0xff020000)
 287 #define PCMCIA_MEM_SIZE         ((uint)(64 * 1024))
 288
 289 #define BCSR0                   ((uint) (BCSR_ADDR + 00))
 290 #define BCSR1                   ((uint) (BCSR_ADDR + 0x04))
 291 #define BCSR2                   ((uint) (BCSR_ADDR + 0x08))
 292 #define BCSR3                   ((uint) (BCSR_ADDR + 0x0c))
 293 #define BCSR4                   ((uint) (BCSR_ADDR + 0x10))
 294
 295 /* FADS bitvalues by Helmut Buchsbaum
 296  * see MPC8xxADS User's Manual for a proper description
 297  * of the following structures
 298  */
 299
 300 #define BCSR0_ERB       ((uint)0x80000000)
 301 #define BCSR0_IP        ((uint)0x40000000)
 302 #define BCSR0_BDIS      ((uint)0x10000000)
 303 #define BCSR0_BPS_MASK  ((uint)0x0C000000)
 304 #define BCSR0_ISB_MASK  ((uint)0x01800000)
 305 #define BCSR0_DBGC_MASK ((uint)0x00600000)
 306 #define BCSR0_DBPC_MASK ((uint)0x00180000)
 307 #define BCSR0_EBDF_MASK ((uint)0x00060000)
 308
 309 #define BCSR1_FLASH_EN           ((uint)0x80000000)
 310 #define BCSR1_DRAM_EN            ((uint)0x40000000)
 311 #define BCSR1_ETHEN              ((uint)0x20000000)
 312 #define BCSR1_IRDEN              ((uint)0x10000000)
 313 #define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
 314 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
 315 #define BCSR1_BCSR_EN            ((uint)0x02000000)
 316 #define BCSR1_RS232EN_1          ((uint)0x01000000)
 317 #define BCSR1_PCCEN              ((uint)0x00800000)
 318 #define BCSR1_PCCVCC0            ((uint)0x00400000)
 319 #define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
 320 #define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
 321 #define BCSR1_RS232EN_2          ((uint)0x00040000)
 322 #define BCSR1_SDRAM_EN           ((uint)0x00020000)
 323 #define BCSR1_PCCVCC1            ((uint)0x00010000)
 324
 325 #define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
 326 #define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
 327 #define BCSR2_DRAM_PD_SHIFT      (23)
 328 #define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
 329 #define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
 330
 331 #define BCSR3_DBID_MASK          ((ushort)0x3800)
 332 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
 333 #define BCSR3_BREVNR0            ((ushort)0x0080)
 334 #define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
 335 #define BCSR3_BREVN1             ((ushort)0x0008)
 336 #define BCSR3_BREVN2_MASK        ((ushort)0x0003)
 337
 338 #define BCSR4_ETHLOOP            ((uint)0x80000000)
 339 #define BCSR4_TFPLDL             ((uint)0x40000000)
 340 #define BCSR4_TPSQEL             ((uint)0x20000000)
 341 #define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
 342 #ifdef CONFIG_MPC823
 343 #define BCSR4_USB_EN             ((uint)0x08000000)
 344 #endif /* CONFIG_MPC823 */
 345 #ifdef CONFIG_MPC860SAR
 346 #define BCSR4_UTOPIA_EN          ((uint)0x08000000)
 347 #endif /* CONFIG_MPC860SAR */
 348 #ifdef CONFIG_MPC860T
 349 #define BCSR4_FETH_EN            ((uint)0x08000000)
 350 #endif /* CONFIG_MPC860T */
 351 #define BCSR4_USB_SPEED          ((uint)0x04000000)
 352 #define BCSR4_VCCO               ((uint)0x02000000)
 353 #define BCSR4_VIDEO_ON           ((uint)0x00800000)
 354 #define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
 355 #define BCSR4_VIDEO_RST          ((uint)0x00200000)
 356 #define BCSR4_MODEM_EN           ((uint)0x00100000)
 357 #define BCSR4_DATA_VOICE         ((uint)0x00080000)
 358
 359 #define CONFIG_DRAM_40MHZ               1
 360
 361 #ifdef CONFIG_MPC860T
 362
 363 /* Interrupt level assignments.
 364 */
 365 #define FEC_INTERRUPT   SIU_LEVEL1      /* FEC interrupt */
 366
 367 #endif /* CONFIG_MPC860T */
 368
 369 /* We don't use the 8259.
 370 */
 371 #define NR_8259_INTS    0
 372
 373 #define CONFIG_CMD_NET
 374 /*
 375  * MPC8xx CPM Options
 376  */
 377 #define CONFIG_SCC_ENET 1
 378 #define CONFIG_SCC1_ENET 1
 379 #define CONFIG_FEC_ENET 1
 380 #undef  CONFIG_CPM_IIC
 381 #undef  CONFIG_UCODE_PATCH
 382
 383
 384 #define CONFIG_DISK_SPINUP_TIME 1000000
 385
 386
 387 /* PCMCIA configuration */
 388
 389 #define PCMCIA_MAX_SLOTS    2
 390
 391 #ifdef CONFIG_MPC860
 392 #define PCMCIA_SLOT_A 1
 393 #endif
 394
 395 #endif  /* __CONFIG_H */