include/configs/MIP405.h

   1 /*
   2  * (C) Copyright 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /***********************************************************
  32  * High Level Configuration Options
  33  * (easy to change)
  34  ***********************************************************/
  35 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  36 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  37 #define CONFIG_MIP405           1       /* ...on a MIP405 board         */
  38 /***********************************************************
  39  * Note that it may also be a MIP405T board which is a subset of the
  40  * MIP405
  41  ***********************************************************/
  42 /***********************************************************
  43  * WARNING:
  44  * CONFIG_BOOT_PCI is only used for first boot-up and should
  45  * NOT be enabled for production bootloader
  46  ***********************************************************/
  47 /*#define        CONFIG_BOOT_PCI         1*/
  48 /***********************************************************
  49  * Clock
  50  ***********************************************************/
  51 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  52
  53 /***********************************************************
  54  * Command definitions
  55  ***********************************************************/
  56 #define MIP405_COMMON_CMDS \
  57                        (CONFIG_CMD_DFL  | \
  58                         CFG_CMD_IDE     | \
  59                         CFG_CMD_DHCP    | \
  60                         CFG_CMD_CACHE   | \
  61                         CFG_CMD_PCI     | \
  62                         CFG_CMD_IRQ     | \
  63                         CFG_CMD_ECHO    | \
  64                         CFG_CMD_EEPROM  | \
  65                         CFG_CMD_I2C     | \
  66                         CFG_CMD_REGINFO | \
  67                         CFG_CMD_DATE    | \
  68                         CFG_CMD_ELF     | \
  69                         CFG_CMD_MII     | \
  70                         CFG_CMD_SAVES   | \
  71                         CFG_CMD_BSP     )
  72
  73 #if defined(CONFIG_MIP405T)
  74 #define CONFIG_COMMANDS         \
  75                         MIP405_COMMON_CMDS
  76 #else
  77 #define CONFIG_COMMANDS         \
  78                         (MIP405_COMMON_CMDS | \
  79                         CFG_CMD_USB     | \
  80                         CFG_CMD_DOC     )
  81
  82 #endif
  83
  84 /* this must be included AFTER the definition of CONFIG_COMMANDS  (if any) */
  85 #include <cmd_confdefs.h>
  86
  87 #define  CFG_HUSH_PARSER
  88 #define  CFG_PROMPT_HUSH_PS2 "> "
  89 /**************************************************************
  90  * I2C Stuff:
  91  * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
  92  * 0x53.
  93  * The Atmel EEPROM uses 16Bit addressing.
  94  ***************************************************************/
  95
  96 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
  97 #define CFG_I2C_SPEED           50000   /* I2C speed and slave address */
  98 #define CFG_I2C_SLAVE           0x7F
  99
 100 #define CFG_I2C_EEPROM_ADDR     0x53    /* EEPROM 24C128/256            */
 101 #define CFG_I2C_EEPROM_ADDR_LEN 2       /* Bytes of address             */
 102 /* mask of address bits that overflow into the "EEPROM chip address"    */
 103 #undef CFG_I2C_EEPROM_ADDR_OVERFLOW
 104 #define CFG_EEPROM_PAGE_WRITE_BITS 6    /* The Atmel 24C128/256 has     */
 105                                         /* 64 byte page write mode using*/
 106                                         /* last 6 bits of the address   */
 107 #define CFG_EEPROM_PAGE_WRITE_ENABLE    /* enable Page write */
 108 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
 109
 110
 111 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 112 #define CFG_ENV_OFFSET          0x00000 /* environment starts at the beginning of the EEPROM */
 113 #define CFG_ENV_SIZE            0x00800 /* 2k bytes may be used for env vars */
 114
 115 /***************************************************************
 116  * Definitions for Serial Presence Detect EEPROM address
 117  * (to get SDRAM settings)
 118  ***************************************************************/
 119 /*#define SDRAM_EEPROM_WRITE_ADDRESS    0xA0
 120 #define SDRAM_EEPROM_READ_ADDRESS       0xA1
 121 */
 122 /**************************************************************
 123  * Environment definitions
 124  **************************************************************/
 125 #define CONFIG_BAUDRATE         9600    /* STD Baudrate */
 126 #define CONFIG_BOOTDELAY        5
 127 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 128 #define CONFIG_BOOT_RETRY_TIME  -10     /* feature is avaiable but not enabled */
 129 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check console even if bootdelay = 0 */
 130
 131 #define CONFIG_BOOTCOMMAND      "diskboot 400000 0:1; bootm" /* autoboot command                */
 132 #define CONFIG_BOOTARGS         "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
 133
 134 #define CONFIG_IPADDR           10.0.0.100
 135 #define CONFIG_SERVERIP         10.0.0.1
 136 #define CONFIG_PREBOOT
 137 /***************************************************************
 138  * defines if the console is stored in the environment
 139  ***************************************************************/
 140 #define CFG_CONSOLE_IS_IN_ENV   /* stdin, stdout and stderr are in evironment */
 141 /***************************************************************
 142  * defines if an overwrite_console function exists
 143  *************************************************************/
 144 #define CFG_CONSOLE_OVERWRITE_ROUTINE
 145 #define CFG_CONSOLE_INFO_QUIET
 146 /***************************************************************
 147  * defines if the overwrite_console should be stored in the
 148  * environment
 149  **************************************************************/
 150 #undef CFG_CONSOLE_ENV_OVERWRITE
 151
 152 /**************************************************************
 153  * loads config
 154  *************************************************************/
 155 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 156 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 157
 158 #define CONFIG_MISC_INIT_R
 159 /***********************************************************
 160  * Miscellaneous configurable options
 161  **********************************************************/
 162 #define CFG_LONGHELP                    /* undef to save memory         */
 163 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 164 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 165 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 166 #else
 167 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 168 #endif
 169 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 170 #define CFG_MAXARGS     16              /* max number of command args   */
 171 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 172
 173 #define CFG_MEMTEST_START       0x0100000       /* memtest works on     */
 174 #define CFG_MEMTEST_END         0x0C00000       /* 1 ... 12 MB in DRAM  */
 175
 176 #undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
 177 #define CFG_BASE_BAUD       916667
 178
 179 /* The following table includes the supported baudrates */
 180 #define CFG_BAUDRATE_TABLE      \
 181         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 182          57600, 115200, 230400, 460800, 921600 }
 183
 184 #define CFG_LOAD_ADDR   0x400000        /* default load address */
 185 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
 186
 187 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 188
 189 /*-----------------------------------------------------------------------
 190  * PCI stuff
 191  *-----------------------------------------------------------------------
 192  */
 193 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 194 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 195 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 196
 197 #define CONFIG_PCI                      /* include pci support          */
 198 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* configure as pci-host        */
 199 #define CONFIG_PCI_PNP                  /* pci plug-and-play            */
 200                                         /* resource configuration       */
 201 #define CFG_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
 202 #define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
 203 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 204 #define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
 205 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 206 #define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
 207 #define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
 208 #define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 209
 210 /*-----------------------------------------------------------------------
 211  * Start addresses for the final memory configuration
 212  * (Set up by the startup code)
 213  * Please note that CFG_SDRAM_BASE _must_ start at 0
 214  */
 215 #define CFG_SDRAM_BASE          0x00000000
 216 #define CFG_FLASH_BASE          0xFFF80000
 217 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 218 #define CFG_MONITOR_LEN         (512 * 1024)    /* Reserve 512 kB for Monitor   */
 219 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserve 128 kB for malloc()  */
 220
 221 /*
 222  * For booting Linux, the board info and command line data
 223  * have to be in the first 8 MB of memory, since this is
 224  * the maximum mapped by the Linux kernel during initialization.
 225  */
 226 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 227 /*-----------------------------------------------------------------------
 228  * FLASH organization
 229  */
 230 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 231 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 232
 233 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 234 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 235
 236 /*-----------------------------------------------------------------------
 237  * Cache Configuration
 238  */
 239 #define CFG_DCACHE_SIZE         0x4000  /* For IBM 405GPr CPUs                  */
 240 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 241 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 242 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 243 #endif
 244
 245 /*
 246  * Init Memory Controller:
 247  */
 248
 249 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 250 #define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
 251
 252 #define CONFIG_BOARD_PRE_INIT
 253
 254 /* Peripheral Bus Mapping */
 255 #define PER_PLD_ADDR            0xF4000000 /* smallest window is 1MByte 0x10 0000*/
 256 #define PER_UART0_ADDR          0xF4100000 /* smallest window is 1MByte 0x10 0000*/
 257 #define PER_UART1_ADDR          0xF4200000 /* smallest window is 1MByte 0x10 0000*/
 258
 259 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
 260 #define CONFIG_PORT_ADDR        PER_PLD_ADDR + 5
 261
 262
 263 /*-----------------------------------------------------------------------
 264  * Definitions for initial stack pointer and data area (in On Chip SRAM)
 265  */
 266 #define CFG_TEMP_STACK_OCM      1
 267 #define CFG_OCM_DATA_ADDR       0xF0000000
 268 #define CFG_OCM_DATA_SIZE       0x1000
 269 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR       /* inside of On Chip SRAM    */
 270 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE       /* End of On Chip SRAM         */
 271 #define CFG_GBL_DATA_SIZE       64              /* size in bytes reserved for initial data */
 272 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 273 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 274
 275 /*
 276  * Internal Definitions
 277  *
 278  * Boot Flags
 279  */
 280 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 281 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 282
 283
 284 /***********************************************************************
 285  * External peripheral base address
 286  ***********************************************************************/
 287 #define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
 288
 289 /***********************************************************************
 290  * Last Stage Init
 291  ***********************************************************************/
 292 #define CONFIG_LAST_STAGE_INIT
 293 /************************************************************
 294  * Ethernet Stuff
 295  ***********************************************************/
 296 #define CONFIG_MII              1       /* MII PHY management           */
 297 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 298
 299 /************************************************************
 300  * RTC
 301  ***********************************************************/
 302 #define CONFIG_RTC_MC146818
 303 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 304
 305 /************************************************************
 306  * IDE/ATA stuff
 307  ************************************************************/
 308 #if defined(CONFIG_MIP405T)
 309 #define CFG_IDE_MAXBUS          1   /* MIP405T has only one IDE bus     */
 310 #else
 311 #define CFG_IDE_MAXBUS          2   /* max. 2 IDE busses        */
 312 #endif
 313
 314 #define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 315
 316 #define CFG_ATA_BASE_ADDR       CFG_ISA_IO_BASE_ADDRESS /* base address */
 317 #define CFG_ATA_IDE0_OFFSET     0x01F0          /* ide0 offste */
 318 #define CFG_ATA_IDE1_OFFSET     0x0170          /* ide1 offset */
 319 #define CFG_ATA_DATA_OFFSET     0               /* data reg offset      */
 320 #define CFG_ATA_REG_OFFSET      0               /* reg offset */
 321 #define CFG_ATA_ALT_OFFSET      0x200           /* alternate register offset */
 322
 323 #undef  CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
 324 #undef  CONFIG_IDE_LED         /* no led for ide supported     */
 325 #define CONFIG_IDE_RESET       /* reset for ide supported...    */
 326 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
 327
 328 /************************************************************
 329  * ATAPI support (experimental)
 330  ************************************************************/
 331 #define CONFIG_ATAPI                    /* enable ATAPI Support */
 332
 333 /************************************************************
 334  * SCSI support (experimental) only SYM53C8xx supported
 335  ************************************************************/
 336 #undef CONFIG_SCSI_SYM53C8XX
 337
 338 #ifdef CONFIG_SCSI_SYM53C8XX
 339 #define CFG_SCSI_MAX_LUN        8 /* number of supported LUNs */
 340 #define CFG_SCSI_MAX_SCSI_ID    7 /* maximum SCSI ID (0..6) */
 341 #define CFG_SCSI_MAX_DEVICE     CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
 342 #define CFG_SCSI_SPIN_UP_TIME   2
 343 #endif /* CONFIG_SCSI_SYM53C8XX */
 344 /************************************************************
 345  * DISK Partition support
 346  ************************************************************/
 347 #define CONFIG_DOS_PARTITION
 348 #define CONFIG_MAC_PARTITION
 349 #define CONFIG_ISO_PARTITION /* Experimental */
 350
 351 /************************************************************
 352  * Disk-On-Chip configuration
 353  ************************************************************/
 354 #define CFG_MAX_DOC_DEVICE      1       /* Max number of DOC devices            */
 355 #define CFG_DOC_SHORT_TIMEOUT
 356 #define CFG_DOC_SUPPORT_2000
 357 #define CFG_DOC_SUPPORT_MILLENNIUM
 358 /************************************************************
 359  * Keyboard support
 360  ************************************************************/
 361 #undef CONFIG_ISA_KEYBOARD
 362
 363 /************************************************************
 364  * Video support
 365  ************************************************************/
 366 #define CONFIG_VIDEO                    /*To enable video controller support */
 367 #define CONFIG_VIDEO_CT69000
 368 #define CONFIG_CFB_CONSOLE
 369 #define CONFIG_VIDEO_LOGO
 370 #define CONFIG_CONSOLE_EXTRA_INFO
 371 #define CONFIG_VGA_AS_SINGLE_DEVICE
 372 #define CONFIG_VIDEO_SW_CURSOR
 373 #undef CONFIG_VIDEO_ONBOARD
 374 /************************************************************
 375  * USB support EXPERIMENTAL
 376  ************************************************************/
 377 #if !defined(CONFIG_MIP405T)
 378 #define CONFIG_USB_UHCI
 379 #define CONFIG_USB_KEYBOARD
 380 #define CONFIG_USB_STORAGE
 381
 382 /* Enable needed helper functions */
 383 #define CFG_DEVICE_DEREGISTER           /* needs device_deregister */
 384 #endif
 385 /************************************************************
 386  * Debug support
 387  ************************************************************/
 388 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 389 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 390 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 391 #endif
 392
 393 /************************************************************
 394  * Ident
 395  ************************************************************/
 396
 397 #define VERSION_TAG "released"
 398 #if !defined(CONFIG_MIP405T)
 399 #define CONFIG_ISO_STRING "MEV-10072-001"
 400 #else
 401 #define CONFIG_ISO_STRING "MEV-10082-001"
 402 #endif
 403
 404 #if !defined(CONFIG_BOOT_PCI)
 405 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
 406 #else
 407 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
 408 #endif
 409
 410
 411 #endif  /* __CONFIG_H */