]> git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/MIP405.h
bcdba714a540af2d6d57ed0768f2dab640e3cf92
[people/ms/u-boot.git] / include / configs / MIP405.h
1 /*
2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 /*
9 * board/config.h - configuration options, board specific
10 */
11
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14
15 /***********************************************************
16 * High Level Configuration Options
17 * (easy to change)
18 ***********************************************************/
19 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
20
21 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
22
23 /***********************************************************
24 * Note that it may also be a MIP405T board which is a subset of the
25 * MIP405
26 ***********************************************************/
27 /***********************************************************
28 * WARNING:
29 * CONFIG_BOOT_PCI is only used for first boot-up and should
30 * NOT be enabled for production bootloader
31 ***********************************************************/
32 /*#define CONFIG_BOOT_PCI 1*/
33 /***********************************************************
34 * Clock
35 ***********************************************************/
36 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
37
38 /*
39 * BOOTP options
40 */
41 #define CONFIG_BOOTP_BOOTFILESIZE
42 #define CONFIG_BOOTP_BOOTPATH
43 #define CONFIG_BOOTP_GATEWAY
44 #define CONFIG_BOOTP_HOSTNAME
45
46 /*
47 * Command line configuration.
48 */
49 #define CONFIG_CMD_DATE
50 #define CONFIG_CMD_EEPROM
51 #define CONFIG_CMD_IDE
52 #define CONFIG_CMD_IRQ
53 #define CONFIG_CMD_JFFS2
54 #define CONFIG_CMD_PCI
55 #define CONFIG_CMD_REGINFO
56 #define CONFIG_CMD_SAVES
57
58 /**************************************************************
59 * I2C Stuff:
60 * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
61 * 0x53.
62 * The Atmel EEPROM uses 16Bit addressing.
63 ***************************************************************/
64
65 #define CONFIG_SYS_I2C
66 #define CONFIG_SYS_I2C_PPC4XX
67 #define CONFIG_SYS_I2C_PPC4XX_CH0
68 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
69 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
70
71 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
72 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
73 /* mask of address bits that overflow into the "EEPROM chip address" */
74 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
75 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
76 /* 64 byte page write mode using*/
77 /* last 6 bits of the address */
78 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
79
80 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
81 #define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
82 #define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
83
84 /***************************************************************
85 * Definitions for Serial Presence Detect EEPROM address
86 * (to get SDRAM settings)
87 ***************************************************************/
88 /*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
89 #define SDRAM_EEPROM_READ_ADDRESS 0xA1
90 */
91 /**************************************************************
92 * Environment definitions
93 **************************************************************/
94 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
95 /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
96
97 #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
98 #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
99
100 #define CONFIG_IPADDR 10.0.0.100
101 #define CONFIG_SERVERIP 10.0.0.1
102 #define CONFIG_PREBOOT
103 /***************************************************************
104 * defines if an overwrite_console function exists
105 *************************************************************/
106 /***************************************************************
107 * defines if the overwrite_console should be stored in the
108 * environment
109 **************************************************************/
110
111 /**************************************************************
112 * loads config
113 *************************************************************/
114 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
115 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
116
117 #define CONFIG_MISC_INIT_R
118 /***********************************************************
119 * Miscellaneous configurable options
120 **********************************************************/
121 #define CONFIG_SYS_LONGHELP /* undef to save memory */
122 #if defined(CONFIG_CMD_KGDB)
123 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
124 #else
125 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
126 #endif
127 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
128 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
129 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
130
131 #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
132 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
133
134 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
135 #define CONFIG_SYS_NS16550_SERIAL
136 #define CONFIG_SYS_NS16550_REG_SIZE 1
137 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
138
139 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
140 #define CONFIG_SYS_BASE_BAUD 916667
141
142 /* The following table includes the supported baudrates */
143 #define CONFIG_SYS_BAUDRATE_TABLE \
144 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
145 57600, 115200, 230400, 460800, 921600 }
146
147 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
148 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
149
150 /*-----------------------------------------------------------------------
151 * PCI stuff
152 *-----------------------------------------------------------------------
153 */
154 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
155 #define PCI_HOST_FORCE 1 /* configure as pci host */
156 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
157
158 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
159 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
160 /* resource configuration */
161 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
162 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
163 #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
164 #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
165 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
166 #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
167 #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
168 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
169
170 /*-----------------------------------------------------------------------
171 * Start addresses for the final memory configuration
172 * (Set up by the startup code)
173 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
174 */
175 #define CONFIG_SYS_SDRAM_BASE 0x00000000
176 #define CONFIG_SYS_FLASH_BASE 0xFFF80000
177 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
178 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
179 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
180
181 /*
182 * For booting Linux, the board info and command line data
183 * have to be in the first 8 MB of memory, since this is
184 * the maximum mapped by the Linux kernel during initialization.
185 */
186 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
187 /*-----------------------------------------------------------------------
188 * FLASH organization
189 */
190 #define CONFIG_SYS_UPDATE_FLASH_SIZE
191 #define CONFIG_SYS_FLASH_PROTECTION
192 #define CONFIG_SYS_FLASH_EMPTY_INFO
193
194 #define CONFIG_SYS_FLASH_CFI
195 #define CONFIG_FLASH_CFI_DRIVER
196
197 #define CONFIG_FLASH_SHOW_PROGRESS 45
198
199 #define CONFIG_SYS_MAX_FLASH_BANKS 1
200 #define CONFIG_SYS_MAX_FLASH_SECT 256
201
202 /*
203 * JFFS2 partitions
204 *
205 */
206 /* No command line, one static partition, whole device */
207 #undef CONFIG_CMD_MTDPARTS
208 #define CONFIG_JFFS2_DEV "nor0"
209 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
210 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
211
212 /* mtdparts command line support */
213 /* Note: fake mtd_id used, no linux mtd map file */
214 /*
215 #define CONFIG_CMD_MTDPARTS
216 #define MTDIDS_DEFAULT "nor0=mip405-0"
217 #define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)"
218 */
219
220 /*-----------------------------------------------------------------------
221 * Logbuffer Configuration
222 */
223 #undef CONFIG_LOGBUFFER /* supported but not enabled */
224 /*-----------------------------------------------------------------------
225 * Bootcountlimit Configuration
226 */
227 #undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */
228
229 /*-----------------------------------------------------------------------
230 * POST Configuration
231 */
232 #if 0 /* enable this if POST is desired (is supported but not enabled) */
233 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
234 CONFIG_SYS_POST_CPU | \
235 CONFIG_SYS_POST_RTC | \
236 CONFIG_SYS_POST_I2C)
237
238 #endif
239 /*
240 * Init Memory Controller:
241 */
242 #define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
243 #define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
244 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
245 #define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
246
247 #define CONFIG_BOARD_EARLY_INIT_R
248
249 /* Peripheral Bus Mapping */
250 #define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
251 #define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
252 #define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
253
254 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
255 #define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
256
257 /*-----------------------------------------------------------------------
258 * Definitions for initial stack pointer and data area (in On Chip SRAM)
259 */
260 #define CONFIG_SYS_TEMP_STACK_OCM 1
261 #define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
262 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
263 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
264 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
265 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
266 /* reserve some memory for POST and BOOT limit info */
267 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
268
269 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
270 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
271 #endif
272
273 /***********************************************************************
274 * External peripheral base address
275 ***********************************************************************/
276 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
277
278 /***********************************************************************
279 * Last Stage Init
280 ***********************************************************************/
281 #define CONFIG_LAST_STAGE_INIT
282 /************************************************************
283 * Ethernet Stuff
284 ***********************************************************/
285 #define CONFIG_PPC4xx_EMAC
286 #define CONFIG_MII 1 /* MII PHY management */
287 #define CONFIG_PHY_ADDR 1 /* PHY address */
288 #define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
289 #define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */
290 /************************************************************
291 * RTC
292 ***********************************************************/
293 #define CONFIG_RTC_MC146818
294 #undef CONFIG_WATCHDOG /* watchdog disabled */
295
296 /************************************************************
297 * IDE/ATA stuff
298 ************************************************************/
299 #if defined(CONFIG_TARGET_MIP405T)
300 #define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
301 #else
302 #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
303 #endif
304
305 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
306
307 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
308 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
309 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
310 #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
311 #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
312 #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
313
314 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
315 #undef CONFIG_IDE_LED /* no led for ide supported */
316 #define CONFIG_IDE_RESET /* reset for ide supported... */
317 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
318 #define CONFIG_SUPPORT_VFAT
319 /************************************************************
320 * ATAPI support (experimental)
321 ************************************************************/
322 #define CONFIG_ATAPI /* enable ATAPI Support */
323
324 /************************************************************
325 * DISK Partition support
326 ************************************************************/
327
328 /************************************************************
329 * Video support
330 ************************************************************/
331 #define CONFIG_VIDEO_LOGO
332 #undef CONFIG_VIDEO_ONBOARD
333 /************************************************************
334 * USB support EXPERIMENTAL
335 ************************************************************/
336 #if !defined(CONFIG_TARGET_MIP405T)
337 #define CONFIG_USB_UHCI
338
339 /* Enable needed helper functions */
340 #endif
341 /************************************************************
342 * Debug support
343 ************************************************************/
344 #if defined(CONFIG_CMD_KGDB)
345 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
346 #endif
347
348 /************************************************************
349 * support BZIP2 compression
350 ************************************************************/
351 #define CONFIG_BZIP2 1
352
353 #endif /* __CONFIG_H */