include/configs/MIP405.h

   1 /*
   2  * (C) Copyright 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /***********************************************************
  16  * High Level Configuration Options
  17  * (easy to change)
  18  ***********************************************************/
  19 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  20 #define CONFIG_MIP405           1       /* ...on a MIP405 board         */
  21
  22 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  23
  24 /***********************************************************
  25  * Note that it may also be a MIP405T board which is a subset of the
  26  * MIP405
  27  ***********************************************************/
  28 /***********************************************************
  29  * WARNING:
  30  * CONFIG_BOOT_PCI is only used for first boot-up and should
  31  * NOT be enabled for production bootloader
  32  ***********************************************************/
  33 /*#define        CONFIG_BOOT_PCI         1*/
  34 /***********************************************************
  35  * Clock
  36  ***********************************************************/
  37 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  38
  39 /*
  40  * BOOTP options
  41  */
  42 #define CONFIG_BOOTP_BOOTFILESIZE
  43 #define CONFIG_BOOTP_BOOTPATH
  44 #define CONFIG_BOOTP_GATEWAY
  45 #define CONFIG_BOOTP_HOSTNAME
  46
  47 /*
  48  * Command line configuration.
  49  */
  50 #define CONFIG_CMD_DATE
  51 #define CONFIG_CMD_EEPROM
  52 #define CONFIG_CMD_IDE
  53 #define CONFIG_CMD_IRQ
  54 #define CONFIG_CMD_JFFS2
  55 #define CONFIG_CMD_PCI
  56 #define CONFIG_CMD_REGINFO
  57 #define CONFIG_CMD_SAVES
  58 #define CONFIG_CMD_BSP
  59
  60 #if !defined(CONFIG_MIP405T)
  61 #endif
  62
  63 /**************************************************************
  64  * I2C Stuff:
  65  * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
  66  * 0x53.
  67  * The Atmel EEPROM uses 16Bit addressing.
  68  ***************************************************************/
  69
  70 #define CONFIG_SYS_I2C
  71 #define CONFIG_SYS_I2C_PPC4XX
  72 #define CONFIG_SYS_I2C_PPC4XX_CH0
  73 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           50000
  74 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
  75
  76 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x53    /* EEPROM 24C128/256            */
  77 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* Bytes of address             */
  78 /* mask of address bits that overflow into the "EEPROM chip address"    */
  79 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  80 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6     /* The Atmel 24C128/256 has     */
  81                                         /* 64 byte page write mode using*/
  82                                         /* last 6 bits of the address   */
  83 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
  84
  85 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
  86 #define CONFIG_ENV_OFFSET               0x00000 /* environment starts at the beginning of the EEPROM */
  87 #define CONFIG_ENV_SIZE         0x00800 /* 2k bytes may be used for env vars */
  88
  89 /***************************************************************
  90  * Definitions for Serial Presence Detect EEPROM address
  91  * (to get SDRAM settings)
  92  ***************************************************************/
  93 /*#define SDRAM_EEPROM_WRITE_ADDRESS    0xA0
  94 #define SDRAM_EEPROM_READ_ADDRESS       0xA1
  95 */
  96 /**************************************************************
  97  * Environment definitions
  98  **************************************************************/
  99 #define CONFIG_BAUDRATE         9600    /* STD Baudrate */
 100 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 101 /* #define CONFIG_BOOT_RETRY_TIME       -10     /XXX* feature is available but not enabled */
 102
 103 #define CONFIG_BOOTCOMMAND      "diskboot 400000 0:1; bootm" /* autoboot command                */
 104 #define CONFIG_BOOTARGS         "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
 105
 106 #define CONFIG_IPADDR           10.0.0.100
 107 #define CONFIG_SERVERIP         10.0.0.1
 108 #define CONFIG_PREBOOT
 109 /***************************************************************
 110  * defines if the console is stored in the environment
 111  ***************************************************************/
 112 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* stdin, stdout and stderr are in evironment */
 113 /***************************************************************
 114  * defines if an overwrite_console function exists
 115  *************************************************************/
 116 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 117 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 118 /***************************************************************
 119  * defines if the overwrite_console should be stored in the
 120  * environment
 121  **************************************************************/
 122 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 123
 124 /**************************************************************
 125  * loads config
 126  *************************************************************/
 127 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 128 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 129
 130 #define CONFIG_MISC_INIT_R
 131 /***********************************************************
 132  * Miscellaneous configurable options
 133  **********************************************************/
 134 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 135 #if defined(CONFIG_CMD_KGDB)
 136 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 137 #else
 138 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 139 #endif
 140 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 141 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 142 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 143
 144 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 145 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 1 ... 12 MB in DRAM  */
 146
 147 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 148 #define CONFIG_SYS_NS16550_SERIAL
 149 #define CONFIG_SYS_NS16550_REG_SIZE     1
 150 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 151
 152 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 153 #define CONFIG_SYS_BASE_BAUD       916667
 154
 155 /* The following table includes the supported baudrates */
 156 #define CONFIG_SYS_BAUDRATE_TABLE       \
 157         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 158          57600, 115200, 230400, 460800, 921600 }
 159
 160 #define CONFIG_SYS_LOAD_ADDR    0x400000        /* default load address */
 161 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 162
 163 /*-----------------------------------------------------------------------
 164  * PCI stuff
 165  *-----------------------------------------------------------------------
 166  */
 167 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 168 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 169 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 170
 171 #define CONFIG_PCI                      /* include pci support          */
 172 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 173 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* configure as pci-host        */
 174 #define CONFIG_PCI_PNP                  /* pci plug-and-play            */
 175                                         /* resource configuration       */
 176 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000   /* PCI Vendor ID: to-do!!!      */
 177 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000   /* PCI Device ID: to-do!!!      */
 178 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 179 #define CONFIG_SYS_PCI_PTM1MS   0x80000001      /* 2GB, enable hard-wired to 1  */
 180 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 181 #define CONFIG_SYS_PCI_PTM2LA   0x00000000      /* disabled                     */
 182 #define CONFIG_SYS_PCI_PTM2MS   0x00000000      /* disabled                     */
 183 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 184
 185 /*-----------------------------------------------------------------------
 186  * Start addresses for the final memory configuration
 187  * (Set up by the startup code)
 188  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 189  */
 190 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 191 #define CONFIG_SYS_FLASH_BASE           0xFFF80000
 192 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 193 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Monitor   */
 194 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserve 1024 kB for malloc() */
 195
 196 /*
 197  * For booting Linux, the board info and command line data
 198  * have to be in the first 8 MB of memory, since this is
 199  * the maximum mapped by the Linux kernel during initialization.
 200  */
 201 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 202 /*-----------------------------------------------------------------------
 203  * FLASH organization
 204  */
 205 #define CONFIG_SYS_UPDATE_FLASH_SIZE
 206 #define CONFIG_SYS_FLASH_PROTECTION
 207 #define CONFIG_SYS_FLASH_EMPTY_INFO
 208
 209 #define CONFIG_SYS_FLASH_CFI
 210 #define CONFIG_FLASH_CFI_DRIVER
 211
 212 #define CONFIG_FLASH_SHOW_PROGRESS      45
 213
 214 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 215 #define CONFIG_SYS_MAX_FLASH_SECT       256
 216
 217 /*
 218  * JFFS2 partitions
 219  *
 220  */
 221 /* No command line, one static partition, whole device */
 222 #undef CONFIG_CMD_MTDPARTS
 223 #define CONFIG_JFFS2_DEV                "nor0"
 224 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 225 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 226
 227 /* mtdparts command line support */
 228 /* Note: fake mtd_id used, no linux mtd map file */
 229 /*
 230 #define CONFIG_CMD_MTDPARTS
 231 #define MTDIDS_DEFAULT          "nor0=mip405-0"
 232 #define MTDPARTS_DEFAULT        "mtdparts=mip405-0:-(jffs2)"
 233 */
 234
 235 /*-----------------------------------------------------------------------
 236  * Logbuffer Configuration
 237  */
 238 #undef CONFIG_LOGBUFFER         /* supported but not enabled */
 239 /*-----------------------------------------------------------------------
 240  * Bootcountlimit Configuration
 241  */
 242 #undef CONFIG_BOOTCOUNT_LIMIT   /* supported but not enabled */
 243
 244 /*-----------------------------------------------------------------------
 245  * POST Configuration
 246  */
 247 #if 0 /* enable this if POST is desired (is supported but not enabled) */
 248 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY | \
 249                                  CONFIG_SYS_POST_CPU            | \
 250                                  CONFIG_SYS_POST_RTC            | \
 251                                  CONFIG_SYS_POST_I2C)
 252
 253 #endif
 254 /*
 255  * Init Memory Controller:
 256  */
 257 #define FLASH_MAX_SIZE          0x00800000              /* 8MByte max */
 258 #define FLASH_BASE_PRELIM       0xFF800000  /* open the flash CS */
 259 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 260 #define FLASH_SIZE_PRELIM        3  /* maximal flash FLASH size bank #0 */
 261
 262 #define CONFIG_BOARD_EARLY_INIT_F 1
 263 #define CONFIG_BOARD_EARLY_INIT_R
 264
 265 /* Peripheral Bus Mapping */
 266 #define PER_PLD_ADDR            0xF4000000 /* smallest window is 1MByte 0x10 0000*/
 267 #define PER_UART0_ADDR          0xF4100000 /* smallest window is 1MByte 0x10 0000*/
 268 #define PER_UART1_ADDR          0xF4200000 /* smallest window is 1MByte 0x10 0000*/
 269
 270 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
 271 #define CONFIG_PORT_ADDR        PER_PLD_ADDR + 5
 272
 273 /*-----------------------------------------------------------------------
 274  * Definitions for initial stack pointer and data area (in On Chip SRAM)
 275  */
 276 #define CONFIG_SYS_TEMP_STACK_OCM      1
 277 #define CONFIG_SYS_OCM_DATA_ADDR        0xF0000000
 278 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 279 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR        /* inside of On Chip SRAM    */
 280 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE        /* Size of On Chip SRAM        */
 281 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 282 /* reserve some memory for POST and BOOT limit info */
 283 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 32)
 284
 285 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
 286 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
 287 #endif
 288
 289 /***********************************************************************
 290  * External peripheral base address
 291  ***********************************************************************/
 292 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
 293
 294 /***********************************************************************
 295  * Last Stage Init
 296  ***********************************************************************/
 297 #define CONFIG_LAST_STAGE_INIT
 298 /************************************************************
 299  * Ethernet Stuff
 300  ***********************************************************/
 301 #define CONFIG_PPC4xx_EMAC
 302 #define CONFIG_MII              1       /* MII PHY management           */
 303 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 304 #define CONFIG_PHY_RESET_DELAY  300     /* Intel LXT971A needs this */
 305 #define CONFIG_PHY_CMD_DELAY    40      /* Intel LXT971A needs this */
 306 /************************************************************
 307  * RTC
 308  ***********************************************************/
 309 #define CONFIG_RTC_MC146818
 310 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 311
 312 /************************************************************
 313  * IDE/ATA stuff
 314  ************************************************************/
 315 #if defined(CONFIG_MIP405T)
 316 #define CONFIG_SYS_IDE_MAXBUS           1   /* MIP405T has only one IDE bus     */
 317 #else
 318 #define CONFIG_SYS_IDE_MAXBUS           2   /* max. 2 IDE busses        */
 319 #endif
 320
 321 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 322
 323 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
 324 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x01F0          /* ide0 offste */
 325 #define CONFIG_SYS_ATA_IDE1_OFFSET      0x0170          /* ide1 offset */
 326 #define CONFIG_SYS_ATA_DATA_OFFSET      0               /* data reg offset      */
 327 #define CONFIG_SYS_ATA_REG_OFFSET       0               /* reg offset */
 328 #define CONFIG_SYS_ATA_ALT_OFFSET       0x200           /* alternate register offset */
 329
 330 #undef  CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
 331 #undef  CONFIG_IDE_LED         /* no led for ide supported     */
 332 #define CONFIG_IDE_RESET       /* reset for ide supported...    */
 333 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
 334 #define CONFIG_SUPPORT_VFAT
 335 /************************************************************
 336  * ATAPI support (experimental)
 337  ************************************************************/
 338 #define CONFIG_ATAPI                    /* enable ATAPI Support */
 339
 340 /************************************************************
 341  * DISK Partition support
 342  ************************************************************/
 343 #define CONFIG_DOS_PARTITION
 344 #define CONFIG_MAC_PARTITION
 345 #define CONFIG_ISO_PARTITION /* Experimental */
 346
 347 /************************************************************
 348  * Video support
 349  ************************************************************/
 350 #define CONFIG_VIDEO                    /*To enable video controller support */
 351 #define CONFIG_VIDEO_CT69000
 352 #define CONFIG_CFB_CONSOLE
 353 #define CONFIG_VIDEO_LOGO
 354 #define CONFIG_CONSOLE_EXTRA_INFO
 355 #define CONFIG_VGA_AS_SINGLE_DEVICE
 356 #define CONFIG_VIDEO_SW_CURSOR
 357 #undef CONFIG_VIDEO_ONBOARD
 358 /************************************************************
 359  * USB support EXPERIMENTAL
 360  ************************************************************/
 361 #if !defined(CONFIG_MIP405T)
 362 #define CONFIG_USB_UHCI
 363 #define CONFIG_USB_KEYBOARD
 364
 365 /* Enable needed helper functions */
 366 #define CONFIG_SYS_STDIO_DEREGISTER             /* needs stdio_deregister */
 367 #endif
 368 /************************************************************
 369  * Debug support
 370  ************************************************************/
 371 #if defined(CONFIG_CMD_KGDB)
 372 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 373 #endif
 374
 375 /************************************************************
 376  * support BZIP2 compression
 377  ************************************************************/
 378 #define CONFIG_BZIP2            1
 379
 380 /************************************************************
 381  * Ident
 382  ************************************************************/
 383
 384 #define VERSION_TAG "released"
 385 #if !defined(CONFIG_MIP405T)
 386 #define CONFIG_ISO_STRING "MEV-10072-001"
 387 #else
 388 #define CONFIG_ISO_STRING "MEV-10082-001"
 389 #endif
 390
 391 #endif  /* __CONFIG_H */