include/configs/MIP405.h

   1 /*
   2  * (C) Copyright 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /***********************************************************
  16  * High Level Configuration Options
  17  * (easy to change)
  18  ***********************************************************/
  19 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  20 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  21 #define CONFIG_MIP405           1       /* ...on a MIP405 board         */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  24
  25 /***********************************************************
  26  * Note that it may also be a MIP405T board which is a subset of the
  27  * MIP405
  28  ***********************************************************/
  29 /***********************************************************
  30  * WARNING:
  31  * CONFIG_BOOT_PCI is only used for first boot-up and should
  32  * NOT be enabled for production bootloader
  33  ***********************************************************/
  34 /*#define        CONFIG_BOOT_PCI         1*/
  35 /***********************************************************
  36  * Clock
  37  ***********************************************************/
  38 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  39
  40
  41 /*
  42  * BOOTP options
  43  */
  44 #define CONFIG_BOOTP_BOOTFILESIZE
  45 #define CONFIG_BOOTP_BOOTPATH
  46 #define CONFIG_BOOTP_GATEWAY
  47 #define CONFIG_BOOTP_HOSTNAME
  48
  49
  50 /*
  51  * Command line configuration.
  52  */
  53 #include <config_cmd_default.h>
  54
  55 #define CONFIG_CMD_CACHE
  56 #define CONFIG_CMD_DATE
  57 #define CONFIG_CMD_DHCP
  58 #define CONFIG_CMD_EEPROM
  59 #define CONFIG_CMD_ELF
  60 #define CONFIG_CMD_FAT
  61 #define CONFIG_CMD_I2C
  62 #define CONFIG_CMD_IDE
  63 #define CONFIG_CMD_IRQ
  64 #define CONFIG_CMD_JFFS2
  65 #define CONFIG_CMD_MII
  66 #define CONFIG_CMD_PCI
  67 #define CONFIG_CMD_PING
  68 #define CONFIG_CMD_REGINFO
  69 #define CONFIG_CMD_SAVES
  70 #define CONFIG_CMD_BSP
  71
  72 #if !defined(CONFIG_MIP405T)
  73     #define CONFIG_CMD_USB
  74 #endif
  75
  76
  77 #define  CONFIG_SYS_HUSH_PARSER
  78 /**************************************************************
  79  * I2C Stuff:
  80  * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
  81  * 0x53.
  82  * The Atmel EEPROM uses 16Bit addressing.
  83  ***************************************************************/
  84
  85 #define CONFIG_SYS_I2C
  86 #define CONFIG_SYS_I2C_PPC4XX
  87 #define CONFIG_SYS_I2C_PPC4XX_CH0
  88 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           50000
  89 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
  90
  91 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x53    /* EEPROM 24C128/256            */
  92 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* Bytes of address             */
  93 /* mask of address bits that overflow into the "EEPROM chip address"    */
  94 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  95 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6     /* The Atmel 24C128/256 has     */
  96                                         /* 64 byte page write mode using*/
  97                                         /* last 6 bits of the address   */
  98 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
  99
 100
 101 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 102 #define CONFIG_ENV_OFFSET               0x00000 /* environment starts at the beginning of the EEPROM */
 103 #define CONFIG_ENV_SIZE         0x00800 /* 2k bytes may be used for env vars */
 104
 105 /***************************************************************
 106  * Definitions for Serial Presence Detect EEPROM address
 107  * (to get SDRAM settings)
 108  ***************************************************************/
 109 /*#define SDRAM_EEPROM_WRITE_ADDRESS    0xA0
 110 #define SDRAM_EEPROM_READ_ADDRESS       0xA1
 111 */
 112 /**************************************************************
 113  * Environment definitions
 114  **************************************************************/
 115 #define CONFIG_BAUDRATE         9600    /* STD Baudrate */
 116 #define CONFIG_BOOTDELAY        5
 117 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 118 /* #define CONFIG_BOOT_RETRY_TIME       -10     /XXX* feature is available but not enabled */
 119 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check console even if bootdelay = 0 */
 120
 121 #define CONFIG_BOOTCOMMAND      "diskboot 400000 0:1; bootm" /* autoboot command                */
 122 #define CONFIG_BOOTARGS         "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
 123
 124 #define CONFIG_IPADDR           10.0.0.100
 125 #define CONFIG_SERVERIP         10.0.0.1
 126 #define CONFIG_PREBOOT
 127 /***************************************************************
 128  * defines if the console is stored in the environment
 129  ***************************************************************/
 130 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* stdin, stdout and stderr are in evironment */
 131 /***************************************************************
 132  * defines if an overwrite_console function exists
 133  *************************************************************/
 134 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 135 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 136 /***************************************************************
 137  * defines if the overwrite_console should be stored in the
 138  * environment
 139  **************************************************************/
 140 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 141
 142 /**************************************************************
 143  * loads config
 144  *************************************************************/
 145 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 146 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 147
 148 #define CONFIG_MISC_INIT_R
 149 /***********************************************************
 150  * Miscellaneous configurable options
 151  **********************************************************/
 152 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 153 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 154 #if defined(CONFIG_CMD_KGDB)
 155 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 156 #else
 157 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 158 #endif
 159 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 160 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 161 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 162
 163 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 164 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 1 ... 12 MB in DRAM  */
 165
 166 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 167 #define CONFIG_SYS_NS16550
 168 #define CONFIG_SYS_NS16550_SERIAL
 169 #define CONFIG_SYS_NS16550_REG_SIZE     1
 170 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 171
 172 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 173 #define CONFIG_SYS_BASE_BAUD       916667
 174
 175 /* The following table includes the supported baudrates */
 176 #define CONFIG_SYS_BAUDRATE_TABLE       \
 177         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 178          57600, 115200, 230400, 460800, 921600 }
 179
 180 #define CONFIG_SYS_LOAD_ADDR    0x400000        /* default load address */
 181 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 182
 183 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 184
 185 /*-----------------------------------------------------------------------
 186  * PCI stuff
 187  *-----------------------------------------------------------------------
 188  */
 189 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 190 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 191 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 192
 193 #define CONFIG_PCI                      /* include pci support          */
 194 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 195 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* configure as pci-host        */
 196 #define CONFIG_PCI_PNP                  /* pci plug-and-play            */
 197                                         /* resource configuration       */
 198 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000   /* PCI Vendor ID: to-do!!!      */
 199 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000   /* PCI Device ID: to-do!!!      */
 200 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 201 #define CONFIG_SYS_PCI_PTM1MS   0x80000001      /* 2GB, enable hard-wired to 1  */
 202 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 203 #define CONFIG_SYS_PCI_PTM2LA   0x00000000      /* disabled                     */
 204 #define CONFIG_SYS_PCI_PTM2MS   0x00000000      /* disabled                     */
 205 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 206
 207 /*-----------------------------------------------------------------------
 208  * Start addresses for the final memory configuration
 209  * (Set up by the startup code)
 210  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 211  */
 212 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 213 #define CONFIG_SYS_FLASH_BASE           0xFFF80000
 214 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 215 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Monitor   */
 216 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserve 1024 kB for malloc() */
 217
 218 /*
 219  * For booting Linux, the board info and command line data
 220  * have to be in the first 8 MB of memory, since this is
 221  * the maximum mapped by the Linux kernel during initialization.
 222  */
 223 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 224 /*-----------------------------------------------------------------------
 225  * FLASH organization
 226  */
 227 #define CONFIG_SYS_UPDATE_FLASH_SIZE
 228 #define CONFIG_SYS_FLASH_PROTECTION
 229 #define CONFIG_SYS_FLASH_EMPTY_INFO
 230
 231 #define CONFIG_SYS_FLASH_CFI
 232 #define CONFIG_FLASH_CFI_DRIVER
 233
 234 #define CONFIG_FLASH_SHOW_PROGRESS      45
 235
 236 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 237 #define CONFIG_SYS_MAX_FLASH_SECT       256
 238
 239 /*
 240  * JFFS2 partitions
 241  *
 242  */
 243 /* No command line, one static partition, whole device */
 244 #undef CONFIG_CMD_MTDPARTS
 245 #define CONFIG_JFFS2_DEV                "nor0"
 246 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 247 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 248
 249 /* mtdparts command line support */
 250 /* Note: fake mtd_id used, no linux mtd map file */
 251 /*
 252 #define CONFIG_CMD_MTDPARTS
 253 #define MTDIDS_DEFAULT          "nor0=mip405-0"
 254 #define MTDPARTS_DEFAULT        "mtdparts=mip405-0:-(jffs2)"
 255 */
 256
 257 /*-----------------------------------------------------------------------
 258  * Logbuffer Configuration
 259  */
 260 #undef CONFIG_LOGBUFFER         /* supported but not enabled */
 261 /*-----------------------------------------------------------------------
 262  * Bootcountlimit Configuration
 263  */
 264 #undef CONFIG_BOOTCOUNT_LIMIT   /* supported but not enabled */
 265
 266 /*-----------------------------------------------------------------------
 267  * POST Configuration
 268  */
 269 #if 0 /* enable this if POST is desired (is supported but not enabled) */
 270 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY | \
 271                                  CONFIG_SYS_POST_CPU            | \
 272                                  CONFIG_SYS_POST_RTC            | \
 273                                  CONFIG_SYS_POST_I2C)
 274
 275 #endif
 276 /*
 277  * Init Memory Controller:
 278  */
 279 #define FLASH_MAX_SIZE          0x00800000              /* 8MByte max */
 280 #define FLASH_BASE_PRELIM       0xFF800000  /* open the flash CS */
 281 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 282 #define FLASH_SIZE_PRELIM        3  /* maximal flash FLASH size bank #0 */
 283
 284 #define CONFIG_BOARD_EARLY_INIT_F 1
 285 #define CONFIG_BOARD_EARLY_INIT_R
 286
 287 /* Peripheral Bus Mapping */
 288 #define PER_PLD_ADDR            0xF4000000 /* smallest window is 1MByte 0x10 0000*/
 289 #define PER_UART0_ADDR          0xF4100000 /* smallest window is 1MByte 0x10 0000*/
 290 #define PER_UART1_ADDR          0xF4200000 /* smallest window is 1MByte 0x10 0000*/
 291
 292 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
 293 #define CONFIG_PORT_ADDR        PER_PLD_ADDR + 5
 294
 295
 296 /*-----------------------------------------------------------------------
 297  * Definitions for initial stack pointer and data area (in On Chip SRAM)
 298  */
 299 #define CONFIG_SYS_TEMP_STACK_OCM      1
 300 #define CONFIG_SYS_OCM_DATA_ADDR        0xF0000000
 301 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 302 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR        /* inside of On Chip SRAM    */
 303 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE        /* Size of On Chip SRAM        */
 304 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 305 /* reserve some memory for POST and BOOT limit info */
 306 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 32)
 307
 308 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
 309 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
 310 #endif
 311
 312 /***********************************************************************
 313  * External peripheral base address
 314  ***********************************************************************/
 315 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
 316
 317 /***********************************************************************
 318  * Last Stage Init
 319  ***********************************************************************/
 320 #define CONFIG_LAST_STAGE_INIT
 321 /************************************************************
 322  * Ethernet Stuff
 323  ***********************************************************/
 324 #define CONFIG_PPC4xx_EMAC
 325 #define CONFIG_MII              1       /* MII PHY management           */
 326 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 327 #define CONFIG_PHY_RESET_DELAY  300     /* Intel LXT971A needs this */
 328 #define CONFIG_PHY_CMD_DELAY    40      /* Intel LXT971A needs this */
 329 /************************************************************
 330  * RTC
 331  ***********************************************************/
 332 #define CONFIG_RTC_MC146818
 333 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 334
 335 /************************************************************
 336  * IDE/ATA stuff
 337  ************************************************************/
 338 #if defined(CONFIG_MIP405T)
 339 #define CONFIG_SYS_IDE_MAXBUS           1   /* MIP405T has only one IDE bus     */
 340 #else
 341 #define CONFIG_SYS_IDE_MAXBUS           2   /* max. 2 IDE busses        */
 342 #endif
 343
 344 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 345
 346 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
 347 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x01F0          /* ide0 offste */
 348 #define CONFIG_SYS_ATA_IDE1_OFFSET      0x0170          /* ide1 offset */
 349 #define CONFIG_SYS_ATA_DATA_OFFSET      0               /* data reg offset      */
 350 #define CONFIG_SYS_ATA_REG_OFFSET       0               /* reg offset */
 351 #define CONFIG_SYS_ATA_ALT_OFFSET       0x200           /* alternate register offset */
 352
 353 #undef  CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
 354 #undef  CONFIG_IDE_LED         /* no led for ide supported     */
 355 #define CONFIG_IDE_RESET       /* reset for ide supported...    */
 356 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
 357 #define CONFIG_SUPPORT_VFAT
 358 /************************************************************
 359  * ATAPI support (experimental)
 360  ************************************************************/
 361 #define CONFIG_ATAPI                    /* enable ATAPI Support */
 362
 363 /************************************************************
 364  * DISK Partition support
 365  ************************************************************/
 366 #define CONFIG_DOS_PARTITION
 367 #define CONFIG_MAC_PARTITION
 368 #define CONFIG_ISO_PARTITION /* Experimental */
 369
 370 /************************************************************
 371  * Keyboard support
 372  ************************************************************/
 373 #undef CONFIG_ISA_KEYBOARD
 374
 375 /************************************************************
 376  * Video support
 377  ************************************************************/
 378 #define CONFIG_VIDEO                    /*To enable video controller support */
 379 #define CONFIG_VIDEO_CT69000
 380 #define CONFIG_CFB_CONSOLE
 381 #define CONFIG_VIDEO_LOGO
 382 #define CONFIG_CONSOLE_EXTRA_INFO
 383 #define CONFIG_VGA_AS_SINGLE_DEVICE
 384 #define CONFIG_VIDEO_SW_CURSOR
 385 #undef CONFIG_VIDEO_ONBOARD
 386 /************************************************************
 387  * USB support EXPERIMENTAL
 388  ************************************************************/
 389 #if !defined(CONFIG_MIP405T)
 390 #define CONFIG_USB_UHCI
 391 #define CONFIG_USB_KEYBOARD
 392 #define CONFIG_USB_STORAGE
 393
 394 /* Enable needed helper functions */
 395 #define CONFIG_SYS_STDIO_DEREGISTER             /* needs stdio_deregister */
 396 #endif
 397 /************************************************************
 398  * Debug support
 399  ************************************************************/
 400 #if defined(CONFIG_CMD_KGDB)
 401 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 402 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 403 #endif
 404
 405 /************************************************************
 406  * support BZIP2 compression
 407  ************************************************************/
 408 #define CONFIG_BZIP2            1
 409
 410 /************************************************************
 411  * Ident
 412  ************************************************************/
 413
 414 #define VERSION_TAG "released"
 415 #if !defined(CONFIG_MIP405T)
 416 #define CONFIG_ISO_STRING "MEV-10072-001"
 417 #else
 418 #define CONFIG_ISO_STRING "MEV-10082-001"
 419 #endif
 420
 421 #if !defined(CONFIG_BOOT_PCI)
 422 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
 423 #else
 424 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
 425 #endif
 426
 427
 428 #endif  /* __CONFIG_H */