include/configs/MIP405.h

   1 /*
   2  * (C) Copyright 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /***********************************************************
  16  * High Level Configuration Options
  17  * (easy to change)
  18  ***********************************************************/
  19 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  20
  21 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  22
  23 /***********************************************************
  24  * Note that it may also be a MIP405T board which is a subset of the
  25  * MIP405
  26  ***********************************************************/
  27 /***********************************************************
  28  * WARNING:
  29  * CONFIG_BOOT_PCI is only used for first boot-up and should
  30  * NOT be enabled for production bootloader
  31  ***********************************************************/
  32 /*#define        CONFIG_BOOT_PCI         1*/
  33 /***********************************************************
  34  * Clock
  35  ***********************************************************/
  36 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  37
  38 /*
  39  * BOOTP options
  40  */
  41 #define CONFIG_BOOTP_BOOTFILESIZE
  42 #define CONFIG_BOOTP_BOOTPATH
  43 #define CONFIG_BOOTP_GATEWAY
  44 #define CONFIG_BOOTP_HOSTNAME
  45
  46 /*
  47  * Command line configuration.
  48  */
  49 #define CONFIG_CMD_EEPROM
  50 #define CONFIG_CMD_IDE
  51 #define CONFIG_CMD_IRQ
  52 #define CONFIG_CMD_JFFS2
  53 #define CONFIG_CMD_PCI
  54 #define CONFIG_CMD_REGINFO
  55 #define CONFIG_CMD_SAVES
  56
  57 /**************************************************************
  58  * I2C Stuff:
  59  * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
  60  * 0x53.
  61  * The Atmel EEPROM uses 16Bit addressing.
  62  ***************************************************************/
  63
  64 #define CONFIG_SYS_I2C
  65 #define CONFIG_SYS_I2C_PPC4XX
  66 #define CONFIG_SYS_I2C_PPC4XX_CH0
  67 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           50000
  68 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
  69
  70 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x53    /* EEPROM 24C128/256            */
  71 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* Bytes of address             */
  72 /* mask of address bits that overflow into the "EEPROM chip address"    */
  73 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  74 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6     /* The Atmel 24C128/256 has     */
  75                                         /* 64 byte page write mode using*/
  76                                         /* last 6 bits of the address   */
  77 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
  78
  79 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
  80 #define CONFIG_ENV_OFFSET               0x00000 /* environment starts at the beginning of the EEPROM */
  81 #define CONFIG_ENV_SIZE         0x00800 /* 2k bytes may be used for env vars */
  82
  83 /***************************************************************
  84  * Definitions for Serial Presence Detect EEPROM address
  85  * (to get SDRAM settings)
  86  ***************************************************************/
  87 /*#define SDRAM_EEPROM_WRITE_ADDRESS    0xA0
  88 #define SDRAM_EEPROM_READ_ADDRESS       0xA1
  89 */
  90 /**************************************************************
  91  * Environment definitions
  92  **************************************************************/
  93 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
  94 /* #define CONFIG_BOOT_RETRY_TIME       -10     /XXX* feature is available but not enabled */
  95
  96 #define CONFIG_BOOTCOMMAND      "diskboot 400000 0:1; bootm" /* autoboot command                */
  97 #define CONFIG_BOOTARGS         "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
  98
  99 #define CONFIG_IPADDR           10.0.0.100
 100 #define CONFIG_SERVERIP         10.0.0.1
 101 #define CONFIG_PREBOOT
 102 /***************************************************************
 103  * defines if an overwrite_console function exists
 104  *************************************************************/
 105 /***************************************************************
 106  * defines if the overwrite_console should be stored in the
 107  * environment
 108  **************************************************************/
 109
 110 /**************************************************************
 111  * loads config
 112  *************************************************************/
 113 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 114 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 115
 116 #define CONFIG_MISC_INIT_R
 117 /***********************************************************
 118  * Miscellaneous configurable options
 119  **********************************************************/
 120 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 121 #if defined(CONFIG_CMD_KGDB)
 122 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 123 #else
 124 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 125 #endif
 126 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 127 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 128 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 129
 130 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 131 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 1 ... 12 MB in DRAM  */
 132
 133 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 134 #define CONFIG_SYS_NS16550_SERIAL
 135 #define CONFIG_SYS_NS16550_REG_SIZE     1
 136 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 137
 138 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 139 #define CONFIG_SYS_BASE_BAUD       916667
 140
 141 /* The following table includes the supported baudrates */
 142 #define CONFIG_SYS_BAUDRATE_TABLE       \
 143         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 144          57600, 115200, 230400, 460800, 921600 }
 145
 146 #define CONFIG_SYS_LOAD_ADDR    0x400000        /* default load address */
 147 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 148
 149 /*-----------------------------------------------------------------------
 150  * PCI stuff
 151  *-----------------------------------------------------------------------
 152  */
 153 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 154 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 155 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 156
 157 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 158 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* configure as pci-host        */
 159                                         /* resource configuration       */
 160 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000   /* PCI Vendor ID: to-do!!!      */
 161 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000   /* PCI Device ID: to-do!!!      */
 162 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 163 #define CONFIG_SYS_PCI_PTM1MS   0x80000001      /* 2GB, enable hard-wired to 1  */
 164 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 165 #define CONFIG_SYS_PCI_PTM2LA   0x00000000      /* disabled                     */
 166 #define CONFIG_SYS_PCI_PTM2MS   0x00000000      /* disabled                     */
 167 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 168
 169 /*-----------------------------------------------------------------------
 170  * Start addresses for the final memory configuration
 171  * (Set up by the startup code)
 172  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 173  */
 174 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 175 #define CONFIG_SYS_FLASH_BASE           0xFFF80000
 176 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 177 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Monitor   */
 178 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserve 1024 kB for malloc() */
 179
 180 /*
 181  * For booting Linux, the board info and command line data
 182  * have to be in the first 8 MB of memory, since this is
 183  * the maximum mapped by the Linux kernel during initialization.
 184  */
 185 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 186 /*-----------------------------------------------------------------------
 187  * FLASH organization
 188  */
 189 #define CONFIG_SYS_UPDATE_FLASH_SIZE
 190 #define CONFIG_SYS_FLASH_PROTECTION
 191 #define CONFIG_SYS_FLASH_EMPTY_INFO
 192
 193 #define CONFIG_SYS_FLASH_CFI
 194 #define CONFIG_FLASH_CFI_DRIVER
 195
 196 #define CONFIG_FLASH_SHOW_PROGRESS      45
 197
 198 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 199 #define CONFIG_SYS_MAX_FLASH_SECT       256
 200
 201 /*
 202  * JFFS2 partitions
 203  *
 204  */
 205 /* No command line, one static partition, whole device */
 206 #undef CONFIG_CMD_MTDPARTS
 207 #define CONFIG_JFFS2_DEV                "nor0"
 208 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 209 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 210
 211 /* mtdparts command line support */
 212 /* Note: fake mtd_id used, no linux mtd map file */
 213 /*
 214 #define CONFIG_CMD_MTDPARTS
 215 #define MTDIDS_DEFAULT          "nor0=mip405-0"
 216 #define MTDPARTS_DEFAULT        "mtdparts=mip405-0:-(jffs2)"
 217 */
 218
 219 /*-----------------------------------------------------------------------
 220  * Logbuffer Configuration
 221  */
 222 #undef CONFIG_LOGBUFFER         /* supported but not enabled */
 223 /*-----------------------------------------------------------------------
 224  * Bootcountlimit Configuration
 225  */
 226 #undef CONFIG_BOOTCOUNT_LIMIT   /* supported but not enabled */
 227
 228 /*-----------------------------------------------------------------------
 229  * POST Configuration
 230  */
 231 #if 0 /* enable this if POST is desired (is supported but not enabled) */
 232 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY | \
 233                                  CONFIG_SYS_POST_CPU            | \
 234                                  CONFIG_SYS_POST_RTC            | \
 235                                  CONFIG_SYS_POST_I2C)
 236
 237 #endif
 238 /*
 239  * Init Memory Controller:
 240  */
 241 #define FLASH_MAX_SIZE          0x00800000              /* 8MByte max */
 242 #define FLASH_BASE_PRELIM       0xFF800000  /* open the flash CS */
 243 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 244 #define FLASH_SIZE_PRELIM        3  /* maximal flash FLASH size bank #0 */
 245
 246 #define CONFIG_BOARD_EARLY_INIT_R
 247
 248 /* Peripheral Bus Mapping */
 249 #define PER_PLD_ADDR            0xF4000000 /* smallest window is 1MByte 0x10 0000*/
 250 #define PER_UART0_ADDR          0xF4100000 /* smallest window is 1MByte 0x10 0000*/
 251 #define PER_UART1_ADDR          0xF4200000 /* smallest window is 1MByte 0x10 0000*/
 252
 253 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
 254 #define CONFIG_PORT_ADDR        PER_PLD_ADDR + 5
 255
 256 /*-----------------------------------------------------------------------
 257  * Definitions for initial stack pointer and data area (in On Chip SRAM)
 258  */
 259 #define CONFIG_SYS_TEMP_STACK_OCM      1
 260 #define CONFIG_SYS_OCM_DATA_ADDR        0xF0000000
 261 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 262 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR        /* inside of On Chip SRAM    */
 263 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE        /* Size of On Chip SRAM        */
 264 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 265 /* reserve some memory for POST and BOOT limit info */
 266 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 32)
 267
 268 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
 269 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
 270 #endif
 271
 272 /***********************************************************************
 273  * External peripheral base address
 274  ***********************************************************************/
 275 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
 276
 277 /***********************************************************************
 278  * Last Stage Init
 279  ***********************************************************************/
 280 #define CONFIG_LAST_STAGE_INIT
 281 /************************************************************
 282  * Ethernet Stuff
 283  ***********************************************************/
 284 #define CONFIG_PPC4xx_EMAC
 285 #define CONFIG_MII              1       /* MII PHY management           */
 286 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 287 #define CONFIG_PHY_RESET_DELAY  300     /* Intel LXT971A needs this */
 288 #define CONFIG_PHY_CMD_DELAY    40      /* Intel LXT971A needs this */
 289 /************************************************************
 290  * RTC
 291  ***********************************************************/
 292 #define CONFIG_RTC_MC146818
 293 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 294
 295 /************************************************************
 296  * IDE/ATA stuff
 297  ************************************************************/
 298 #if defined(CONFIG_TARGET_MIP405T)
 299 #define CONFIG_SYS_IDE_MAXBUS           1   /* MIP405T has only one IDE bus     */
 300 #else
 301 #define CONFIG_SYS_IDE_MAXBUS           2   /* max. 2 IDE busses        */
 302 #endif
 303
 304 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 305
 306 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
 307 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x01F0          /* ide0 offste */
 308 #define CONFIG_SYS_ATA_IDE1_OFFSET      0x0170          /* ide1 offset */
 309 #define CONFIG_SYS_ATA_DATA_OFFSET      0               /* data reg offset      */
 310 #define CONFIG_SYS_ATA_REG_OFFSET       0               /* reg offset */
 311 #define CONFIG_SYS_ATA_ALT_OFFSET       0x200           /* alternate register offset */
 312
 313 #undef  CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
 314 #undef  CONFIG_IDE_LED         /* no led for ide supported     */
 315 #define CONFIG_IDE_RESET       /* reset for ide supported...    */
 316 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
 317 #define CONFIG_SUPPORT_VFAT
 318 /************************************************************
 319  * ATAPI support (experimental)
 320  ************************************************************/
 321 #define CONFIG_ATAPI                    /* enable ATAPI Support */
 322
 323 /************************************************************
 324  * DISK Partition support
 325  ************************************************************/
 326
 327 /************************************************************
 328  * Video support
 329  ************************************************************/
 330 #define CONFIG_VIDEO_LOGO
 331 #undef CONFIG_VIDEO_ONBOARD
 332 /************************************************************
 333  * USB support EXPERIMENTAL
 334  ************************************************************/
 335 #if !defined(CONFIG_TARGET_MIP405T)
 336 #define CONFIG_USB_UHCI
 337
 338 /* Enable needed helper functions */
 339 #endif
 340 /************************************************************
 341  * Debug support
 342  ************************************************************/
 343 #if defined(CONFIG_CMD_KGDB)
 344 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 345 #endif
 346
 347 /************************************************************
 348  * support BZIP2 compression
 349  ************************************************************/
 350 #define CONFIG_BZIP2            1
 351
 352 #endif  /* __CONFIG_H */