include/configs/MIP405.h

   1 /*
   2  * (C) Copyright 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /***********************************************************
  16  * High Level Configuration Options
  17  * (easy to change)
  18  ***********************************************************/
  19 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  20 #define CONFIG_MIP405           1       /* ...on a MIP405 board         */
  21
  22 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  23
  24 #define CONFIG_SYS_GENERIC_BOARD
  25
  26 /***********************************************************
  27  * Note that it may also be a MIP405T board which is a subset of the
  28  * MIP405
  29  ***********************************************************/
  30 /***********************************************************
  31  * WARNING:
  32  * CONFIG_BOOT_PCI is only used for first boot-up and should
  33  * NOT be enabled for production bootloader
  34  ***********************************************************/
  35 /*#define        CONFIG_BOOT_PCI         1*/
  36 /***********************************************************
  37  * Clock
  38  ***********************************************************/
  39 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  40
  41
  42 /*
  43  * BOOTP options
  44  */
  45 #define CONFIG_BOOTP_BOOTFILESIZE
  46 #define CONFIG_BOOTP_BOOTPATH
  47 #define CONFIG_BOOTP_GATEWAY
  48 #define CONFIG_BOOTP_HOSTNAME
  49
  50
  51 /*
  52  * Command line configuration.
  53  */
  54 #include <config_cmd_default.h>
  55
  56 #define CONFIG_CMD_CACHE
  57 #define CONFIG_CMD_DATE
  58 #define CONFIG_CMD_DHCP
  59 #define CONFIG_CMD_EEPROM
  60 #define CONFIG_CMD_ELF
  61 #define CONFIG_CMD_FAT
  62 #define CONFIG_CMD_I2C
  63 #define CONFIG_CMD_IDE
  64 #define CONFIG_CMD_IRQ
  65 #define CONFIG_CMD_JFFS2
  66 #define CONFIG_CMD_MII
  67 #define CONFIG_CMD_PCI
  68 #define CONFIG_CMD_PING
  69 #define CONFIG_CMD_REGINFO
  70 #define CONFIG_CMD_SAVES
  71 #define CONFIG_CMD_BSP
  72
  73 #if !defined(CONFIG_MIP405T)
  74     #define CONFIG_CMD_USB
  75 #endif
  76
  77
  78 #define  CONFIG_SYS_HUSH_PARSER
  79 /**************************************************************
  80  * I2C Stuff:
  81  * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
  82  * 0x53.
  83  * The Atmel EEPROM uses 16Bit addressing.
  84  ***************************************************************/
  85
  86 #define CONFIG_SYS_I2C
  87 #define CONFIG_SYS_I2C_PPC4XX
  88 #define CONFIG_SYS_I2C_PPC4XX_CH0
  89 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           50000
  90 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
  91
  92 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x53    /* EEPROM 24C128/256            */
  93 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* Bytes of address             */
  94 /* mask of address bits that overflow into the "EEPROM chip address"    */
  95 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  96 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6     /* The Atmel 24C128/256 has     */
  97                                         /* 64 byte page write mode using*/
  98                                         /* last 6 bits of the address   */
  99 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 100
 101
 102 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 103 #define CONFIG_ENV_OFFSET               0x00000 /* environment starts at the beginning of the EEPROM */
 104 #define CONFIG_ENV_SIZE         0x00800 /* 2k bytes may be used for env vars */
 105
 106 /***************************************************************
 107  * Definitions for Serial Presence Detect EEPROM address
 108  * (to get SDRAM settings)
 109  ***************************************************************/
 110 /*#define SDRAM_EEPROM_WRITE_ADDRESS    0xA0
 111 #define SDRAM_EEPROM_READ_ADDRESS       0xA1
 112 */
 113 /**************************************************************
 114  * Environment definitions
 115  **************************************************************/
 116 #define CONFIG_BAUDRATE         9600    /* STD Baudrate */
 117 #define CONFIG_BOOTDELAY        5
 118 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 119 /* #define CONFIG_BOOT_RETRY_TIME       -10     /XXX* feature is available but not enabled */
 120 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check console even if bootdelay = 0 */
 121
 122 #define CONFIG_BOOTCOMMAND      "diskboot 400000 0:1; bootm" /* autoboot command                */
 123 #define CONFIG_BOOTARGS         "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
 124
 125 #define CONFIG_IPADDR           10.0.0.100
 126 #define CONFIG_SERVERIP         10.0.0.1
 127 #define CONFIG_PREBOOT
 128 /***************************************************************
 129  * defines if the console is stored in the environment
 130  ***************************************************************/
 131 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* stdin, stdout and stderr are in evironment */
 132 /***************************************************************
 133  * defines if an overwrite_console function exists
 134  *************************************************************/
 135 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 136 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 137 /***************************************************************
 138  * defines if the overwrite_console should be stored in the
 139  * environment
 140  **************************************************************/
 141 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 142
 143 /**************************************************************
 144  * loads config
 145  *************************************************************/
 146 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 147 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 148
 149 #define CONFIG_MISC_INIT_R
 150 /***********************************************************
 151  * Miscellaneous configurable options
 152  **********************************************************/
 153 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 154 #if defined(CONFIG_CMD_KGDB)
 155 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 156 #else
 157 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 158 #endif
 159 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 160 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 161 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 162
 163 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 164 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 1 ... 12 MB in DRAM  */
 165
 166 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 167 #define CONFIG_SYS_NS16550
 168 #define CONFIG_SYS_NS16550_SERIAL
 169 #define CONFIG_SYS_NS16550_REG_SIZE     1
 170 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 171
 172 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 173 #define CONFIG_SYS_BASE_BAUD       916667
 174
 175 /* The following table includes the supported baudrates */
 176 #define CONFIG_SYS_BAUDRATE_TABLE       \
 177         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 178          57600, 115200, 230400, 460800, 921600 }
 179
 180 #define CONFIG_SYS_LOAD_ADDR    0x400000        /* default load address */
 181 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 182
 183 /*-----------------------------------------------------------------------
 184  * PCI stuff
 185  *-----------------------------------------------------------------------
 186  */
 187 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 188 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 189 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 190
 191 #define CONFIG_PCI                      /* include pci support          */
 192 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 193 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* configure as pci-host        */
 194 #define CONFIG_PCI_PNP                  /* pci plug-and-play            */
 195                                         /* resource configuration       */
 196 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000   /* PCI Vendor ID: to-do!!!      */
 197 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000   /* PCI Device ID: to-do!!!      */
 198 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 199 #define CONFIG_SYS_PCI_PTM1MS   0x80000001      /* 2GB, enable hard-wired to 1  */
 200 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 201 #define CONFIG_SYS_PCI_PTM2LA   0x00000000      /* disabled                     */
 202 #define CONFIG_SYS_PCI_PTM2MS   0x00000000      /* disabled                     */
 203 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 204
 205 /*-----------------------------------------------------------------------
 206  * Start addresses for the final memory configuration
 207  * (Set up by the startup code)
 208  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 209  */
 210 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 211 #define CONFIG_SYS_FLASH_BASE           0xFFF80000
 212 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 213 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Monitor   */
 214 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserve 1024 kB for malloc() */
 215
 216 /*
 217  * For booting Linux, the board info and command line data
 218  * have to be in the first 8 MB of memory, since this is
 219  * the maximum mapped by the Linux kernel during initialization.
 220  */
 221 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 222 /*-----------------------------------------------------------------------
 223  * FLASH organization
 224  */
 225 #define CONFIG_SYS_UPDATE_FLASH_SIZE
 226 #define CONFIG_SYS_FLASH_PROTECTION
 227 #define CONFIG_SYS_FLASH_EMPTY_INFO
 228
 229 #define CONFIG_SYS_FLASH_CFI
 230 #define CONFIG_FLASH_CFI_DRIVER
 231
 232 #define CONFIG_FLASH_SHOW_PROGRESS      45
 233
 234 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 235 #define CONFIG_SYS_MAX_FLASH_SECT       256
 236
 237 /*
 238  * JFFS2 partitions
 239  *
 240  */
 241 /* No command line, one static partition, whole device */
 242 #undef CONFIG_CMD_MTDPARTS
 243 #define CONFIG_JFFS2_DEV                "nor0"
 244 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 245 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 246
 247 /* mtdparts command line support */
 248 /* Note: fake mtd_id used, no linux mtd map file */
 249 /*
 250 #define CONFIG_CMD_MTDPARTS
 251 #define MTDIDS_DEFAULT          "nor0=mip405-0"
 252 #define MTDPARTS_DEFAULT        "mtdparts=mip405-0:-(jffs2)"
 253 */
 254
 255 /*-----------------------------------------------------------------------
 256  * Logbuffer Configuration
 257  */
 258 #undef CONFIG_LOGBUFFER         /* supported but not enabled */
 259 /*-----------------------------------------------------------------------
 260  * Bootcountlimit Configuration
 261  */
 262 #undef CONFIG_BOOTCOUNT_LIMIT   /* supported but not enabled */
 263
 264 /*-----------------------------------------------------------------------
 265  * POST Configuration
 266  */
 267 #if 0 /* enable this if POST is desired (is supported but not enabled) */
 268 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY | \
 269                                  CONFIG_SYS_POST_CPU            | \
 270                                  CONFIG_SYS_POST_RTC            | \
 271                                  CONFIG_SYS_POST_I2C)
 272
 273 #endif
 274 /*
 275  * Init Memory Controller:
 276  */
 277 #define FLASH_MAX_SIZE          0x00800000              /* 8MByte max */
 278 #define FLASH_BASE_PRELIM       0xFF800000  /* open the flash CS */
 279 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 280 #define FLASH_SIZE_PRELIM        3  /* maximal flash FLASH size bank #0 */
 281
 282 #define CONFIG_BOARD_EARLY_INIT_F 1
 283 #define CONFIG_BOARD_EARLY_INIT_R
 284
 285 /* Peripheral Bus Mapping */
 286 #define PER_PLD_ADDR            0xF4000000 /* smallest window is 1MByte 0x10 0000*/
 287 #define PER_UART0_ADDR          0xF4100000 /* smallest window is 1MByte 0x10 0000*/
 288 #define PER_UART1_ADDR          0xF4200000 /* smallest window is 1MByte 0x10 0000*/
 289
 290 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
 291 #define CONFIG_PORT_ADDR        PER_PLD_ADDR + 5
 292
 293
 294 /*-----------------------------------------------------------------------
 295  * Definitions for initial stack pointer and data area (in On Chip SRAM)
 296  */
 297 #define CONFIG_SYS_TEMP_STACK_OCM      1
 298 #define CONFIG_SYS_OCM_DATA_ADDR        0xF0000000
 299 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 300 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR        /* inside of On Chip SRAM    */
 301 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE        /* Size of On Chip SRAM        */
 302 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 303 /* reserve some memory for POST and BOOT limit info */
 304 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 32)
 305
 306 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
 307 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
 308 #endif
 309
 310 /***********************************************************************
 311  * External peripheral base address
 312  ***********************************************************************/
 313 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
 314
 315 /***********************************************************************
 316  * Last Stage Init
 317  ***********************************************************************/
 318 #define CONFIG_LAST_STAGE_INIT
 319 /************************************************************
 320  * Ethernet Stuff
 321  ***********************************************************/
 322 #define CONFIG_PPC4xx_EMAC
 323 #define CONFIG_MII              1       /* MII PHY management           */
 324 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 325 #define CONFIG_PHY_RESET_DELAY  300     /* Intel LXT971A needs this */
 326 #define CONFIG_PHY_CMD_DELAY    40      /* Intel LXT971A needs this */
 327 /************************************************************
 328  * RTC
 329  ***********************************************************/
 330 #define CONFIG_RTC_MC146818
 331 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 332
 333 /************************************************************
 334  * IDE/ATA stuff
 335  ************************************************************/
 336 #if defined(CONFIG_MIP405T)
 337 #define CONFIG_SYS_IDE_MAXBUS           1   /* MIP405T has only one IDE bus     */
 338 #else
 339 #define CONFIG_SYS_IDE_MAXBUS           2   /* max. 2 IDE busses        */
 340 #endif
 341
 342 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 343
 344 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
 345 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x01F0          /* ide0 offste */
 346 #define CONFIG_SYS_ATA_IDE1_OFFSET      0x0170          /* ide1 offset */
 347 #define CONFIG_SYS_ATA_DATA_OFFSET      0               /* data reg offset      */
 348 #define CONFIG_SYS_ATA_REG_OFFSET       0               /* reg offset */
 349 #define CONFIG_SYS_ATA_ALT_OFFSET       0x200           /* alternate register offset */
 350
 351 #undef  CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
 352 #undef  CONFIG_IDE_LED         /* no led for ide supported     */
 353 #define CONFIG_IDE_RESET       /* reset for ide supported...    */
 354 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
 355 #define CONFIG_SUPPORT_VFAT
 356 /************************************************************
 357  * ATAPI support (experimental)
 358  ************************************************************/
 359 #define CONFIG_ATAPI                    /* enable ATAPI Support */
 360
 361 /************************************************************
 362  * DISK Partition support
 363  ************************************************************/
 364 #define CONFIG_DOS_PARTITION
 365 #define CONFIG_MAC_PARTITION
 366 #define CONFIG_ISO_PARTITION /* Experimental */
 367
 368 /************************************************************
 369  * Keyboard support
 370  ************************************************************/
 371 #undef CONFIG_ISA_KEYBOARD
 372
 373 /************************************************************
 374  * Video support
 375  ************************************************************/
 376 #define CONFIG_VIDEO                    /*To enable video controller support */
 377 #define CONFIG_VIDEO_CT69000
 378 #define CONFIG_CFB_CONSOLE
 379 #define CONFIG_VIDEO_LOGO
 380 #define CONFIG_CONSOLE_EXTRA_INFO
 381 #define CONFIG_VGA_AS_SINGLE_DEVICE
 382 #define CONFIG_VIDEO_SW_CURSOR
 383 #undef CONFIG_VIDEO_ONBOARD
 384 /************************************************************
 385  * USB support EXPERIMENTAL
 386  ************************************************************/
 387 #if !defined(CONFIG_MIP405T)
 388 #define CONFIG_USB_UHCI
 389 #define CONFIG_USB_KEYBOARD
 390 #define CONFIG_USB_STORAGE
 391
 392 /* Enable needed helper functions */
 393 #define CONFIG_SYS_STDIO_DEREGISTER             /* needs stdio_deregister */
 394 #endif
 395 /************************************************************
 396  * Debug support
 397  ************************************************************/
 398 #if defined(CONFIG_CMD_KGDB)
 399 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 400 #endif
 401
 402 /************************************************************
 403  * support BZIP2 compression
 404  ************************************************************/
 405 #define CONFIG_BZIP2            1
 406
 407 /************************************************************
 408  * Ident
 409  ************************************************************/
 410
 411 #define VERSION_TAG "released"
 412 #if !defined(CONFIG_MIP405T)
 413 #define CONFIG_ISO_STRING "MEV-10072-001"
 414 #else
 415 #define CONFIG_ISO_STRING "MEV-10082-001"
 416 #endif
 417
 418 #if !defined(CONFIG_BOOT_PCI)
 419 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
 420 #else
 421 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
 422 #endif
 423
 424
 425 #endif  /* __CONFIG_H */