include/configs/MIP405.h

   1 /*
   2  * (C) Copyright 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /***********************************************************
  16  * High Level Configuration Options
  17  * (easy to change)
  18  ***********************************************************/
  19 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  20 #define CONFIG_MIP405           1       /* ...on a MIP405 board         */
  21
  22 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  23
  24 #define CONFIG_SYS_GENERIC_BOARD
  25
  26 /***********************************************************
  27  * Note that it may also be a MIP405T board which is a subset of the
  28  * MIP405
  29  ***********************************************************/
  30 /***********************************************************
  31  * WARNING:
  32  * CONFIG_BOOT_PCI is only used for first boot-up and should
  33  * NOT be enabled for production bootloader
  34  ***********************************************************/
  35 /*#define        CONFIG_BOOT_PCI         1*/
  36 /***********************************************************
  37  * Clock
  38  ***********************************************************/
  39 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  40
  41
  42 /*
  43  * BOOTP options
  44  */
  45 #define CONFIG_BOOTP_BOOTFILESIZE
  46 #define CONFIG_BOOTP_BOOTPATH
  47 #define CONFIG_BOOTP_GATEWAY
  48 #define CONFIG_BOOTP_HOSTNAME
  49
  50
  51 /*
  52  * Command line configuration.
  53  */
  54 #define CONFIG_CMD_CACHE
  55 #define CONFIG_CMD_DATE
  56 #define CONFIG_CMD_DHCP
  57 #define CONFIG_CMD_EEPROM
  58 #define CONFIG_CMD_FAT
  59 #define CONFIG_CMD_I2C
  60 #define CONFIG_CMD_IDE
  61 #define CONFIG_CMD_IRQ
  62 #define CONFIG_CMD_JFFS2
  63 #define CONFIG_CMD_MII
  64 #define CONFIG_CMD_PCI
  65 #define CONFIG_CMD_PING
  66 #define CONFIG_CMD_REGINFO
  67 #define CONFIG_CMD_SAVES
  68 #define CONFIG_CMD_BSP
  69
  70 #if !defined(CONFIG_MIP405T)
  71     #define CONFIG_CMD_USB
  72 #endif
  73
  74
  75 #define  CONFIG_SYS_HUSH_PARSER
  76 /**************************************************************
  77  * I2C Stuff:
  78  * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
  79  * 0x53.
  80  * The Atmel EEPROM uses 16Bit addressing.
  81  ***************************************************************/
  82
  83 #define CONFIG_SYS_I2C
  84 #define CONFIG_SYS_I2C_PPC4XX
  85 #define CONFIG_SYS_I2C_PPC4XX_CH0
  86 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           50000
  87 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
  88
  89 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x53    /* EEPROM 24C128/256            */
  90 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* Bytes of address             */
  91 /* mask of address bits that overflow into the "EEPROM chip address"    */
  92 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  93 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6     /* The Atmel 24C128/256 has     */
  94                                         /* 64 byte page write mode using*/
  95                                         /* last 6 bits of the address   */
  96 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
  97
  98
  99 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 100 #define CONFIG_ENV_OFFSET               0x00000 /* environment starts at the beginning of the EEPROM */
 101 #define CONFIG_ENV_SIZE         0x00800 /* 2k bytes may be used for env vars */
 102
 103 /***************************************************************
 104  * Definitions for Serial Presence Detect EEPROM address
 105  * (to get SDRAM settings)
 106  ***************************************************************/
 107 /*#define SDRAM_EEPROM_WRITE_ADDRESS    0xA0
 108 #define SDRAM_EEPROM_READ_ADDRESS       0xA1
 109 */
 110 /**************************************************************
 111  * Environment definitions
 112  **************************************************************/
 113 #define CONFIG_BAUDRATE         9600    /* STD Baudrate */
 114 #define CONFIG_BOOTDELAY        5
 115 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 116 /* #define CONFIG_BOOT_RETRY_TIME       -10     /XXX* feature is available but not enabled */
 117 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check console even if bootdelay = 0 */
 118
 119 #define CONFIG_BOOTCOMMAND      "diskboot 400000 0:1; bootm" /* autoboot command                */
 120 #define CONFIG_BOOTARGS         "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
 121
 122 #define CONFIG_IPADDR           10.0.0.100
 123 #define CONFIG_SERVERIP         10.0.0.1
 124 #define CONFIG_PREBOOT
 125 /***************************************************************
 126  * defines if the console is stored in the environment
 127  ***************************************************************/
 128 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* stdin, stdout and stderr are in evironment */
 129 /***************************************************************
 130  * defines if an overwrite_console function exists
 131  *************************************************************/
 132 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 133 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 134 /***************************************************************
 135  * defines if the overwrite_console should be stored in the
 136  * environment
 137  **************************************************************/
 138 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 139
 140 /**************************************************************
 141  * loads config
 142  *************************************************************/
 143 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 144 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 145
 146 #define CONFIG_MISC_INIT_R
 147 /***********************************************************
 148  * Miscellaneous configurable options
 149  **********************************************************/
 150 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 151 #if defined(CONFIG_CMD_KGDB)
 152 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 153 #else
 154 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 155 #endif
 156 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 157 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 158 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 159
 160 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 161 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 1 ... 12 MB in DRAM  */
 162
 163 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 164 #define CONFIG_SYS_NS16550
 165 #define CONFIG_SYS_NS16550_SERIAL
 166 #define CONFIG_SYS_NS16550_REG_SIZE     1
 167 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 168
 169 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 170 #define CONFIG_SYS_BASE_BAUD       916667
 171
 172 /* The following table includes the supported baudrates */
 173 #define CONFIG_SYS_BAUDRATE_TABLE       \
 174         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 175          57600, 115200, 230400, 460800, 921600 }
 176
 177 #define CONFIG_SYS_LOAD_ADDR    0x400000        /* default load address */
 178 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 179
 180 /*-----------------------------------------------------------------------
 181  * PCI stuff
 182  *-----------------------------------------------------------------------
 183  */
 184 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 185 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 186 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 187
 188 #define CONFIG_PCI                      /* include pci support          */
 189 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 190 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* configure as pci-host        */
 191 #define CONFIG_PCI_PNP                  /* pci plug-and-play            */
 192                                         /* resource configuration       */
 193 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000   /* PCI Vendor ID: to-do!!!      */
 194 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000   /* PCI Device ID: to-do!!!      */
 195 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 196 #define CONFIG_SYS_PCI_PTM1MS   0x80000001      /* 2GB, enable hard-wired to 1  */
 197 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 198 #define CONFIG_SYS_PCI_PTM2LA   0x00000000      /* disabled                     */
 199 #define CONFIG_SYS_PCI_PTM2MS   0x00000000      /* disabled                     */
 200 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 201
 202 /*-----------------------------------------------------------------------
 203  * Start addresses for the final memory configuration
 204  * (Set up by the startup code)
 205  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 206  */
 207 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 208 #define CONFIG_SYS_FLASH_BASE           0xFFF80000
 209 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 210 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Monitor   */
 211 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserve 1024 kB for malloc() */
 212
 213 /*
 214  * For booting Linux, the board info and command line data
 215  * have to be in the first 8 MB of memory, since this is
 216  * the maximum mapped by the Linux kernel during initialization.
 217  */
 218 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 219 /*-----------------------------------------------------------------------
 220  * FLASH organization
 221  */
 222 #define CONFIG_SYS_UPDATE_FLASH_SIZE
 223 #define CONFIG_SYS_FLASH_PROTECTION
 224 #define CONFIG_SYS_FLASH_EMPTY_INFO
 225
 226 #define CONFIG_SYS_FLASH_CFI
 227 #define CONFIG_FLASH_CFI_DRIVER
 228
 229 #define CONFIG_FLASH_SHOW_PROGRESS      45
 230
 231 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 232 #define CONFIG_SYS_MAX_FLASH_SECT       256
 233
 234 /*
 235  * JFFS2 partitions
 236  *
 237  */
 238 /* No command line, one static partition, whole device */
 239 #undef CONFIG_CMD_MTDPARTS
 240 #define CONFIG_JFFS2_DEV                "nor0"
 241 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 242 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 243
 244 /* mtdparts command line support */
 245 /* Note: fake mtd_id used, no linux mtd map file */
 246 /*
 247 #define CONFIG_CMD_MTDPARTS
 248 #define MTDIDS_DEFAULT          "nor0=mip405-0"
 249 #define MTDPARTS_DEFAULT        "mtdparts=mip405-0:-(jffs2)"
 250 */
 251
 252 /*-----------------------------------------------------------------------
 253  * Logbuffer Configuration
 254  */
 255 #undef CONFIG_LOGBUFFER         /* supported but not enabled */
 256 /*-----------------------------------------------------------------------
 257  * Bootcountlimit Configuration
 258  */
 259 #undef CONFIG_BOOTCOUNT_LIMIT   /* supported but not enabled */
 260
 261 /*-----------------------------------------------------------------------
 262  * POST Configuration
 263  */
 264 #if 0 /* enable this if POST is desired (is supported but not enabled) */
 265 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY | \
 266                                  CONFIG_SYS_POST_CPU            | \
 267                                  CONFIG_SYS_POST_RTC            | \
 268                                  CONFIG_SYS_POST_I2C)
 269
 270 #endif
 271 /*
 272  * Init Memory Controller:
 273  */
 274 #define FLASH_MAX_SIZE          0x00800000              /* 8MByte max */
 275 #define FLASH_BASE_PRELIM       0xFF800000  /* open the flash CS */
 276 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 277 #define FLASH_SIZE_PRELIM        3  /* maximal flash FLASH size bank #0 */
 278
 279 #define CONFIG_BOARD_EARLY_INIT_F 1
 280 #define CONFIG_BOARD_EARLY_INIT_R
 281
 282 /* Peripheral Bus Mapping */
 283 #define PER_PLD_ADDR            0xF4000000 /* smallest window is 1MByte 0x10 0000*/
 284 #define PER_UART0_ADDR          0xF4100000 /* smallest window is 1MByte 0x10 0000*/
 285 #define PER_UART1_ADDR          0xF4200000 /* smallest window is 1MByte 0x10 0000*/
 286
 287 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
 288 #define CONFIG_PORT_ADDR        PER_PLD_ADDR + 5
 289
 290
 291 /*-----------------------------------------------------------------------
 292  * Definitions for initial stack pointer and data area (in On Chip SRAM)
 293  */
 294 #define CONFIG_SYS_TEMP_STACK_OCM      1
 295 #define CONFIG_SYS_OCM_DATA_ADDR        0xF0000000
 296 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 297 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR        /* inside of On Chip SRAM    */
 298 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE        /* Size of On Chip SRAM        */
 299 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 300 /* reserve some memory for POST and BOOT limit info */
 301 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 32)
 302
 303 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
 304 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
 305 #endif
 306
 307 /***********************************************************************
 308  * External peripheral base address
 309  ***********************************************************************/
 310 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
 311
 312 /***********************************************************************
 313  * Last Stage Init
 314  ***********************************************************************/
 315 #define CONFIG_LAST_STAGE_INIT
 316 /************************************************************
 317  * Ethernet Stuff
 318  ***********************************************************/
 319 #define CONFIG_PPC4xx_EMAC
 320 #define CONFIG_MII              1       /* MII PHY management           */
 321 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 322 #define CONFIG_PHY_RESET_DELAY  300     /* Intel LXT971A needs this */
 323 #define CONFIG_PHY_CMD_DELAY    40      /* Intel LXT971A needs this */
 324 /************************************************************
 325  * RTC
 326  ***********************************************************/
 327 #define CONFIG_RTC_MC146818
 328 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 329
 330 /************************************************************
 331  * IDE/ATA stuff
 332  ************************************************************/
 333 #if defined(CONFIG_MIP405T)
 334 #define CONFIG_SYS_IDE_MAXBUS           1   /* MIP405T has only one IDE bus     */
 335 #else
 336 #define CONFIG_SYS_IDE_MAXBUS           2   /* max. 2 IDE busses        */
 337 #endif
 338
 339 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 340
 341 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
 342 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x01F0          /* ide0 offste */
 343 #define CONFIG_SYS_ATA_IDE1_OFFSET      0x0170          /* ide1 offset */
 344 #define CONFIG_SYS_ATA_DATA_OFFSET      0               /* data reg offset      */
 345 #define CONFIG_SYS_ATA_REG_OFFSET       0               /* reg offset */
 346 #define CONFIG_SYS_ATA_ALT_OFFSET       0x200           /* alternate register offset */
 347
 348 #undef  CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
 349 #undef  CONFIG_IDE_LED         /* no led for ide supported     */
 350 #define CONFIG_IDE_RESET       /* reset for ide supported...    */
 351 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
 352 #define CONFIG_SUPPORT_VFAT
 353 /************************************************************
 354  * ATAPI support (experimental)
 355  ************************************************************/
 356 #define CONFIG_ATAPI                    /* enable ATAPI Support */
 357
 358 /************************************************************
 359  * DISK Partition support
 360  ************************************************************/
 361 #define CONFIG_DOS_PARTITION
 362 #define CONFIG_MAC_PARTITION
 363 #define CONFIG_ISO_PARTITION /* Experimental */
 364
 365 /************************************************************
 366  * Keyboard support
 367  ************************************************************/
 368 #undef CONFIG_ISA_KEYBOARD
 369
 370 /************************************************************
 371  * Video support
 372  ************************************************************/
 373 #define CONFIG_VIDEO                    /*To enable video controller support */
 374 #define CONFIG_VIDEO_CT69000
 375 #define CONFIG_CFB_CONSOLE
 376 #define CONFIG_VIDEO_LOGO
 377 #define CONFIG_CONSOLE_EXTRA_INFO
 378 #define CONFIG_VGA_AS_SINGLE_DEVICE
 379 #define CONFIG_VIDEO_SW_CURSOR
 380 #undef CONFIG_VIDEO_ONBOARD
 381 /************************************************************
 382  * USB support EXPERIMENTAL
 383  ************************************************************/
 384 #if !defined(CONFIG_MIP405T)
 385 #define CONFIG_USB_UHCI
 386 #define CONFIG_USB_KEYBOARD
 387 #define CONFIG_USB_STORAGE
 388
 389 /* Enable needed helper functions */
 390 #define CONFIG_SYS_STDIO_DEREGISTER             /* needs stdio_deregister */
 391 #endif
 392 /************************************************************
 393  * Debug support
 394  ************************************************************/
 395 #if defined(CONFIG_CMD_KGDB)
 396 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 397 #endif
 398
 399 /************************************************************
 400  * support BZIP2 compression
 401  ************************************************************/
 402 #define CONFIG_BZIP2            1
 403
 404 /************************************************************
 405  * Ident
 406  ************************************************************/
 407
 408 #define VERSION_TAG "released"
 409 #if !defined(CONFIG_MIP405T)
 410 #define CONFIG_ISO_STRING "MEV-10072-001"
 411 #else
 412 #define CONFIG_ISO_STRING "MEV-10082-001"
 413 #endif
 414
 415 #if !defined(CONFIG_BOOT_PCI)
 416 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
 417 #else
 418 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
 419 #endif
 420
 421
 422 #endif  /* __CONFIG_H */