include/configs/MIP405.h

   1 /*
   2  * (C) Copyright 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /***********************************************************
  32  * High Level Configuration Options
  33  * (easy to change)
  34  ***********************************************************/
  35 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  36 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  37 #define CONFIG_MIP405           1       /* ...on a MIP405 board         */
  38 /***********************************************************
  39  * Note that it may also be a MIP405T board which is a subset of the
  40  * MIP405
  41  ***********************************************************/
  42 /***********************************************************
  43  * WARNING:
  44  * CONFIG_BOOT_PCI is only used for first boot-up and should
  45  * NOT be enabled for production bootloader
  46  ***********************************************************/
  47 /*#define        CONFIG_BOOT_PCI         1*/
  48 /***********************************************************
  49  * Clock
  50  ***********************************************************/
  51 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  52
  53
  54 /*
  55  * BOOTP options
  56  */
  57 #define CONFIG_BOOTP_BOOTFILESIZE
  58 #define CONFIG_BOOTP_BOOTPATH
  59 #define CONFIG_BOOTP_GATEWAY
  60 #define CONFIG_BOOTP_HOSTNAME
  61
  62
  63 /*
  64  * Command line configuration.
  65  */
  66 #include <config_cmd_default.h>
  67
  68 #define CONFIG_CMD_CACHE
  69 #define CONFIG_CMD_DATE
  70 #define CONFIG_CMD_DHCP
  71 #define CONFIG_CMD_EEPROM
  72 #define CONFIG_CMD_ELF
  73 #define CONFIG_CMD_FAT
  74 #define CONFIG_CMD_I2C
  75 #define CONFIG_CMD_IDE
  76 #define CONFIG_CMD_IRQ
  77 #define CONFIG_CMD_JFFS2
  78 #define CONFIG_CMD_MII
  79 #define CONFIG_CMD_PCI
  80 #define CONFIG_CMD_PING
  81 #define CONFIG_CMD_REGINFO
  82 #define CONFIG_CMD_SAVES
  83 #define CONFIG_CMD_BSP
  84
  85 #if !defined(CONFIG_MIP405T)
  86     #define CONFIG_CMD_USB
  87     #define CONFIG_CMD_DOC
  88 #endif
  89
  90
  91 #define CONFIG_NAND_LEGACY
  92
  93 #define  CONFIG_SYS_HUSH_PARSER
  94 #define  CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  95 /**************************************************************
  96  * I2C Stuff:
  97  * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
  98  * 0x53.
  99  * The Atmel EEPROM uses 16Bit addressing.
 100  ***************************************************************/
 101
 102 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 103 #define CONFIG_SYS_I2C_SPEED            50000   /* I2C speed and slave address */
 104 #define CONFIG_SYS_I2C_SLAVE            0x7F
 105
 106 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x53    /* EEPROM 24C128/256            */
 107 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* Bytes of address             */
 108 /* mask of address bits that overflow into the "EEPROM chip address"    */
 109 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 110 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6     /* The Atmel 24C128/256 has     */
 111                                         /* 64 byte page write mode using*/
 112                                         /* last 6 bits of the address   */
 113 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 114
 115
 116 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 117 #define CONFIG_ENV_OFFSET               0x00000 /* environment starts at the beginning of the EEPROM */
 118 #define CONFIG_ENV_SIZE         0x00800 /* 2k bytes may be used for env vars */
 119
 120 /***************************************************************
 121  * Definitions for Serial Presence Detect EEPROM address
 122  * (to get SDRAM settings)
 123  ***************************************************************/
 124 /*#define SDRAM_EEPROM_WRITE_ADDRESS    0xA0
 125 #define SDRAM_EEPROM_READ_ADDRESS       0xA1
 126 */
 127 /**************************************************************
 128  * Environment definitions
 129  **************************************************************/
 130 #define CONFIG_BAUDRATE         9600    /* STD Baudrate */
 131 #define CONFIG_BOOTDELAY        5
 132 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 133 /* #define CONFIG_BOOT_RETRY_TIME       -10     /XXX* feature is available but not enabled */
 134 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check console even if bootdelay = 0 */
 135
 136 #define CONFIG_BOOTCOMMAND      "diskboot 400000 0:1; bootm" /* autoboot command                */
 137 #define CONFIG_BOOTARGS         "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
 138
 139 #define CONFIG_IPADDR           10.0.0.100
 140 #define CONFIG_SERVERIP         10.0.0.1
 141 #define CONFIG_PREBOOT
 142 /***************************************************************
 143  * defines if the console is stored in the environment
 144  ***************************************************************/
 145 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* stdin, stdout and stderr are in evironment */
 146 /***************************************************************
 147  * defines if an overwrite_console function exists
 148  *************************************************************/
 149 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 150 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 151 /***************************************************************
 152  * defines if the overwrite_console should be stored in the
 153  * environment
 154  **************************************************************/
 155 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 156
 157 /**************************************************************
 158  * loads config
 159  *************************************************************/
 160 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 161 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 162
 163 #define CONFIG_MISC_INIT_R
 164 /***********************************************************
 165  * Miscellaneous configurable options
 166  **********************************************************/
 167 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 168 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 169 #if defined(CONFIG_CMD_KGDB)
 170 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 171 #else
 172 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 173 #endif
 174 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 175 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 176 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 177
 178 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 179 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 1 ... 12 MB in DRAM  */
 180
 181 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 182 #define CONFIG_SYS_BASE_BAUD       916667
 183
 184 /* The following table includes the supported baudrates */
 185 #define CONFIG_SYS_BAUDRATE_TABLE       \
 186         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 187          57600, 115200, 230400, 460800, 921600 }
 188
 189 #define CONFIG_SYS_LOAD_ADDR    0x400000        /* default load address */
 190 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 191
 192 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 193
 194 /*-----------------------------------------------------------------------
 195  * PCI stuff
 196  *-----------------------------------------------------------------------
 197  */
 198 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 199 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 200 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 201
 202 #define CONFIG_PCI                      /* include pci support          */
 203 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* configure as pci-host        */
 204 #define CONFIG_PCI_PNP                  /* pci plug-and-play            */
 205                                         /* resource configuration       */
 206 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000   /* PCI Vendor ID: to-do!!!      */
 207 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000   /* PCI Device ID: to-do!!!      */
 208 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 209 #define CONFIG_SYS_PCI_PTM1MS   0x80000001      /* 2GB, enable hard-wired to 1  */
 210 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 211 #define CONFIG_SYS_PCI_PTM2LA   0x00000000      /* disabled                     */
 212 #define CONFIG_SYS_PCI_PTM2MS   0x00000000      /* disabled                     */
 213 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 214
 215 /*-----------------------------------------------------------------------
 216  * Start addresses for the final memory configuration
 217  * (Set up by the startup code)
 218  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 219  */
 220 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 221 #define CONFIG_SYS_FLASH_BASE           0xFFF80000
 222 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 223 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Monitor   */
 224 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserve 1024 kB for malloc() */
 225
 226 /*
 227  * For booting Linux, the board info and command line data
 228  * have to be in the first 8 MB of memory, since this is
 229  * the maximum mapped by the Linux kernel during initialization.
 230  */
 231 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 232 /*-----------------------------------------------------------------------
 233  * FLASH organization
 234  */
 235 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 236 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 237
 238 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 239 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 240
 241 /*
 242  * JFFS2 partitions
 243  *
 244  */
 245 /* No command line, one static partition, whole device */
 246 #undef CONFIG_CMD_MTDPARTS
 247 #define CONFIG_JFFS2_DEV                "nor0"
 248 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 249 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 250
 251 /* mtdparts command line support */
 252 /* Note: fake mtd_id used, no linux mtd map file */
 253 /*
 254 #define CONFIG_CMD_MTDPARTS
 255 #define MTDIDS_DEFAULT          "nor0=mip405-0"
 256 #define MTDPARTS_DEFAULT        "mtdparts=mip405-0:-(jffs2)"
 257 */
 258
 259 /*-----------------------------------------------------------------------
 260  * Logbuffer Configuration
 261  */
 262 #undef CONFIG_LOGBUFFER         /* supported but not enabled */
 263 /*-----------------------------------------------------------------------
 264  * Bootcountlimit Configuration
 265  */
 266 #undef CONFIG_BOOTCOUNT_LIMIT   /* supported but not enabled */
 267
 268 /*-----------------------------------------------------------------------
 269  * POST Configuration
 270  */
 271 #if 0 /* enable this if POST is desired (is supported but not enabled) */
 272 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY | \
 273                                  CONFIG_SYS_POST_CPU            | \
 274                                  CONFIG_SYS_POST_RTC            | \
 275                                  CONFIG_SYS_POST_I2C)
 276
 277 #endif
 278 /*
 279  * Init Memory Controller:
 280  */
 281 #define FLASH_MAX_SIZE          0x00800000              /* 8MByte max */
 282 #define FLASH_BASE_PRELIM       0xFF800000  /* open the flash CS */
 283 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 284 #define FLASH_SIZE_PRELIM        3  /* maximal flash FLASH size bank #0 */
 285
 286 #define CONFIG_BOARD_EARLY_INIT_F 1
 287
 288 /* Peripheral Bus Mapping */
 289 #define PER_PLD_ADDR            0xF4000000 /* smallest window is 1MByte 0x10 0000*/
 290 #define PER_UART0_ADDR          0xF4100000 /* smallest window is 1MByte 0x10 0000*/
 291 #define PER_UART1_ADDR          0xF4200000 /* smallest window is 1MByte 0x10 0000*/
 292
 293 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
 294 #define CONFIG_PORT_ADDR        PER_PLD_ADDR + 5
 295
 296
 297 /*-----------------------------------------------------------------------
 298  * Definitions for initial stack pointer and data area (in On Chip SRAM)
 299  */
 300 #define CONFIG_SYS_TEMP_STACK_OCM      1
 301 #define CONFIG_SYS_OCM_DATA_ADDR        0xF0000000
 302 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 303 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR        /* inside of On Chip SRAM    */
 304 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE        /* End of On Chip SRAM         */
 305 #define CONFIG_SYS_GBL_DATA_SIZE        64              /* size in bytes reserved for initial data */
 306 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 307 /* reserve some memory for POST and BOOT limit info */
 308 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 32)
 309
 310 #ifdef  CONFIG_POST             /* reserve one word for POST Info */
 311 #define CONFIG_SYS_POST_WORD_ADDR       (CONFIG_SYS_GBL_DATA_OFFSET - 4)
 312 #endif
 313
 314 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
 315 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
 316 #endif
 317
 318 /*
 319  * Internal Definitions
 320  *
 321  * Boot Flags
 322  */
 323 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 324 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 325
 326
 327 /***********************************************************************
 328  * External peripheral base address
 329  ***********************************************************************/
 330 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
 331
 332 /***********************************************************************
 333  * Last Stage Init
 334  ***********************************************************************/
 335 #define CONFIG_LAST_STAGE_INIT
 336 /************************************************************
 337  * Ethernet Stuff
 338  ***********************************************************/
 339 #define CONFIG_PPC4xx_EMAC
 340 #define CONFIG_MII              1       /* MII PHY management           */
 341 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 342 #define CONFIG_PHY_RESET_DELAY  300     /* Intel LXT971A needs this */
 343 #define CONFIG_PHY_CMD_DELAY    40      /* Intel LXT971A needs this */
 344 /************************************************************
 345  * RTC
 346  ***********************************************************/
 347 #define CONFIG_RTC_MC146818
 348 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 349
 350 /************************************************************
 351  * IDE/ATA stuff
 352  ************************************************************/
 353 #if defined(CONFIG_MIP405T)
 354 #define CONFIG_SYS_IDE_MAXBUS           1   /* MIP405T has only one IDE bus     */
 355 #else
 356 #define CONFIG_SYS_IDE_MAXBUS           2   /* max. 2 IDE busses        */
 357 #endif
 358
 359 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 360
 361 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
 362 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x01F0          /* ide0 offste */
 363 #define CONFIG_SYS_ATA_IDE1_OFFSET      0x0170          /* ide1 offset */
 364 #define CONFIG_SYS_ATA_DATA_OFFSET      0               /* data reg offset      */
 365 #define CONFIG_SYS_ATA_REG_OFFSET       0               /* reg offset */
 366 #define CONFIG_SYS_ATA_ALT_OFFSET       0x200           /* alternate register offset */
 367
 368 #undef  CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
 369 #undef  CONFIG_IDE_LED         /* no led for ide supported     */
 370 #define CONFIG_IDE_RESET       /* reset for ide supported...    */
 371 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
 372 #define CONFIG_SUPPORT_VFAT
 373 /************************************************************
 374  * ATAPI support (experimental)
 375  ************************************************************/
 376 #define CONFIG_ATAPI                    /* enable ATAPI Support */
 377
 378 /************************************************************
 379  * DISK Partition support
 380  ************************************************************/
 381 #define CONFIG_DOS_PARTITION
 382 #define CONFIG_MAC_PARTITION
 383 #define CONFIG_ISO_PARTITION /* Experimental */
 384
 385 /************************************************************
 386  * Disk-On-Chip configuration
 387  ************************************************************/
 388 #define CONFIG_SYS_MAX_DOC_DEVICE       1       /* Max number of DOC devices            */
 389 #define CONFIG_SYS_DOC_SHORT_TIMEOUT
 390 #define CONFIG_SYS_DOC_SUPPORT_2000
 391 #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 392 /************************************************************
 393  * Keyboard support
 394  ************************************************************/
 395 #undef CONFIG_ISA_KEYBOARD
 396
 397 /************************************************************
 398  * Video support
 399  ************************************************************/
 400 #define CONFIG_VIDEO                    /*To enable video controller support */
 401 #define CONFIG_VIDEO_CT69000
 402 #define CONFIG_CFB_CONSOLE
 403 #define CONFIG_VIDEO_LOGO
 404 #define CONFIG_CONSOLE_EXTRA_INFO
 405 #define CONFIG_VGA_AS_SINGLE_DEVICE
 406 #define CONFIG_VIDEO_SW_CURSOR
 407 #undef CONFIG_VIDEO_ONBOARD
 408 /************************************************************
 409  * USB support EXPERIMENTAL
 410  ************************************************************/
 411 #if !defined(CONFIG_MIP405T)
 412 #define CONFIG_USB_UHCI
 413 #define CONFIG_USB_KEYBOARD
 414 #define CONFIG_USB_STORAGE
 415
 416 /* Enable needed helper functions */
 417 #define CONFIG_SYS_DEVICE_DEREGISTER            /* needs device_deregister */
 418 #endif
 419 /************************************************************
 420  * Debug support
 421  ************************************************************/
 422 #if defined(CONFIG_CMD_KGDB)
 423 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 424 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 425 #endif
 426
 427 /************************************************************
 428  * support BZIP2 compression
 429  ************************************************************/
 430 #define CONFIG_BZIP2            1
 431
 432 /************************************************************
 433  * Ident
 434  ************************************************************/
 435
 436 #define VERSION_TAG "released"
 437 #if !defined(CONFIG_MIP405T)
 438 #define CONFIG_ISO_STRING "MEV-10072-001"
 439 #else
 440 #define CONFIG_ISO_STRING "MEV-10082-001"
 441 #endif
 442
 443 #if !defined(CONFIG_BOOT_PCI)
 444 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
 445 #else
 446 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
 447 #endif
 448
 449
 450 #endif  /* __CONFIG_H */