include/configs/MIP405.h

   1 /*
   2  * (C) Copyright 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /***********************************************************
  16  * High Level Configuration Options
  17  * (easy to change)
  18  ***********************************************************/
  19 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  20
  21 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  22
  23 /***********************************************************
  24  * Note that it may also be a MIP405T board which is a subset of the
  25  * MIP405
  26  ***********************************************************/
  27 /***********************************************************
  28  * WARNING:
  29  * CONFIG_BOOT_PCI is only used for first boot-up and should
  30  * NOT be enabled for production bootloader
  31  ***********************************************************/
  32 /*#define        CONFIG_BOOT_PCI         1*/
  33 /***********************************************************
  34  * Clock
  35  ***********************************************************/
  36 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  37
  38 /*
  39  * BOOTP options
  40  */
  41 #define CONFIG_BOOTP_BOOTFILESIZE
  42 #define CONFIG_BOOTP_BOOTPATH
  43 #define CONFIG_BOOTP_GATEWAY
  44 #define CONFIG_BOOTP_HOSTNAME
  45
  46 /*
  47  * Command line configuration.
  48  */
  49 #define CONFIG_CMD_DATE
  50 #define CONFIG_CMD_EEPROM
  51 #define CONFIG_CMD_IDE
  52 #define CONFIG_CMD_IRQ
  53 #define CONFIG_CMD_JFFS2
  54 #define CONFIG_CMD_PCI
  55 #define CONFIG_CMD_REGINFO
  56 #define CONFIG_CMD_SAVES
  57 #define CONFIG_CMD_BSP
  58
  59 /**************************************************************
  60  * I2C Stuff:
  61  * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
  62  * 0x53.
  63  * The Atmel EEPROM uses 16Bit addressing.
  64  ***************************************************************/
  65
  66 #define CONFIG_SYS_I2C
  67 #define CONFIG_SYS_I2C_PPC4XX
  68 #define CONFIG_SYS_I2C_PPC4XX_CH0
  69 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           50000
  70 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
  71
  72 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x53    /* EEPROM 24C128/256            */
  73 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* Bytes of address             */
  74 /* mask of address bits that overflow into the "EEPROM chip address"    */
  75 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  76 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6     /* The Atmel 24C128/256 has     */
  77                                         /* 64 byte page write mode using*/
  78                                         /* last 6 bits of the address   */
  79 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
  80
  81 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
  82 #define CONFIG_ENV_OFFSET               0x00000 /* environment starts at the beginning of the EEPROM */
  83 #define CONFIG_ENV_SIZE         0x00800 /* 2k bytes may be used for env vars */
  84
  85 /***************************************************************
  86  * Definitions for Serial Presence Detect EEPROM address
  87  * (to get SDRAM settings)
  88  ***************************************************************/
  89 /*#define SDRAM_EEPROM_WRITE_ADDRESS    0xA0
  90 #define SDRAM_EEPROM_READ_ADDRESS       0xA1
  91 */
  92 /**************************************************************
  93  * Environment definitions
  94  **************************************************************/
  95 #define CONFIG_BAUDRATE         9600    /* STD Baudrate */
  96 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
  97 /* #define CONFIG_BOOT_RETRY_TIME       -10     /XXX* feature is available but not enabled */
  98
  99 #define CONFIG_BOOTCOMMAND      "diskboot 400000 0:1; bootm" /* autoboot command                */
 100 #define CONFIG_BOOTARGS         "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
 101
 102 #define CONFIG_IPADDR           10.0.0.100
 103 #define CONFIG_SERVERIP         10.0.0.1
 104 #define CONFIG_PREBOOT
 105 /***************************************************************
 106  * defines if the console is stored in the environment
 107  ***************************************************************/
 108 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* stdin, stdout and stderr are in evironment */
 109 /***************************************************************
 110  * defines if an overwrite_console function exists
 111  *************************************************************/
 112 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 113 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 114 /***************************************************************
 115  * defines if the overwrite_console should be stored in the
 116  * environment
 117  **************************************************************/
 118 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 119
 120 /**************************************************************
 121  * loads config
 122  *************************************************************/
 123 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 124 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 125
 126 #define CONFIG_MISC_INIT_R
 127 /***********************************************************
 128  * Miscellaneous configurable options
 129  **********************************************************/
 130 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 131 #if defined(CONFIG_CMD_KGDB)
 132 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 133 #else
 134 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 135 #endif
 136 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 137 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 138 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 139
 140 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 141 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 1 ... 12 MB in DRAM  */
 142
 143 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 144 #define CONFIG_SYS_NS16550_SERIAL
 145 #define CONFIG_SYS_NS16550_REG_SIZE     1
 146 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 147
 148 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 149 #define CONFIG_SYS_BASE_BAUD       916667
 150
 151 /* The following table includes the supported baudrates */
 152 #define CONFIG_SYS_BAUDRATE_TABLE       \
 153         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 154          57600, 115200, 230400, 460800, 921600 }
 155
 156 #define CONFIG_SYS_LOAD_ADDR    0x400000        /* default load address */
 157 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 158
 159 /*-----------------------------------------------------------------------
 160  * PCI stuff
 161  *-----------------------------------------------------------------------
 162  */
 163 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 164 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 165 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 166
 167 #define CONFIG_PCI                      /* include pci support          */
 168 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 169 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* configure as pci-host        */
 170 #define CONFIG_PCI_PNP                  /* pci plug-and-play            */
 171                                         /* resource configuration       */
 172 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000   /* PCI Vendor ID: to-do!!!      */
 173 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000   /* PCI Device ID: to-do!!!      */
 174 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 175 #define CONFIG_SYS_PCI_PTM1MS   0x80000001      /* 2GB, enable hard-wired to 1  */
 176 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 177 #define CONFIG_SYS_PCI_PTM2LA   0x00000000      /* disabled                     */
 178 #define CONFIG_SYS_PCI_PTM2MS   0x00000000      /* disabled                     */
 179 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 180
 181 /*-----------------------------------------------------------------------
 182  * Start addresses for the final memory configuration
 183  * (Set up by the startup code)
 184  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 185  */
 186 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 187 #define CONFIG_SYS_FLASH_BASE           0xFFF80000
 188 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 189 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Monitor   */
 190 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserve 1024 kB for malloc() */
 191
 192 /*
 193  * For booting Linux, the board info and command line data
 194  * have to be in the first 8 MB of memory, since this is
 195  * the maximum mapped by the Linux kernel during initialization.
 196  */
 197 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 198 /*-----------------------------------------------------------------------
 199  * FLASH organization
 200  */
 201 #define CONFIG_SYS_UPDATE_FLASH_SIZE
 202 #define CONFIG_SYS_FLASH_PROTECTION
 203 #define CONFIG_SYS_FLASH_EMPTY_INFO
 204
 205 #define CONFIG_SYS_FLASH_CFI
 206 #define CONFIG_FLASH_CFI_DRIVER
 207
 208 #define CONFIG_FLASH_SHOW_PROGRESS      45
 209
 210 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 211 #define CONFIG_SYS_MAX_FLASH_SECT       256
 212
 213 /*
 214  * JFFS2 partitions
 215  *
 216  */
 217 /* No command line, one static partition, whole device */
 218 #undef CONFIG_CMD_MTDPARTS
 219 #define CONFIG_JFFS2_DEV                "nor0"
 220 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 221 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 222
 223 /* mtdparts command line support */
 224 /* Note: fake mtd_id used, no linux mtd map file */
 225 /*
 226 #define CONFIG_CMD_MTDPARTS
 227 #define MTDIDS_DEFAULT          "nor0=mip405-0"
 228 #define MTDPARTS_DEFAULT        "mtdparts=mip405-0:-(jffs2)"
 229 */
 230
 231 /*-----------------------------------------------------------------------
 232  * Logbuffer Configuration
 233  */
 234 #undef CONFIG_LOGBUFFER         /* supported but not enabled */
 235 /*-----------------------------------------------------------------------
 236  * Bootcountlimit Configuration
 237  */
 238 #undef CONFIG_BOOTCOUNT_LIMIT   /* supported but not enabled */
 239
 240 /*-----------------------------------------------------------------------
 241  * POST Configuration
 242  */
 243 #if 0 /* enable this if POST is desired (is supported but not enabled) */
 244 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY | \
 245                                  CONFIG_SYS_POST_CPU            | \
 246                                  CONFIG_SYS_POST_RTC            | \
 247                                  CONFIG_SYS_POST_I2C)
 248
 249 #endif
 250 /*
 251  * Init Memory Controller:
 252  */
 253 #define FLASH_MAX_SIZE          0x00800000              /* 8MByte max */
 254 #define FLASH_BASE_PRELIM       0xFF800000  /* open the flash CS */
 255 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 256 #define FLASH_SIZE_PRELIM        3  /* maximal flash FLASH size bank #0 */
 257
 258 #define CONFIG_BOARD_EARLY_INIT_F 1
 259 #define CONFIG_BOARD_EARLY_INIT_R
 260
 261 /* Peripheral Bus Mapping */
 262 #define PER_PLD_ADDR            0xF4000000 /* smallest window is 1MByte 0x10 0000*/
 263 #define PER_UART0_ADDR          0xF4100000 /* smallest window is 1MByte 0x10 0000*/
 264 #define PER_UART1_ADDR          0xF4200000 /* smallest window is 1MByte 0x10 0000*/
 265
 266 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
 267 #define CONFIG_PORT_ADDR        PER_PLD_ADDR + 5
 268
 269 /*-----------------------------------------------------------------------
 270  * Definitions for initial stack pointer and data area (in On Chip SRAM)
 271  */
 272 #define CONFIG_SYS_TEMP_STACK_OCM      1
 273 #define CONFIG_SYS_OCM_DATA_ADDR        0xF0000000
 274 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 275 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR        /* inside of On Chip SRAM    */
 276 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE        /* Size of On Chip SRAM        */
 277 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 278 /* reserve some memory for POST and BOOT limit info */
 279 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 32)
 280
 281 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
 282 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
 283 #endif
 284
 285 /***********************************************************************
 286  * External peripheral base address
 287  ***********************************************************************/
 288 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
 289
 290 /***********************************************************************
 291  * Last Stage Init
 292  ***********************************************************************/
 293 #define CONFIG_LAST_STAGE_INIT
 294 /************************************************************
 295  * Ethernet Stuff
 296  ***********************************************************/
 297 #define CONFIG_PPC4xx_EMAC
 298 #define CONFIG_MII              1       /* MII PHY management           */
 299 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 300 #define CONFIG_PHY_RESET_DELAY  300     /* Intel LXT971A needs this */
 301 #define CONFIG_PHY_CMD_DELAY    40      /* Intel LXT971A needs this */
 302 /************************************************************
 303  * RTC
 304  ***********************************************************/
 305 #define CONFIG_RTC_MC146818
 306 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 307
 308 /************************************************************
 309  * IDE/ATA stuff
 310  ************************************************************/
 311 #if defined(CONFIG_TARGET_MIP405T)
 312 #define CONFIG_SYS_IDE_MAXBUS           1   /* MIP405T has only one IDE bus     */
 313 #else
 314 #define CONFIG_SYS_IDE_MAXBUS           2   /* max. 2 IDE busses        */
 315 #endif
 316
 317 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 318
 319 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
 320 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x01F0          /* ide0 offste */
 321 #define CONFIG_SYS_ATA_IDE1_OFFSET      0x0170          /* ide1 offset */
 322 #define CONFIG_SYS_ATA_DATA_OFFSET      0               /* data reg offset      */
 323 #define CONFIG_SYS_ATA_REG_OFFSET       0               /* reg offset */
 324 #define CONFIG_SYS_ATA_ALT_OFFSET       0x200           /* alternate register offset */
 325
 326 #undef  CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
 327 #undef  CONFIG_IDE_LED         /* no led for ide supported     */
 328 #define CONFIG_IDE_RESET       /* reset for ide supported...    */
 329 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
 330 #define CONFIG_SUPPORT_VFAT
 331 /************************************************************
 332  * ATAPI support (experimental)
 333  ************************************************************/
 334 #define CONFIG_ATAPI                    /* enable ATAPI Support */
 335
 336 /************************************************************
 337  * DISK Partition support
 338  ************************************************************/
 339 #define CONFIG_DOS_PARTITION
 340 #define CONFIG_MAC_PARTITION
 341 #define CONFIG_ISO_PARTITION /* Experimental */
 342
 343 /************************************************************
 344  * Video support
 345  ************************************************************/
 346 #define CONFIG_VIDEO                    /*To enable video controller support */
 347 #define CONFIG_VIDEO_CT69000
 348 #define CONFIG_CFB_CONSOLE
 349 #define CONFIG_VIDEO_LOGO
 350 #define CONFIG_CONSOLE_EXTRA_INFO
 351 #define CONFIG_VGA_AS_SINGLE_DEVICE
 352 #define CONFIG_VIDEO_SW_CURSOR
 353 #undef CONFIG_VIDEO_ONBOARD
 354 /************************************************************
 355  * USB support EXPERIMENTAL
 356  ************************************************************/
 357 #if !defined(CONFIG_TARGET_MIP405T)
 358 #define CONFIG_USB_UHCI
 359 #define CONFIG_USB_KEYBOARD
 360
 361 /* Enable needed helper functions */
 362 #define CONFIG_SYS_STDIO_DEREGISTER             /* needs stdio_deregister */
 363 #endif
 364 /************************************************************
 365  * Debug support
 366  ************************************************************/
 367 #if defined(CONFIG_CMD_KGDB)
 368 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 369 #endif
 370
 371 /************************************************************
 372  * support BZIP2 compression
 373  ************************************************************/
 374 #define CONFIG_BZIP2            1
 375
 376 #endif  /* __CONFIG_H */