include/configs/MOUSSE.h

   1 /*
   2  * (C) Copyright 2000, 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2001
   6  * James F. Dougherty (jfd@cs.stanford.edu)
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /*
  12  *
  13  * Configuration settings for the MOUSSE board.
  14  * See also: http://www.vooha.com/
  15  *
  16  */
  17
  18 /* ------------------------------------------------------------------------- */
  19
  20 /*
  21  * board/config.h - configuration options, board specific
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC824X      1
  33 #define CONFIG_MPC8240      1
  34 #define CONFIG_MOUSSE       1
  35
  36 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  37 #define CONFIG_SYS_LDSCRIPT     "board/mousse/u-boot.lds"
  38
  39 #define CONFIG_SYS_ADDR_MAP_B      1
  40
  41 #define CONFIG_CONS_INDEX   1
  42 #define CONFIG_BAUDRATE     9600
  43 #if 1
  44 #define CONFIG_BOOTCOMMAND  "tftp 100000 vmlinux.img;bootm"    /* autoboot command */
  45 #else
  46 #define CONFIG_BOOTCOMMAND  "bootm ffe10000"
  47 #endif
  48 #define CONFIG_BOOTARGS      "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138"
  49 #define CONFIG_BOOTDELAY     3
  50
  51
  52 /*
  53  * BOOTP options
  54  */
  55 #define CONFIG_BOOTP_BOOTFILESIZE
  56 #define CONFIG_BOOTP_BOOTPATH
  57 #define CONFIG_BOOTP_GATEWAY
  58 #define CONFIG_BOOTP_HOSTNAME
  59
  60
  61 /*
  62  * Command line configuration.
  63  */
  64 #include <config_cmd_default.h>
  65
  66 #define CONFIG_CMD_ASKENV
  67 #define CONFIG_CMD_DATE
  68
  69
  70 #define CONFIG_ENV_OVERWRITE 1
  71 #define CONFIG_ETH_ADDR      "00:10:18:10:00:06"
  72
  73 #define CONFIG_DOS_PARTITION  1 /* MSDOS bootable partitiion support */
  74
  75 #include "../board/mousse/mousse.h"
  76
  77 /*
  78  * Miscellaneous configurable options
  79  */
  80 #undef CONFIG_SYS_LONGHELP                /* undef to save memory     */
  81 #define CONFIG_SYS_PROMPT      "=>"  /* Monitor Command Prompt   */
  82 #define CONFIG_SYS_CBSIZE      256        /* Console I/O Buffer Size  */
  83 #define CONFIG_SYS_PBSIZE      (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  84 #define CONFIG_SYS_MAXARGS     8           /* Max number of command args   */
  85
  86 #define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */
  87 #define CONFIG_SYS_LOAD_ADDR   0x00100000  /* Default load address         */
  88
  89 /*-----------------------------------------------------------------------
  90  * Start addresses for the final memory configuration
  91  * (Set up by the startup code)
  92  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  93  */
  94 #define CONFIG_SYS_SDRAM_BASE      0x00000000
  95
  96 #ifdef DEBUG
  97 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_SDRAM_BASE
  98 #else
  99 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_FLASH_BASE
 100 #endif
 101
 102 #ifdef DEBUG
 103 #define CONFIG_SYS_MONITOR_LEN     (4 << 20)    /* lots of mem ... */
 104 #else
 105 #define CONFIG_SYS_MONITOR_LEN     (512 << 10)  /* 512K PLCC bootrom */
 106 #endif
 107 #define CONFIG_SYS_MALLOC_LEN      (2*(4096 << 10))    /* 2*4096kB for malloc()  */
 108
 109 #define CONFIG_SYS_MEMTEST_START   0x00004000   /* memtest works on      */
 110 #define CONFIG_SYS_MEMTEST_END     0x02000000   /* 0 ... 32 MB in DRAM   */
 111
 112
 113 #define CONFIG_SYS_EUMB_ADDR       0xFC000000
 114
 115 #define CONFIG_SYS_ISA_MEM         0xFD000000
 116 #define CONFIG_SYS_ISA_IO          0xFE000000
 117
 118 #define CONFIG_SYS_FLASH_BASE      0xFFF00000
 119 #define CONFIG_SYS_FLASH_SIZE      ((uint)(512 * 1024))
 120 #define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 121 #define FLASH_BASE0_PRELIM  0xFFF00000  /* 512K PLCC FLASH/AM29F040*/
 122 #define FLASH_BASE0_SIZE    0x80000     /* 512K */
 123 #define FLASH_BASE1_PRELIM  0xFFE10000  /* AMD 29LV160DB
 124                                            1MB - 64K FLASH0 SEG =960K
 125                                            (size=0xf0000)*/
 126
 127 /*
 128  * NS16550 Configuration
 129  */
 130 #define CONFIG_SYS_NS16550
 131 #define CONFIG_SYS_NS16550_SERIAL
 132
 133 #define CONFIG_SYS_NS16550_REG_SIZE     1
 134
 135 #define CONFIG_SYS_NS16550_CLK          18432000
 136
 137 #define CONFIG_SYS_NS16550_COM1 0xFFE08080
 138
 139 /*-----------------------------------------------------------------------
 140  * Definitions for initial stack pointer and data area (in DPRAM)
 141  */
 142 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
 143 #define CONFIG_SYS_INIT_RAM_SIZE   0x2F00  /* Size of used area in DPRAM  */
 144 #define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 145 #define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET
 146
 147 /*
 148  * Low Level Configuration Settings
 149  * (address mappings, register initial values, etc.)
 150  * You should know what you are doing if you make changes here.
 151  * For the detail description refer to the MPC8240 user's manual.
 152  */
 153
 154 #define CONFIG_SYS_CLK_FREQ  33000000   /* external frequency to pll */
 155 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2
 156 #define CONFIG_SYS_HZ               1000
 157
 158 #define CONFIG_SYS_ETH_DEV_FN       0x00
 159 #define CONFIG_SYS_ETH_IOBASE       0x00104000
 160
 161
 162         /* Bit-field values for MCCR1.
 163          */
 164 #define CONFIG_SYS_ROMNAL          8
 165 #define CONFIG_SYS_ROMFAL          8
 166
 167         /* Bit-field values for MCCR2.
 168          */
 169 #define CONFIG_SYS_REFINT          0xf5     /* Refresh interval               */
 170
 171         /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 172          */
 173 #define CONFIG_SYS_BSTOPRE         0x79
 174
 175 #ifdef INCLUDE_ECC
 176 #define USE_ECC                         1
 177 #else /* INCLUDE_ECC */
 178 #define USE_ECC                         0
 179 #endif /* INCLUDE_ECC */
 180
 181
 182         /* Bit-field values for MCCR3.
 183          */
 184 #define CONFIG_SYS_REFREC          8       /* Refresh to activate interval   */
 185 #define CONFIG_SYS_RDLAT           (4+USE_ECC)   /* Data latancy from read command */
 186
 187         /* Bit-field values for MCCR4.
 188          */
 189 #define CONFIG_SYS_PRETOACT        3       /* Precharge to activate interval */
 190 #define CONFIG_SYS_ACTTOPRE        5       /* Activate to Precharge interval */
 191 #define CONFIG_SYS_SDMODE_CAS_LAT  3       /* SDMODE CAS latancy             */
 192 #define CONFIG_SYS_SDMODE_WRAP     0       /* SDMODE wrap type               */
 193 #define CONFIG_SYS_SDMODE_BURSTLEN 2       /* SDMODE Burst length            */
 194 #define CONFIG_SYS_ACTORW          2
 195 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER (1-USE_ECC)
 196
 197 /* Memory bank settings.
 198  * Only bits 20-29 are actually used from these vales to set the
 199  * start/end addresses. The upper two bits will always be 0, and the lower
 200  * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 201  * address. Refer to the MPC8240 book.
 202  */
 203 #define CONFIG_SYS_RAM_SIZE        0x04000000  /* 64MB */
 204
 205
 206 #define CONFIG_SYS_BANK0_START     0x00000000
 207 #define CONFIG_SYS_BANK0_END       (CONFIG_SYS_RAM_SIZE - 1)
 208 #define CONFIG_SYS_BANK0_ENABLE    1
 209 #define CONFIG_SYS_BANK1_START     0x3ff00000
 210 #define CONFIG_SYS_BANK1_END       0x3fffffff
 211 #define CONFIG_SYS_BANK1_ENABLE    0
 212 #define CONFIG_SYS_BANK2_START     0x3ff00000
 213 #define CONFIG_SYS_BANK2_END       0x3fffffff
 214 #define CONFIG_SYS_BANK2_ENABLE    0
 215 #define CONFIG_SYS_BANK3_START     0x3ff00000
 216 #define CONFIG_SYS_BANK3_END       0x3fffffff
 217 #define CONFIG_SYS_BANK3_ENABLE    0
 218 #define CONFIG_SYS_BANK4_START     0x3ff00000
 219 #define CONFIG_SYS_BANK4_END       0x3fffffff
 220 #define CONFIG_SYS_BANK4_ENABLE    0
 221 #define CONFIG_SYS_BANK5_START     0x3ff00000
 222 #define CONFIG_SYS_BANK5_END       0x3fffffff
 223 #define CONFIG_SYS_BANK5_ENABLE    0
 224 #define CONFIG_SYS_BANK6_START     0x3ff00000
 225 #define CONFIG_SYS_BANK6_END       0x3fffffff
 226 #define CONFIG_SYS_BANK6_ENABLE    0
 227 #define CONFIG_SYS_BANK7_START     0x3ff00000
 228 #define CONFIG_SYS_BANK7_END       0x3fffffff
 229 #define CONFIG_SYS_BANK7_ENABLE    0
 230
 231 #define CONFIG_SYS_ODCR            0x7f
 232
 233
 234 #define CONFIG_SYS_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory
 235                                     see 8240 book for details*/
 236 #define PCI_MEM_SPACE1_START    0x80000000
 237 #define PCI_MEM_SPACE2_START    0xfd000000
 238
 239 /* IBAT/DBAT Configuration */
 240 /* Ram: 64MB, starts at address-0, r/w instruction/data */
 241 #define CONFIG_SYS_IBAT0U      (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
 242 #define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 243 #define CONFIG_SYS_DBAT0U      CONFIG_SYS_IBAT0U
 244 #define CONFIG_SYS_DBAT0L      CONFIG_SYS_IBAT0L
 245
 246 /* MPLD/Port-X I/O Space : data and instruction read/write,  cache-inhibit */
 247 #define CONFIG_SYS_IBAT1U      (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
 248 #if 0
 249 #define CONFIG_SYS_IBAT1L      (PORTX_DEV_BASE | BATL_PP_10  | BATL_MEMCOHERENCE |\
 250                          BATL_WRITETHROUGH | BATL_CACHEINHIBIT)
 251 #else
 252 #define CONFIG_SYS_IBAT1L      (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT)
 253 #endif
 254 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 255 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 256
 257 /* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */
 258 #define CONFIG_SYS_IBAT2U       (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP)
 259 #define CONFIG_SYS_IBAT2L       (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT)
 260 #define CONFIG_SYS_DBAT2U      CONFIG_SYS_IBAT2U
 261 #define CONFIG_SYS_DBAT2L      CONFIG_SYS_IBAT2L
 262
 263 /* PCI Memory region 2: PCI Devices in 0xFD space */
 264 #define CONFIG_SYS_IBAT3U       (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP)
 265 #define CONFIG_SYS_IBAT3L       (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
 266 #define CONFIG_SYS_DBAT3U      CONFIG_SYS_IBAT3U
 267 #define CONFIG_SYS_DBAT3L      CONFIG_SYS_IBAT3L
 268
 269
 270 /*
 271  * For booting Linux, the board info and command line data
 272  * have to be in the first 8 MB of memory, since this is
 273  * the maximum mapped by the Linux kernel during initialization.
 274  */
 275 #define CONFIG_SYS_BOOTMAPSZ       (8 << 20)   /* Initial Memory map for Linux */
 276
 277 /*-----------------------------------------------------------------------
 278  * FLASH organization
 279  */
 280 #define CONFIG_SYS_MAX_FLASH_BANKS     3       /* Max number of flash banks         */
 281 #define CONFIG_SYS_MAX_FLASH_SECT      64      /* Max number of sectors in one bank */
 282
 283 #define CONFIG_SYS_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)   */
 284 #define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)   */
 285
 286 #if 0
 287 #define CONFIG_ENV_IS_IN_FLASH      1
 288 #define CONFIG_ENV_OFFSET          0x8000  /* Offset of the Environment Sector  */
 289 #define CONFIG_ENV_SIZE            0x4000  /* Size of the Environment Sector    */
 290 #else
 291 #define CONFIG_ENV_IS_IN_NVRAM          1
 292 #define CONFIG_ENV_ADDR            NV_OFF_U_BOOT_ADDR /* PortX NVM Free addr*/
 293 #define CONFIG_ENV_OFFSET          CONFIG_ENV_ADDR
 294 #define CONFIG_ENV_SIZE            NV_U_BOOT_ENV_SIZE /* 2K */
 295 #endif
 296 /*-----------------------------------------------------------------------
 297  * Cache Configuration
 298  */
 299 #define CONFIG_SYS_CACHELINE_SIZE  16
 300
 301 /* Localizations */
 302 #if 0
 303 #define CONFIG_ETHADDR          0:0:0:0:1:d
 304 #define CONFIG_IPADDR           172.16.40.113
 305 #define CONFIG_SERVERIP         172.16.40.111
 306 #else
 307 #define CONFIG_ETHADDR          0:0:0:0:1:d
 308 #define CONFIG_IPADDR           209.128.93.138
 309 #define CONFIG_SERVERIP         209.128.93.133
 310 #endif
 311
 312 /*-----------------------------------------------------------------------
 313  * PCI stuff
 314  *-----------------------------------------------------------------------
 315  */
 316 #define CONFIG_PCI                      /* include pci support                  */
 317 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 318 #undef CONFIG_PCI_PNP
 319
 320
 321 #define CONFIG_TULIP
 322
 323 #endif  /* __CONFIG_H */