include/configs/MPC8260ADS.h

   1 /*
   2  * (C) Copyright 2001
   3  * Stuart Hughes <stuarth@lineo.com>
   4  * This file is based on similar values for other boards found in other
   5  * U-Boot config files, and some that I found in the mpc8260ads manual.
   6  *
   7  * Note: my board is a PILOT rev.
   8  * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
   9  *
  10  * (C) Copyright 2003-2004 Arabella Software Ltd.
  11  * Yuli Barcohen <yuli@arabellasw.com>
  12  * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
  13  * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
  14  * Ported to MPC8272ADS board.
  15  *
  16  * Copyright (c) 2005 MontaVista Software, Inc.
  17  * Vitaly Bordug <vbordug@ru.mvista.com>
  18  * Added support for PCI bridge on MPC8272ADS
  19  *
  20  * See file CREDITS for list of people who contributed to this
  21  * project.
  22  *
  23  * This program is free software; you can redistribute it and/or
  24  * modify it under the terms of the GNU General Public License as
  25  * published by the Free Software Foundation; either version 2 of
  26  * the License, or (at your option) any later version.
  27  *
  28  * This program is distributed in the hope that it will be useful,
  29  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  30  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  31  * GNU General Public License for more details.
  32  *
  33  * You should have received a copy of the GNU General Public License
  34  * along with this program; if not, write to the Free Software
  35  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  36  * MA 02111-1307 USA
  37  */
  38
  39 #ifndef __CONFIG_H
  40 #define __CONFIG_H
  41
  42 /*
  43  * High Level Configuration Options
  44  * (easy to change)
  45  */
  46
  47 #define CONFIG_MPC8260ADS       1       /* Motorola PQ2 ADS family board */
  48
  49 #define CONFIG_CPM2             1       /* Has a CPM2 */
  50
  51 /*
  52  * Figure out if we are booting low via flash HRCW or high via the BCSR.
  53  */
  54 #if (TEXT_BASE != 0xFFF00000)           /* Boot low (flash HRCW) */
  55 #   define CONFIG_SYS_LOWBOOT           1
  56 #endif
  57
  58 /* ADS flavours */
  59 #define CONFIG_SYS_8260ADS              1       /* MPC8260ADS */
  60 #define CONFIG_SYS_8266ADS              2       /* MPC8266ADS */
  61 #define CONFIG_SYS_PQ2FADS              3       /* PQ2FADS-ZU or PQ2FADS-VR */
  62 #define CONFIG_SYS_8272ADS              4       /* MPC8272ADS */
  63
  64 #ifndef CONFIG_ADSTYPE
  65 #define CONFIG_ADSTYPE          CONFIG_SYS_8260ADS
  66 #endif /* CONFIG_ADSTYPE */
  67
  68 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
  69 #define CONFIG_MPC8272          1
  70 #else
  71 #define CONFIG_MPC8260          1
  72 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
  73
  74 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  75
  76 /* allow serial and ethaddr to be overwritten */
  77 #define CONFIG_ENV_OVERWRITE
  78
  79 /*
  80  * select serial console configuration
  81  *
  82  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  83  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  84  * for SCC).
  85  *
  86  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  87  * defined elsewhere (for example, on the cogent platform, there are serial
  88  * ports on the motherboard which are used for the serial console - see
  89  * cogent/cma101/serial.[ch]).
  90  */
  91 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  92 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  93 #undef  CONFIG_CONS_NONE                /* define if console on something else */
  94 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  95
  96 /*
  97  * select ethernet configuration
  98  *
  99  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 100  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 101  * for FCC)
 102  *
 103  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 104  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 105  */
 106 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC   */
 107 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC   */
 108 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 109
 110 #ifdef CONFIG_ETHER_ON_FCC
 111
 112 #define CONFIG_ETHER_INDEX      2       /* which SCC/FCC channel for ethernet */
 113
 114 #if   CONFIG_ETHER_INDEX == 1
 115
 116 # define CONFIG_SYS_PHY_ADDR            0
 117 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
 118 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
 119
 120 #elif CONFIG_ETHER_INDEX == 2
 121
 122 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS        /* RxCLK is CLK15, TxCLK is CLK16 */
 123 # define CONFIG_SYS_PHY_ADDR            3
 124 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
 125 #else                                   /* RxCLK is CLK13, TxCLK is CLK14 */
 126 # define CONFIG_SYS_PHY_ADDR            0
 127 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 128 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
 129
 130 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 131
 132 #endif  /* CONFIG_ETHER_INDEX */
 133
 134 #define CONFIG_SYS_CPMFCR_RAMTYPE       0               /* BDs and buffers on 60x bus */
 135 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)  /* Full duplex */
 136
 137 #define CONFIG_MII                      /* MII PHY management           */
 138 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 139 /*
 140  * GPIO pins used for bit-banged MII communications
 141  */
 142 #define MDIO_PORT       2               /* Port C */
 143
 144 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 145 #define CONFIG_SYS_MDIO_PIN     0x00002000      /* PC18 */
 146 #define CONFIG_SYS_MDC_PIN      0x00001000      /* PC19 */
 147 #else
 148 #define CONFIG_SYS_MDIO_PIN     0x00400000      /* PC9  */
 149 #define CONFIG_SYS_MDC_PIN      0x00200000      /* PC10 */
 150 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
 151
 152 #define MDIO_ACTIVE     (iop->pdir |=  CONFIG_SYS_MDIO_PIN)
 153 #define MDIO_TRISTATE   (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
 154 #define MDIO_READ       ((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 155
 156 #define MDIO(bit)       if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
 157                         else    iop->pdat &= ~CONFIG_SYS_MDIO_PIN
 158
 159 #define MDC(bit)        if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
 160                         else    iop->pdat &= ~CONFIG_SYS_MDC_PIN
 161
 162 #define MIIDELAY        udelay(1)
 163
 164 #endif /* CONFIG_ETHER_ON_FCC */
 165
 166 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
 167 #undef CONFIG_SPD_EEPROM        /* On new boards, SDRAM is soldered */
 168 #else
 169 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 170 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address  */
 171 #define CONFIG_SYS_I2C_SLAVE            0x7F
 172
 173 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
 174 #define CONFIG_SPD_ADDR         0x50
 175 #endif
 176 #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
 177
 178 /*PCI*/
 179 #ifdef CONFIG_MPC8272
 180 #define CONFIG_PCI
 181 #define CONFIG_PCI_PNP
 182 #define CONFIG_PCI_BOOTDELAY 0
 183 #define CONFIG_PCI_SCAN_SHOW
 184 #endif
 185
 186 #ifndef CONFIG_SDRAM_PBI
 187 #define CONFIG_SDRAM_PBI        0 /* By default, use bank-based interleaving */
 188 #endif
 189
 190 #ifndef CONFIG_8260_CLKIN
 191 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
 192 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
 193 #else
 194 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
 195 #endif
 196 #endif
 197
 198 #define CONFIG_BAUDRATE         115200
 199
 200 #define CONFIG_OF_LIBFDT        1
 201 #define CONFIG_OF_BOARD_SETUP   1
 202 #if defined(CONFIG_OF_LIBFDT)
 203 #define OF_CPU                  "cpu@0"
 204 #define OF_TBCLK                (bd->bi_busfreq / 4)
 205 #endif
 206
 207 /*
 208  * BOOTP options
 209  */
 210 #define CONFIG_BOOTP_BOOTFILESIZE
 211 #define CONFIG_BOOTP_BOOTPATH
 212 #define CONFIG_BOOTP_GATEWAY
 213 #define CONFIG_BOOTP_HOSTNAME
 214
 215
 216 /*
 217  * Command line configuration.
 218  */
 219 #include <config_cmd_default.h>
 220
 221 #define CONFIG_CMD_ASKENV
 222 #define CONFIG_CMD_CACHE
 223 #define CONFIG_CMD_CDP
 224 #define CONFIG_CMD_DHCP
 225 #define CONFIG_CMD_DIAG
 226 #define CONFIG_CMD_I2C
 227 #define CONFIG_CMD_IMMAP
 228 #define CONFIG_CMD_IRQ
 229 #define CONFIG_CMD_JFFS2
 230 #define CONFIG_CMD_MII
 231 #define CONFIG_CMD_PCI
 232 #define CONFIG_CMD_PING
 233 #define CONFIG_CMD_PORTIO
 234 #define CONFIG_CMD_REGINFO
 235 #define CONFIG_CMD_SAVES
 236 #define CONFIG_CMD_SDRAM
 237
 238 #undef CONFIG_CMD_XIMG
 239
 240 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 241     #undef CONFIG_CMD_SDRAM
 242     #undef CONFIG_CMD_I2C
 243
 244 #elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
 245     #undef CONFIG_CMD_SDRAM
 246     #undef CONFIG_CMD_I2C
 247     #undef CONFIG_CMD_PCI
 248
 249 #else
 250     #undef CONFIG_CMD_PCI
 251
 252 #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
 253
 254
 255 #define CONFIG_BOOTDELAY        5               /* autoboot after 5 seconds */
 256 #define CONFIG_BOOTCOMMAND      "bootm fff80000"        /* autoboot command */
 257 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2"
 258
 259 #if defined(CONFIG_CMD_KGDB)
 260 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 261 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 262 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 263 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 264 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 265 #endif
 266
 267 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 268 #undef  CONFIG_WATCHDOG /* disable platform specific watchdog */
 269
 270 /*
 271  * Miscellaneous configurable options
 272  */
 273 #define CONFIG_SYS_HUSH_PARSER
 274 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 275 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 276 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt   */
 277 #if defined(CONFIG_CMD_KGDB)
 278 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size  */
 279 #else
 280 #define CONFIG_SYS_CBSIZE       256                     /* Console I/O Buffer Size  */
 281 #endif
 282 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 283 #define CONFIG_SYS_MAXARGS      16                      /* max number of command args   */
 284 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 285
 286 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 287 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 288
 289 #define CONFIG_SYS_LOAD_ADDR            0x400000        /* default load address */
 290
 291 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 292
 293 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 294
 295 #define CONFIG_SYS_FLASH_BASE           0xff800000
 296 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 297 #define CONFIG_SYS_MAX_FLASH_SECT       32      /* max num of sects on one chip */
 298 #define CONFIG_SYS_FLASH_SIZE           8
 299 #define CONFIG_SYS_FLASH_ERASE_TOUT     8000    /* Timeout for Flash Erase (in ms)    */
 300 #define CONFIG_SYS_FLASH_WRITE_TOUT     5       /* Timeout for Flash Write (in ms)    */
 301 #define CONFIG_SYS_FLASH_LOCK_TOUT      5       /* Timeout for Flash Set Lock Bit (in ms) */
 302 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    10000   /* Timeout for Flash Clear Lock Bits (in ms) */
 303 #define CONFIG_SYS_FLASH_PROTECTION             /* "Real" (hardware) sectors protection */
 304
 305 /*
 306  * JFFS2 partitions
 307  *
 308  * Note: fake mtd_id used, no linux mtd map file
 309  */
 310 #define MTDIDS_DEFAULT          "nor0=mpc8260ads-0"
 311 #define MTDPARTS_DEFAULT        "mtdparts=mpc8260ads-0:-@1m(jffs2)"
 312 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
 313
 314 /* this is stuff came out of the Motorola docs */
 315 #ifndef CONFIG_SYS_LOWBOOT
 316 #define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
 317 #endif
 318
 319 #define CONFIG_SYS_IMMR         0xF0000000
 320 #define CONFIG_SYS_BCSR         0xF4500000
 321 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 322 #define CONFIG_SYS_PCI_INT              0xF8200000
 323 #endif
 324 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 325 #define CONFIG_SYS_LSDRAM_BASE          0xFD000000
 326
 327 #define RS232EN_1               0x02000002
 328 #define RS232EN_2               0x01000001
 329 #define FETHIEN1                0x08000008
 330 #define FETH1_RST               0x04000004
 331 #define FETHIEN2                0x10000000
 332 #define FETH2_RST               0x08000000
 333 #define BCSR_PCI_MODE           0x01000000
 334
 335 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 336 #define CONFIG_SYS_INIT_RAM_END 0x2000  /* End of used area in DPRAM    */
 337 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
 338 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 339 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 340
 341 #ifdef CONFIG_SYS_LOWBOOT
 342 /* PQ2FADS flash HRCW = 0x0EB4B645 */
 343 #define CONFIG_SYS_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )                        |\
 344                             ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 )    |\
 345                             ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
 346                             ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )             \
 347                         )
 348 #else
 349 /* PQ2FADS BCSR HRCW = 0x0CB23645 */
 350 #define CONFIG_SYS_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )                        |\
 351                             ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 )    |\
 352                             ( HRCW_BMS | HRCW_APPC10 )                      |\
 353                             ( HRCW_MODCK_H0101 )                             \
 354                         )
 355 #endif
 356 /* no slaves */
 357 #define CONFIG_SYS_HRCW_SLAVE1 0
 358 #define CONFIG_SYS_HRCW_SLAVE2 0
 359 #define CONFIG_SYS_HRCW_SLAVE3 0
 360 #define CONFIG_SYS_HRCW_SLAVE4 0
 361 #define CONFIG_SYS_HRCW_SLAVE5 0
 362 #define CONFIG_SYS_HRCW_SLAVE6 0
 363 #define CONFIG_SYS_HRCW_SLAVE7 0
 364
 365 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 366 #define BOOTFLAG_WARM   0x02    /* Software reboot           */
 367
 368 #define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 369 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 370 #   define CONFIG_SYS_RAMBOOT
 371 #endif
 372
 373 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 374 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 375
 376 #ifdef CONFIG_BZIP2
 377 #define CONFIG_SYS_MALLOC_LEN           (4096 << 10)    /* Reserve 4 MB for malloc()    */
 378 #else
 379 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 KB for malloc()  */
 380 #endif /* CONFIG_BZIP2 */
 381
 382 #ifndef CONFIG_SYS_RAMBOOT
 383 #  define CONFIG_ENV_IS_IN_FLASH        1
 384 #  define CONFIG_ENV_SECT_SIZE  0x40000
 385 #  define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
 386 #else
 387 #  define CONFIG_ENV_IS_IN_NVRAM        1
 388 #  define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 389 #  define CONFIG_ENV_SIZE               0x200
 390 #endif /* CONFIG_SYS_RAMBOOT */
 391
 392 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU */
 393 #if defined(CONFIG_CMD_KGDB)
 394 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 395 #endif
 396
 397 #define CONFIG_SYS_HID0_INIT            0
 398 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE )
 399
 400 #define CONFIG_SYS_HID2         0
 401
 402 #define CONFIG_SYS_SYPCR                0xFFFFFFC3
 403 #define CONFIG_SYS_BCR                  0x100C0000
 404 #define CONFIG_SYS_SIUMCR               0x0A200000
 405 #define CONFIG_SYS_SCCR         SCCR_DFBRG01
 406 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | 0x00001801)
 407 #define CONFIG_SYS_OR0_PRELIM           0xFF800876
 408 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR | 0x00001801)
 409 #define CONFIG_SYS_OR1_PRELIM           0xFFFF8010
 410
 411 /*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
 412
 413 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 414 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_PCI_INT | 0x1801)   /* PCI interrupt controller */
 415 #define CONFIG_SYS_OR3_PRELIM   0xFFFF8010
 416 #endif
 417
 418 #define CONFIG_SYS_RMR                  RMR_CSRE
 419 #define CONFIG_SYS_TMCNTSC              (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 420 #define CONFIG_SYS_PISCR                (PISCR_PS|PISCR_PTF|PISCR_PTE)
 421 #define CONFIG_SYS_RCCR         0
 422
 423 #if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS)
 424 #undef CONFIG_SYS_LSDRAM_BASE           /* No local bus SDRAM on these boards */
 425 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */
 426
 427 #if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
 428 #define CONFIG_SYS_OR2                  0xFE002EC0
 429 #define CONFIG_SYS_PSDMR                0x824B36A3
 430 #define CONFIG_SYS_PSRT         0x13
 431 #define CONFIG_SYS_LSDMR                0x828737A3
 432 #define CONFIG_SYS_LSRT         0x13
 433 #define CONFIG_SYS_MPTPR                0x2800
 434 #elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 435 #define CONFIG_SYS_OR2                  0xFC002CC0
 436 #define CONFIG_SYS_PSDMR                0x834E24A3
 437 #define CONFIG_SYS_PSRT         0x13
 438 #define CONFIG_SYS_MPTPR                0x2800
 439 #else
 440 #define CONFIG_SYS_OR2                  0xFF000CA0
 441 #define CONFIG_SYS_PSDMR                0x016EB452
 442 #define CONFIG_SYS_PSRT         0x21
 443 #define CONFIG_SYS_LSDMR                0x0086A522
 444 #define CONFIG_SYS_LSRT         0x21
 445 #define CONFIG_SYS_MPTPR                0x1900
 446 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
 447
 448 #define CONFIG_SYS_RESET_ADDRESS        0x04400000
 449
 450 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 451
 452 /* PCI Memory map (if different from default map */
 453 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE           /* Local base */
 454 #define CONFIG_SYS_PCI_SLV_MEM_BUS              0x00000000              /* PCI base */
 455 #define CONFIG_SYS_PICMR0_MASK_ATTRIB   (PICMR_MASK_512MB | PICMR_ENABLE | \
 456                                  PICMR_PREFETCH_EN)
 457
 458 /*
 459  * These are the windows that allow the CPU to access PCI address space.
 460  * All three PCI master windows, which allow the CPU to access PCI
 461  * prefetch, non prefetch, and IO space (see below), must all fit within
 462  * these windows.
 463  */
 464
 465 /*
 466  * Master window that allows the CPU to access PCI Memory (prefetch).
 467  * This window will be setup with the second set of Outbound ATU registers
 468  * in the bridge.
 469  */
 470
 471 #define CONFIG_SYS_PCI_MSTR_MEM_LOCAL   0x80000000          /* Local base */
 472 #define CONFIG_SYS_PCI_MSTR_MEM_BUS     0x80000000          /* PCI base   */
 473 #define CONFIG_SYS_CPU_PCI_MEM_START    PCI_MSTR_MEM_LOCAL
 474 #define CONFIG_SYS_PCI_MSTR_MEM_SIZE    0x20000000          /* 512MB */
 475 #define CONFIG_SYS_POCMR0_MASK_ATTRIB   (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 476
 477 /*
 478  * Master window that allows the CPU to access PCI Memory (non-prefetch).
 479  * This window will be setup with the second set of Outbound ATU registers
 480  * in the bridge.
 481  */
 482
 483 #define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
 484 #define CONFIG_SYS_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
 485 #define CONFIG_SYS_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
 486 #define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
 487 #define CONFIG_SYS_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
 488
 489 /*
 490  * Master window that allows the CPU to access PCI IO space.
 491  * This window will be setup with the first set of Outbound ATU registers
 492  * in the bridge.
 493  */
 494
 495 #define CONFIG_SYS_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
 496 #define CONFIG_SYS_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
 497 #define CONFIG_SYS_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
 498 #define CONFIG_SYS_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
 499 #define CONFIG_SYS_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
 500
 501
 502 /* PCIBR0 - for PCI IO*/
 503 #define CONFIG_SYS_PCI_MSTR0_LOCAL              CONFIG_SYS_PCI_MSTR_IO_LOCAL            /* Local base */
 504 #define CONFIG_SYS_PCIMSK0_MASK         ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U)     /* Size of window */
 505 /* PCIBR1 - prefetch and non-prefetch regions joined together */
 506 #define CONFIG_SYS_PCI_MSTR1_LOCAL              CONFIG_SYS_PCI_MSTR_MEM_LOCAL
 507 #define CONFIG_SYS_PCIMSK1_MASK         ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
 508
 509 #endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
 510
 511 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 512 #define CONFIG_HAS_ETH1
 513 #endif
 514
 515 #endif /* __CONFIG_H */