include/configs/MPC8260ADS.h

   1 /*
   2  * (C) Copyright 2001
   3  * Stuart Hughes <stuarth@lineo.com>
   4  * This file is based on similar values for other boards found in other
   5  * U-Boot config files, and some that I found in the mpc8260ads manual.
   6  *
   7  * Note: my board is a PILOT rev.
   8  * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
   9  *
  10  * (C) Copyright 2003-2004 Arabella Software Ltd.
  11  * Yuli Barcohen <yuli@arabellasw.com>
  12  * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
  13  * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
  14  * Ported to MPC8272ADS board.
  15  *
  16  * Copyright (c) 2005 MontaVista Software, Inc.
  17  * Vitaly Bordug <vbordug@ru.mvista.com>
  18  * Added support for PCI bridge on MPC8272ADS
  19  *
  20  * See file CREDITS for list of people who contributed to this
  21  * project.
  22  *
  23  * This program is free software; you can redistribute it and/or
  24  * modify it under the terms of the GNU General Public License as
  25  * published by the Free Software Foundation; either version 2 of
  26  * the License, or (at your option) any later version.
  27  *
  28  * This program is distributed in the hope that it will be useful,
  29  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  30  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  31  * GNU General Public License for more details.
  32  *
  33  * You should have received a copy of the GNU General Public License
  34  * along with this program; if not, write to the Free Software
  35  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  36  * MA 02111-1307 USA
  37  */
  38
  39 #ifndef __CONFIG_H
  40 #define __CONFIG_H
  41
  42 /*
  43  * High Level Configuration Options
  44  * (easy to change)
  45  */
  46
  47 #define CONFIG_MPC8260ADS       1       /* Motorola PQ2 ADS family board */
  48
  49 #define CONFIG_CPM2             1       /* Has a CPM2 */
  50
  51 /*
  52  * Figure out if we are booting low via flash HRCW or high via the BCSR.
  53  */
  54 #if (TEXT_BASE != 0xFFF00000)           /* Boot low (flash HRCW) */
  55 #   define CFG_LOWBOOT          1
  56 #endif
  57
  58 /* ADS flavours */
  59 #define CFG_8260ADS             1       /* MPC8260ADS */
  60 #define CFG_8266ADS             2       /* MPC8266ADS */
  61 #define CFG_PQ2FADS             3       /* PQ2FADS-ZU or PQ2FADS-VR */
  62 #define CFG_8272ADS             4       /* MPC8272ADS */
  63
  64 #ifndef CONFIG_ADSTYPE
  65 #define CONFIG_ADSTYPE          CFG_8260ADS
  66 #endif /* CONFIG_ADSTYPE */
  67
  68 #if CONFIG_ADSTYPE == CFG_8272ADS
  69 #define CONFIG_MPC8272          1
  70 #else
  71 #define CONFIG_MPC8260          1
  72 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
  73
  74 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  75
  76 /* allow serial and ethaddr to be overwritten */
  77 #define CONFIG_ENV_OVERWRITE
  78
  79 /*
  80  * select serial console configuration
  81  *
  82  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  83  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  84  * for SCC).
  85  *
  86  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  87  * defined elsewhere (for example, on the cogent platform, there are serial
  88  * ports on the motherboard which are used for the serial console - see
  89  * cogent/cma101/serial.[ch]).
  90  */
  91 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  92 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  93 #undef  CONFIG_CONS_NONE                /* define if console on something else */
  94 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  95
  96 /*
  97  * select ethernet configuration
  98  *
  99  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 100  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 101  * for FCC)
 102  *
 103  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 104  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 105  */
 106 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC   */
 107 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC   */
 108 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 109
 110 #ifdef CONFIG_ETHER_ON_FCC
 111
 112 #define CONFIG_ETHER_INDEX      2       /* which SCC/FCC channel for ethernet */
 113
 114 #if   CONFIG_ETHER_INDEX == 1
 115
 116 # define CFG_PHY_ADDR           0
 117 # define CFG_CMXFCR_VALUE       (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
 118 # define CFG_CMXFCR_MASK        (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
 119
 120 #elif CONFIG_ETHER_INDEX == 2
 121
 122 #if CONFIG_ADSTYPE == CFG_8272ADS       /* RxCLK is CLK15, TxCLK is CLK16 */
 123 # define CFG_PHY_ADDR           3
 124 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
 125 #else                                   /* RxCLK is CLK13, TxCLK is CLK14 */
 126 # define CFG_PHY_ADDR           0
 127 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 128 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
 129
 130 # define CFG_CMXFCR_MASK        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 131
 132 #endif  /* CONFIG_ETHER_INDEX */
 133
 134 #define CFG_CPMFCR_RAMTYPE      0               /* BDs and buffers on 60x bus */
 135 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)  /* Full duplex */
 136
 137 #define CONFIG_MII                      /* MII PHY management           */
 138 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 139 /*
 140  * GPIO pins used for bit-banged MII communications
 141  */
 142 #define MDIO_PORT       2               /* Port C */
 143
 144 #if CONFIG_ADSTYPE == CFG_8272ADS
 145 #define CFG_MDIO_PIN    0x00002000      /* PC18 */
 146 #define CFG_MDC_PIN     0x00001000      /* PC19 */
 147 #else
 148 #define CFG_MDIO_PIN    0x00400000      /* PC9  */
 149 #define CFG_MDC_PIN     0x00200000      /* PC10 */
 150 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
 151
 152 #define MDIO_ACTIVE     (iop->pdir |=  CFG_MDIO_PIN)
 153 #define MDIO_TRISTATE   (iop->pdir &= ~CFG_MDIO_PIN)
 154 #define MDIO_READ       ((iop->pdat &  CFG_MDIO_PIN) != 0)
 155
 156 #define MDIO(bit)       if(bit) iop->pdat |=  CFG_MDIO_PIN; \
 157                         else    iop->pdat &= ~CFG_MDIO_PIN
 158
 159 #define MDC(bit)        if(bit) iop->pdat |=  CFG_MDC_PIN; \
 160                         else    iop->pdat &= ~CFG_MDC_PIN
 161
 162 #define MIIDELAY        udelay(1)
 163
 164 #endif /* CONFIG_ETHER_ON_FCC */
 165
 166 #if CONFIG_ADSTYPE >= CFG_PQ2FADS
 167 #undef CONFIG_SPD_EEPROM        /* On new boards, SDRAM is soldered */
 168 #else
 169 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 170 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address  */
 171 #define CFG_I2C_SLAVE           0x7F
 172
 173 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
 174 #define CONFIG_SPD_ADDR         0x50
 175 #endif
 176 #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
 177
 178 /*PCI*/
 179 #ifdef CONFIG_MPC8272
 180 #define CONFIG_PCI
 181 #define CONFIG_PCI_PNP
 182 #define CONFIG_PCI_BOOTDELAY 0
 183 #define CONFIG_PCI_SCAN_SHOW
 184 #endif
 185
 186 #ifndef CONFIG_SDRAM_PBI
 187 #define CONFIG_SDRAM_PBI        0 /* By default, use bank-based interleaving */
 188 #endif
 189
 190 #ifndef CONFIG_8260_CLKIN
 191 #if CONFIG_ADSTYPE >= CFG_PQ2FADS
 192 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
 193 #else
 194 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
 195 #endif
 196 #endif
 197
 198 #define CONFIG_BAUDRATE         115200
 199
 200 /*
 201  * BOOTP options
 202  */
 203 #define CONFIG_BOOTP_BOOTFILESIZE
 204 #define CONFIG_BOOTP_BOOTPATH
 205 #define CONFIG_BOOTP_GATEWAY
 206 #define CONFIG_BOOTP_HOSTNAME
 207
 208
 209 /*
 210  * Command line configuration.
 211  */
 212 #include <config_cmd_all.h>
 213
 214 #undef CONFIG_CMD_BEDBUG
 215 #undef CONFIG_CMD_BMP
 216 #undef CONFIG_CMD_BSP
 217 #undef CONFIG_CMD_DATE
 218 #undef CONFIG_CMD_DISPLAY
 219 #undef CONFIG_CMD_DOC
 220 #undef CONFIG_CMD_DTT
 221 #undef CONFIG_CMD_EEPROM
 222 #undef CONFIG_CMD_ELF
 223 #undef CONFIG_CMD_EXT2
 224 #undef CONFIG_CMD_FAT
 225 #undef CONFIG_CMD_FDC
 226 #undef CONFIG_CMD_FDOS
 227 #undef CONFIG_CMD_HWFLOW
 228 #undef CONFIG_CMD_IDE
 229 #undef CONFIG_CMD_KGDB
 230 #undef CONFIG_CMD_MFSL
 231 #undef CONFIG_CMD_MMC
 232 #undef CONFIG_CMD_NAND
 233 #undef CONFIG_CMD_PCMCIA
 234 #undef CONFIG_CMD_REISER
 235 #undef CONFIG_CMD_SCSI
 236 #undef CONFIG_CMD_SPI
 237 #undef CONFIG_CMD_SNTP
 238 #undef CONFIG_CMD_UNIVERSE
 239 #undef CONFIG_CMD_USB
 240 #undef CONFIG_CMD_VFD
 241 #undef CONFIG_CMD_XIMG
 242
 243 #if CONFIG_ADSTYPE == CFG_8272ADS
 244     #undef CONFIG_CMD_SDRAM
 245     #undef CONFIG_CMD_I2C
 246
 247 #elif CONFIG_ADSTYPE >= CFG_PQ2FADS
 248     #undef CONFIG_CMD_SDRAM
 249     #undef CONFIG_CMD_I2C
 250     #undef CONFIG_CMD_PCI
 251
 252 #else
 253     #undef CONFIG_CMD_PCI
 254
 255 #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
 256
 257
 258 #define CONFIG_BOOTDELAY        5               /* autoboot after 5 seconds */
 259 #define CONFIG_BOOTCOMMAND      "bootm fff80000"        /* autoboot command */
 260 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2"
 261
 262 #if defined(CONFIG_CMD_KGDB)
 263 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 264 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 265 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 266 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 267 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 268 #endif
 269
 270 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 271 #undef  CONFIG_WATCHDOG /* disable platform specific watchdog */
 272
 273 /*
 274  * Miscellaneous configurable options
 275  */
 276 #define CFG_HUSH_PARSER
 277 #define CFG_PROMPT_HUSH_PS2 "> "
 278 #define CFG_LONGHELP                    /* undef to save memory     */
 279 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt   */
 280 #if defined(CONFIG_CMD_KGDB)
 281 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size  */
 282 #else
 283 #define CFG_CBSIZE      256                     /* Console I/O Buffer Size  */
 284 #endif
 285 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 286 #define CFG_MAXARGS     16                      /* max number of command args   */
 287 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 288
 289 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 290 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 291
 292 #define CFG_LOAD_ADDR           0x400000        /* default load address */
 293
 294 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 295
 296 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 297
 298 #define CFG_FLASH_BASE          0xff800000
 299 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 300 #define CFG_MAX_FLASH_SECT      32      /* max num of sects on one chip */
 301 #define CFG_FLASH_SIZE          8
 302 #define CFG_FLASH_ERASE_TOUT    8000    /* Timeout for Flash Erase (in ms)    */
 303 #define CFG_FLASH_WRITE_TOUT    5       /* Timeout for Flash Write (in ms)    */
 304 #define CFG_FLASH_LOCK_TOUT     5       /* Timeout for Flash Set Lock Bit (in ms) */
 305 #define CFG_FLASH_UNLOCK_TOUT   10000   /* Timeout for Flash Clear Lock Bits (in ms) */
 306 #define CFG_FLASH_PROTECTION            /* "Real" (hardware) sectors protection */
 307
 308 /*
 309  * JFFS2 partitions
 310  *
 311  * Note: fake mtd_id used, no linux mtd map file
 312  */
 313 #define MTDIDS_DEFAULT          "nor0=mpc8260ads-0"
 314 #define MTDPARTS_DEFAULT        "mtdparts=mpc8260ads-0:-@1m(jffs2)"
 315 #define CFG_JFFS2_SORT_FRAGMENTS
 316
 317 /* this is stuff came out of the Motorola docs */
 318 #ifndef CFG_LOWBOOT
 319 #define CFG_DEFAULT_IMMR        0x0F010000
 320 #endif
 321
 322 #define CFG_IMMR                0xF0000000
 323 #define CFG_BCSR                0xF4500000
 324 #if CONFIG_ADSTYPE == CFG_8272ADS
 325 #define CFG_PCI_INT             0xF8200000
 326 #endif
 327 #define CFG_SDRAM_BASE          0x00000000
 328 #define CFG_LSDRAM_BASE         0xFD000000
 329
 330 #define RS232EN_1               0x02000002
 331 #define RS232EN_2               0x01000001
 332 #define FETHIEN1                0x08000008
 333 #define FETH1_RST               0x04000004
 334 #define FETHIEN2                0x10000000
 335 #define FETH2_RST               0x08000000
 336 #define BCSR_PCI_MODE           0x01000000
 337
 338 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 339 #define CFG_INIT_RAM_END        0x2000  /* End of used area in DPRAM    */
 340 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 341 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 342 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 343
 344 #ifdef CFG_LOWBOOT
 345 /* PQ2FADS flash HRCW = 0x0EB4B645 */
 346 #define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )                       |\
 347                             ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 )    |\
 348                             ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
 349                             ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )             \
 350                         )
 351 #else
 352 /* PQ2FADS BCSR HRCW = 0x0CB23645 */
 353 #define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )                       |\
 354                             ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 )    |\
 355                             ( HRCW_BMS | HRCW_APPC10 )                      |\
 356                             ( HRCW_MODCK_H0101 )                             \
 357                         )
 358 #endif
 359 /* no slaves */
 360 #define CFG_HRCW_SLAVE1 0
 361 #define CFG_HRCW_SLAVE2 0
 362 #define CFG_HRCW_SLAVE3 0
 363 #define CFG_HRCW_SLAVE4 0
 364 #define CFG_HRCW_SLAVE5 0
 365 #define CFG_HRCW_SLAVE6 0
 366 #define CFG_HRCW_SLAVE7 0
 367
 368 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 369 #define BOOTFLAG_WARM   0x02    /* Software reboot           */
 370
 371 #define CFG_MONITOR_BASE    TEXT_BASE
 372 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 373 #   define CFG_RAMBOOT
 374 #endif
 375
 376 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 377 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 378
 379 #ifdef CONFIG_BZIP2
 380 #define CFG_MALLOC_LEN          (4096 << 10)    /* Reserve 4 MB for malloc()    */
 381 #else
 382 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 KB for malloc()  */
 383 #endif /* CONFIG_BZIP2 */
 384
 385 #ifndef CFG_RAMBOOT
 386 #  define CFG_ENV_IS_IN_FLASH   1
 387 #  define CFG_ENV_SECT_SIZE     0x40000
 388 #  define CFG_ENV_ADDR          (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
 389 #else
 390 #  define CFG_ENV_IS_IN_NVRAM   1
 391 #  define CFG_ENV_ADDR          (CFG_MONITOR_BASE - 0x1000)
 392 #  define CFG_ENV_SIZE          0x200
 393 #endif /* CFG_RAMBOOT */
 394
 395 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 396 #if defined(CONFIG_CMD_KGDB)
 397 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 398 #endif
 399
 400 #define CFG_HID0_INIT           0
 401 #define CFG_HID0_FINAL          (HID0_ICE | HID0_IFEM | HID0_ABE )
 402
 403 #define CFG_HID2                0
 404
 405 #define CFG_SYPCR               0xFFFFFFC3
 406 #define CFG_BCR                 0x100C0000
 407 #define CFG_SIUMCR              0x0A200000
 408 #define CFG_SCCR                SCCR_DFBRG01
 409 #define CFG_BR0_PRELIM          (CFG_FLASH_BASE | 0x00001801)
 410 #define CFG_OR0_PRELIM          0xFF800876
 411 #define CFG_BR1_PRELIM          (CFG_BCSR | 0x00001801)
 412 #define CFG_OR1_PRELIM          0xFFFF8010
 413
 414 /*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
 415
 416 #if CONFIG_ADSTYPE == CFG_8272ADS
 417 #define CFG_BR3_PRELIM  (CFG_PCI_INT | 0x1801)  /* PCI interrupt controller */
 418 #define CFG_OR3_PRELIM  0xFFFF8010
 419 #endif
 420
 421 #define CFG_RMR                 RMR_CSRE
 422 #define CFG_TMCNTSC             (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 423 #define CFG_PISCR               (PISCR_PS|PISCR_PTF|PISCR_PTE)
 424 #define CFG_RCCR                0
 425
 426 #if (CONFIG_ADSTYPE == CFG_8266ADS) || (CONFIG_ADSTYPE == CFG_8272ADS)
 427 #undef CFG_LSDRAM_BASE          /* No local bus SDRAM on these boards */
 428 #endif /* CONFIG_ADSTYPE == CFG_8266ADS */
 429
 430 #if CONFIG_ADSTYPE == CFG_PQ2FADS
 431 #define CFG_OR2                 0xFE002EC0
 432 #define CFG_PSDMR               0x824B36A3
 433 #define CFG_PSRT                0x13
 434 #define CFG_LSDMR               0x828737A3
 435 #define CFG_LSRT                0x13
 436 #define CFG_MPTPR               0x2800
 437 #elif CONFIG_ADSTYPE == CFG_8272ADS
 438 #define CFG_OR2                 0xFC002CC0
 439 #define CFG_PSDMR               0x834E24A3
 440 #define CFG_PSRT                0x13
 441 #define CFG_MPTPR               0x2800
 442 #else
 443 #define CFG_OR2                 0xFF000CA0
 444 #define CFG_PSDMR               0x016EB452
 445 #define CFG_PSRT                0x21
 446 #define CFG_LSDMR               0x0086A522
 447 #define CFG_LSRT                0x21
 448 #define CFG_MPTPR               0x1900
 449 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 450
 451 #define CFG_RESET_ADDRESS       0x04400000
 452
 453 #if CONFIG_ADSTYPE == CFG_8272ADS
 454
 455 /* PCI Memory map (if different from default map */
 456 #define CFG_PCI_SLV_MEM_LOCAL   CFG_SDRAM_BASE          /* Local base */
 457 #define CFG_PCI_SLV_MEM_BUS             0x00000000              /* PCI base */
 458 #define CFG_PICMR0_MASK_ATTRIB  (PICMR_MASK_512MB | PICMR_ENABLE | \
 459                                  PICMR_PREFETCH_EN)
 460
 461 /*
 462  * These are the windows that allow the CPU to access PCI address space.
 463  * All three PCI master windows, which allow the CPU to access PCI
 464  * prefetch, non prefetch, and IO space (see below), must all fit within
 465  * these windows.
 466  */
 467
 468 /*
 469  * Master window that allows the CPU to access PCI Memory (prefetch).
 470  * This window will be setup with the second set of Outbound ATU registers
 471  * in the bridge.
 472  */
 473
 474 #define CFG_PCI_MSTR_MEM_LOCAL  0x80000000          /* Local base */
 475 #define CFG_PCI_MSTR_MEM_BUS    0x80000000          /* PCI base   */
 476 #define CFG_CPU_PCI_MEM_START   PCI_MSTR_MEM_LOCAL
 477 #define CFG_PCI_MSTR_MEM_SIZE   0x20000000          /* 512MB */
 478 #define CFG_POCMR0_MASK_ATTRIB  (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 479
 480 /*
 481  * Master window that allows the CPU to access PCI Memory (non-prefetch).
 482  * This window will be setup with the second set of Outbound ATU registers
 483  * in the bridge.
 484  */
 485
 486 #define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
 487 #define CFG_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
 488 #define CFG_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
 489 #define CFG_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
 490 #define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
 491
 492 /*
 493  * Master window that allows the CPU to access PCI IO space.
 494  * This window will be setup with the first set of Outbound ATU registers
 495  * in the bridge.
 496  */
 497
 498 #define CFG_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
 499 #define CFG_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
 500 #define CFG_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
 501 #define CFG_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
 502 #define CFG_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
 503
 504
 505 /* PCIBR0 - for PCI IO*/
 506 #define CFG_PCI_MSTR0_LOCAL             CFG_PCI_MSTR_IO_LOCAL           /* Local base */
 507 #define CFG_PCIMSK0_MASK                ~(CFG_PCI_MSTR_IO_SIZE - 1U)    /* Size of window */
 508 /* PCIBR1 - prefetch and non-prefetch regions joined together */
 509 #define CFG_PCI_MSTR1_LOCAL             CFG_PCI_MSTR_MEM_LOCAL
 510 #define CFG_PCIMSK1_MASK                ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)
 511
 512 #endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
 513
 514 #if CONFIG_ADSTYPE == CFG_8272ADS
 515 #define CONFIG_HAS_ETH1
 516 #endif
 517
 518 #endif /* __CONFIG_H */