include/configs/MPC8260ADS.h

   1 /*
   2  * (C) Copyright 2001
   3  * Stuart Hughes <stuarth@lineo.com>
   4  * This file is based on similar values for other boards found in other
   5  * U-Boot config files, and some that I found in the mpc8260ads manual.
   6  *
   7  * Note: my board is a PILOT rev.
   8  * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
   9  *
  10  * (C) Copyright 2003-2004 Arabella Software Ltd.
  11  * Yuli Barcohen <yuli@arabellasw.com>
  12  * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
  13  * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
  14  * Ported to MPC8272ADS board.
  15  *
  16  * Copyright (c) 2005 MontaVista Software, Inc.
  17  * Vitaly Bordug <vbordug@ru.mvista.com>
  18  * Added support for PCI bridge on MPC8272ADS
  19  *
  20  * Copyright (C) Freescale Semiconductor, Inc. 2006-2009.
  21  *
  22  * SPDX-License-Identifier:     GPL-2.0+
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 /*
  29  * High Level Configuration Options
  30  * (easy to change)
  31  */
  32
  33 #define CONFIG_MPC8260ADS       1       /* Motorola PQ2 ADS family board */
  34
  35 #ifndef CONFIG_SYS_TEXT_BASE
  36 #define CONFIG_SYS_TEXT_BASE    0xFFF00000      /* Standard: boot high */
  37 #endif
  38
  39 #define CONFIG_CPM2             1       /* Has a CPM2 */
  40
  41 /*
  42  * Figure out if we are booting low via flash HRCW or high via the BCSR.
  43  */
  44 #if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)                /* Boot low (flash HRCW) */
  45 #   define CONFIG_SYS_LOWBOOT           1
  46 #endif
  47
  48 /* ADS flavours */
  49 #define CONFIG_SYS_8260ADS              1       /* MPC8260ADS */
  50 #define CONFIG_SYS_8266ADS              2       /* MPC8266ADS */
  51 #define CONFIG_SYS_PQ2FADS              3       /* PQ2FADS-ZU or PQ2FADS-VR */
  52 #define CONFIG_SYS_8272ADS              4       /* MPC8272ADS */
  53
  54 #ifndef CONFIG_ADSTYPE
  55 #define CONFIG_ADSTYPE          CONFIG_SYS_8260ADS
  56 #endif /* CONFIG_ADSTYPE */
  57
  58 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
  59 #define CONFIG_MPC8272          1
  60 #elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
  61 /*
  62  * Actually MPC8275, but the code is littered with ifdefs that
  63  * apply to both, or which use this ifdef to assume board-specific
  64  * details. :-(
  65  */
  66 #define CONFIG_MPC8272          1
  67 #else
  68 #define CONFIG_MPC8260          1
  69 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
  70
  71 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  72 #define CONFIG_RESET_PHY_R      1       /* Call reset_phy()             */
  73
  74 /* allow serial and ethaddr to be overwritten */
  75 #define CONFIG_ENV_OVERWRITE
  76
  77 /*
  78  * select serial console configuration
  79  *
  80  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  81  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  82  * for SCC).
  83  *
  84  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  85  * defined elsewhere (for example, on the cogent platform, there are serial
  86  * ports on the motherboard which are used for the serial console - see
  87  * cogent/cma101/serial.[ch]).
  88  */
  89 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  90 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  91 #undef  CONFIG_CONS_NONE                /* define if console on something else */
  92 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  93
  94 /*
  95  * select ethernet configuration
  96  *
  97  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  98  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  99  * for FCC)
 100  *
 101  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 102  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 103  */
 104 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC   */
 105 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC   */
 106 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 107
 108 #ifdef CONFIG_ETHER_ON_FCC
 109
 110 #define CONFIG_ETHER_INDEX      2       /* which SCC/FCC channel for ethernet */
 111
 112 #if   CONFIG_ETHER_INDEX == 1
 113
 114 # define CONFIG_SYS_PHY_ADDR            0
 115 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
 116 # define CONFIG_SYS_CMXFCR_MASK1        (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
 117
 118 #elif CONFIG_ETHER_INDEX == 2
 119
 120 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS        /* RxCLK is CLK15, TxCLK is CLK16 */
 121 # define CONFIG_SYS_PHY_ADDR            3
 122 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
 123 #else                                   /* RxCLK is CLK13, TxCLK is CLK14 */
 124 # define CONFIG_SYS_PHY_ADDR            0
 125 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 126 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
 127
 128 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 129
 130 #endif  /* CONFIG_ETHER_INDEX */
 131
 132 #define CONFIG_SYS_CPMFCR_RAMTYPE       0               /* BDs and buffers on 60x bus */
 133 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)  /* Full duplex */
 134
 135 #define CONFIG_MII                      /* MII PHY management           */
 136 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 137 /*
 138  * GPIO pins used for bit-banged MII communications
 139  */
 140 #define MDIO_PORT       2               /* Port C */
 141 #define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 142                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 143 #define MDC_DECLARE     MDIO_DECLARE
 144
 145 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 146 #define CONFIG_SYS_MDIO_PIN     0x00002000      /* PC18 */
 147 #define CONFIG_SYS_MDC_PIN      0x00001000      /* PC19 */
 148 #else
 149 #define CONFIG_SYS_MDIO_PIN     0x00400000      /* PC9  */
 150 #define CONFIG_SYS_MDC_PIN      0x00200000      /* PC10 */
 151 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
 152
 153 #define MDIO_ACTIVE     (iop->pdir |=  CONFIG_SYS_MDIO_PIN)
 154 #define MDIO_TRISTATE   (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
 155 #define MDIO_READ       ((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 156
 157 #define MDIO(bit)       if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
 158                         else    iop->pdat &= ~CONFIG_SYS_MDIO_PIN
 159
 160 #define MDC(bit)        if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
 161                         else    iop->pdat &= ~CONFIG_SYS_MDC_PIN
 162
 163 #define MIIDELAY        udelay(1)
 164
 165 #endif /* CONFIG_ETHER_ON_FCC */
 166
 167 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
 168 #undef CONFIG_SPD_EEPROM        /* On new boards, SDRAM is soldered */
 169 #else
 170 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 171 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address  */
 172 #define CONFIG_SYS_I2C_SLAVE            0x7F
 173
 174 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
 175 #define CONFIG_SPD_ADDR         0x50
 176 #endif
 177 #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
 178
 179 /*PCI*/
 180 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
 181 #define CONFIG_PCI
 182 #define CONFIG_PCI_INDIRECT_BRIDGE
 183 #define CONFIG_PCI_PNP
 184 #define CONFIG_PCI_BOOTDELAY 0
 185 #define CONFIG_PCI_SCAN_SHOW
 186 #endif
 187
 188 #ifndef CONFIG_SDRAM_PBI
 189 #define CONFIG_SDRAM_PBI        0 /* By default, use bank-based interleaving */
 190 #endif
 191
 192 #ifndef CONFIG_8260_CLKIN
 193 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
 194 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
 195 #else
 196 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
 197 #endif
 198 #endif
 199
 200 #define CONFIG_BAUDRATE         115200
 201
 202 #define CONFIG_OF_LIBFDT        1
 203 #define CONFIG_OF_BOARD_SETUP   1
 204 #if defined(CONFIG_OF_LIBFDT)
 205 #define OF_TBCLK                (bd->bi_busfreq / 4)
 206 #endif
 207
 208 /*
 209  * BOOTP options
 210  */
 211 #define CONFIG_BOOTP_BOOTFILESIZE
 212 #define CONFIG_BOOTP_BOOTPATH
 213 #define CONFIG_BOOTP_GATEWAY
 214 #define CONFIG_BOOTP_HOSTNAME
 215
 216
 217 /*
 218  * Command line configuration.
 219  */
 220 #include <config_cmd_default.h>
 221
 222 #define CONFIG_CMD_ASKENV
 223 #define CONFIG_CMD_CACHE
 224 #define CONFIG_CMD_CDP
 225 #define CONFIG_CMD_DHCP
 226 #define CONFIG_CMD_DIAG
 227 #define CONFIG_CMD_I2C
 228 #define CONFIG_CMD_IMMAP
 229 #define CONFIG_CMD_IRQ
 230 #define CONFIG_CMD_JFFS2
 231 #define CONFIG_CMD_MII
 232 #define CONFIG_CMD_PCI
 233 #define CONFIG_CMD_PING
 234 #define CONFIG_CMD_PORTIO
 235 #define CONFIG_CMD_REGINFO
 236 #define CONFIG_CMD_SAVES
 237 #define CONFIG_CMD_SDRAM
 238
 239 #undef CONFIG_CMD_XIMG
 240
 241 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 242     #undef CONFIG_CMD_SDRAM
 243     #undef CONFIG_CMD_I2C
 244
 245 #elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
 246     #undef CONFIG_CMD_SDRAM
 247     #undef CONFIG_CMD_I2C
 248
 249 #else
 250     #undef CONFIG_CMD_PCI
 251
 252 #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
 253
 254
 255 #define CONFIG_BOOTDELAY        5               /* autoboot after 5 seconds */
 256 #define CONFIG_BOOTCOMMAND      "bootm fff80000"        /* autoboot command */
 257 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2"
 258
 259 #if defined(CONFIG_CMD_KGDB)
 260 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 261 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 262 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 263 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 264 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 265 #endif
 266
 267 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 268 #undef  CONFIG_WATCHDOG /* disable platform specific watchdog */
 269
 270 /*
 271  * Miscellaneous configurable options
 272  */
 273 #define CONFIG_SYS_HUSH_PARSER
 274 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 275 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt   */
 276 #if defined(CONFIG_CMD_KGDB)
 277 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size  */
 278 #else
 279 #define CONFIG_SYS_CBSIZE       256                     /* Console I/O Buffer Size  */
 280 #endif
 281 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 282 #define CONFIG_SYS_MAXARGS      16                      /* max number of command args   */
 283 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 284
 285 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 286 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 287
 288 #define CONFIG_SYS_LOAD_ADDR            0x400000        /* default load address */
 289
 290 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 291
 292 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 293
 294 #define CONFIG_SYS_FLASH_BASE           0xff800000
 295 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 296 #define CONFIG_SYS_MAX_FLASH_SECT       32      /* max num of sects on one chip */
 297 #define CONFIG_SYS_FLASH_SIZE           8
 298 #define CONFIG_SYS_FLASH_ERASE_TOUT     8000    /* Timeout for Flash Erase (in ms)    */
 299 #define CONFIG_SYS_FLASH_WRITE_TOUT     5       /* Timeout for Flash Write (in ms)    */
 300 #define CONFIG_SYS_FLASH_LOCK_TOUT      5       /* Timeout for Flash Set Lock Bit (in ms) */
 301 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    10000   /* Timeout for Flash Clear Lock Bits (in ms) */
 302 #define CONFIG_SYS_FLASH_PROTECTION             /* "Real" (hardware) sectors protection */
 303
 304 /*
 305  * JFFS2 partitions
 306  *
 307  * Note: fake mtd_id used, no linux mtd map file
 308  */
 309 #define MTDIDS_DEFAULT          "nor0=mpc8260ads-0"
 310 #define MTDPARTS_DEFAULT        "mtdparts=mpc8260ads-0:-@1m(jffs2)"
 311 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
 312
 313 /* this is stuff came out of the Motorola docs */
 314 #ifndef CONFIG_SYS_LOWBOOT
 315 #define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
 316 #endif
 317
 318 #define CONFIG_SYS_IMMR         0xF0000000
 319 #define CONFIG_SYS_BCSR         0xF4500000
 320 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
 321 #define CONFIG_SYS_PCI_INT              0xF8200000
 322 #endif
 323 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 324 #define CONFIG_SYS_LSDRAM_BASE          0xFD000000
 325
 326 #define RS232EN_1               0x02000002
 327 #define RS232EN_2               0x01000001
 328 #define FETHIEN1                0x08000008
 329 #define FETH1_RST               0x04000004
 330 #define FETHIEN2                0x10000000
 331 #define FETH2_RST               0x08000000
 332 #define BCSR_PCI_MODE           0x01000000
 333
 334 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 335 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in DPRAM   */
 336 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 337 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 338
 339 #ifdef CONFIG_SYS_LOWBOOT
 340 /* PQ2FADS flash HRCW = 0x0EB4B645 */
 341 #define CONFIG_SYS_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )                        |\
 342                             ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 )    |\
 343                             ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
 344                             ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )             \
 345                         )
 346 #else
 347 /* PQ2FADS BCSR HRCW = 0x0CB23645 */
 348 #define CONFIG_SYS_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )                        |\
 349                             ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 )    |\
 350                             ( HRCW_BMS | HRCW_APPC10 )                      |\
 351                             ( HRCW_MODCK_H0101 )                             \
 352                         )
 353 #endif
 354 /* no slaves */
 355 #define CONFIG_SYS_HRCW_SLAVE1 0
 356 #define CONFIG_SYS_HRCW_SLAVE2 0
 357 #define CONFIG_SYS_HRCW_SLAVE3 0
 358 #define CONFIG_SYS_HRCW_SLAVE4 0
 359 #define CONFIG_SYS_HRCW_SLAVE5 0
 360 #define CONFIG_SYS_HRCW_SLAVE6 0
 361 #define CONFIG_SYS_HRCW_SLAVE7 0
 362
 363 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 364
 365 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 366 #   define CONFIG_SYS_RAMBOOT
 367 #endif
 368
 369 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 370 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 371
 372 #ifdef CONFIG_BZIP2
 373 #define CONFIG_SYS_MALLOC_LEN           (4096 << 10)    /* Reserve 4 MB for malloc()    */
 374 #else
 375 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 KB for malloc()  */
 376 #endif /* CONFIG_BZIP2 */
 377
 378 #ifndef CONFIG_SYS_RAMBOOT
 379 #  define CONFIG_ENV_IS_IN_FLASH        1
 380 #  define CONFIG_ENV_SECT_SIZE  0x40000
 381 #  define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
 382 #else
 383 #  define CONFIG_ENV_IS_IN_NVRAM        1
 384 #  define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 385 #  define CONFIG_ENV_SIZE               0x200
 386 #endif /* CONFIG_SYS_RAMBOOT */
 387
 388 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU */
 389 #if defined(CONFIG_CMD_KGDB)
 390 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 391 #endif
 392
 393 #define CONFIG_SYS_HID0_INIT            0
 394 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE )
 395
 396 #define CONFIG_SYS_HID2         0
 397
 398 #define CONFIG_SYS_SYPCR                0xFFFFFFC3
 399 #define CONFIG_SYS_BCR                  0x100C0000
 400 #define CONFIG_SYS_SIUMCR               0x0A200000
 401 #define CONFIG_SYS_SCCR         SCCR_DFBRG01
 402 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | 0x00001801)
 403 #define CONFIG_SYS_OR0_PRELIM           0xFF800876
 404 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR | 0x00001801)
 405 #define CONFIG_SYS_OR1_PRELIM           0xFFFF8010
 406
 407 /*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
 408
 409 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 410 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_PCI_INT | 0x1801)   /* PCI interrupt controller */
 411 #define CONFIG_SYS_OR3_PRELIM   0xFFFF8010
 412 #elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
 413 #define CONFIG_SYS_BR8_PRELIM   (CONFIG_SYS_PCI_INT | 0x1801)   /* PCI interrupt controller */
 414 #define CONFIG_SYS_OR8_PRELIM   0xFFFF8010
 415 #endif
 416
 417 #define CONFIG_SYS_RMR                  RMR_CSRE
 418 #define CONFIG_SYS_TMCNTSC              (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 419 #define CONFIG_SYS_PISCR                (PISCR_PS|PISCR_PTF|PISCR_PTE)
 420 #define CONFIG_SYS_RCCR         0
 421
 422 #if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS)
 423 #undef CONFIG_SYS_LSDRAM_BASE           /* No local bus SDRAM on these boards */
 424 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */
 425
 426 #if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
 427 #define CONFIG_SYS_OR2                  0xFE002EC0
 428 #define CONFIG_SYS_PSDMR                0x824B36A3
 429 #define CONFIG_SYS_PSRT         0x13
 430 #define CONFIG_SYS_LSDMR                0x828737A3
 431 #define CONFIG_SYS_LSRT         0x13
 432 #define CONFIG_SYS_MPTPR                0x2800
 433 #elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 434 #define CONFIG_SYS_OR2                  0xFC002CC0
 435 #define CONFIG_SYS_PSDMR                0x834E24A3
 436 #define CONFIG_SYS_PSRT         0x13
 437 #define CONFIG_SYS_MPTPR                0x2800
 438 #else
 439 #define CONFIG_SYS_OR2                  0xFF000CA0
 440 #define CONFIG_SYS_PSDMR                0x016EB452
 441 #define CONFIG_SYS_PSRT         0x21
 442 #define CONFIG_SYS_LSDMR                0x0086A522
 443 #define CONFIG_SYS_LSRT         0x21
 444 #define CONFIG_SYS_MPTPR                0x1900
 445 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
 446
 447 #define CONFIG_SYS_RESET_ADDRESS        0x04400000
 448
 449 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
 450
 451 /* PCI Memory map (if different from default map */
 452 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE           /* Local base */
 453 #define CONFIG_SYS_PCI_SLV_MEM_BUS              0x00000000              /* PCI base */
 454 #define CONFIG_SYS_PICMR0_MASK_ATTRIB   (PICMR_MASK_512MB | PICMR_ENABLE | \
 455                                  PICMR_PREFETCH_EN)
 456
 457 /*
 458  * These are the windows that allow the CPU to access PCI address space.
 459  * All three PCI master windows, which allow the CPU to access PCI
 460  * prefetch, non prefetch, and IO space (see below), must all fit within
 461  * these windows.
 462  */
 463
 464 /*
 465  * Master window that allows the CPU to access PCI Memory (prefetch).
 466  * This window will be setup with the second set of Outbound ATU registers
 467  * in the bridge.
 468  */
 469
 470 #define CONFIG_SYS_PCI_MSTR_MEM_LOCAL   0x80000000          /* Local base */
 471 #define CONFIG_SYS_PCI_MSTR_MEM_BUS     0x80000000          /* PCI base   */
 472 #define CONFIG_SYS_CPU_PCI_MEM_START    PCI_MSTR_MEM_LOCAL
 473 #define CONFIG_SYS_PCI_MSTR_MEM_SIZE    0x20000000          /* 512MB */
 474 #define CONFIG_SYS_POCMR0_MASK_ATTRIB   (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 475
 476 /*
 477  * Master window that allows the CPU to access PCI Memory (non-prefetch).
 478  * This window will be setup with the second set of Outbound ATU registers
 479  * in the bridge.
 480  */
 481
 482 #define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
 483 #define CONFIG_SYS_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
 484 #define CONFIG_SYS_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
 485 #define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
 486 #define CONFIG_SYS_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
 487
 488 /*
 489  * Master window that allows the CPU to access PCI IO space.
 490  * This window will be setup with the first set of Outbound ATU registers
 491  * in the bridge.
 492  */
 493
 494 #define CONFIG_SYS_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
 495 #define CONFIG_SYS_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
 496 #define CONFIG_SYS_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
 497 #define CONFIG_SYS_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
 498 #define CONFIG_SYS_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
 499
 500
 501 /* PCIBR0 - for PCI IO*/
 502 #define CONFIG_SYS_PCI_MSTR0_LOCAL              CONFIG_SYS_PCI_MSTR_IO_LOCAL            /* Local base */
 503 #define CONFIG_SYS_PCIMSK0_MASK         ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U)     /* Size of window */
 504 /* PCIBR1 - prefetch and non-prefetch regions joined together */
 505 #define CONFIG_SYS_PCI_MSTR1_LOCAL              CONFIG_SYS_PCI_MSTR_MEM_LOCAL
 506 #define CONFIG_SYS_PCIMSK1_MASK         ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
 507
 508 #endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
 509
 510 #define CONFIG_HAS_ETH0
 511
 512 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 513 #define CONFIG_HAS_ETH1
 514 #endif
 515
 516 #define CONFIG_NETDEV eth0
 517 #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
 518
 519 #define CONFIG_EXTRA_ENV_SETTINGS \
 520         "netdev=" __stringify(CONFIG_NETDEV) "\0"                       \
 521         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 522                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 523                         " +$filesize; " \
 524                 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 525                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 526                         " $filesize; "  \
 527                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 528                         " +$filesize; " \
 529                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 530                         " $filesize\0"  \
 531         "fdtaddr=400000\0"                                              \
 532         "console=ttyCPM0\0"                                             \
 533         "setbootargs=setenv bootargs "                                  \
 534                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 535         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 536                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 537                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 538
 539 #define CONFIG_NFSBOOTCOMMAND                                           \
 540         "setenv rootdev /dev/nfs;"                                      \
 541         "run setipargs;"                                                \
 542         "tftp $loadaddr $bootfile;"                                     \
 543         "tftp $fdtaddr $fdtfile;"                                       \
 544         "bootm $loadaddr - $fdtaddr"
 545
 546 #define CONFIG_RAMBOOTCOMMAND                                           \
 547         "setenv rootdev /dev/ram;"                                      \
 548         "run setbootargs;"                                              \
 549         "tftp $ramdiskaddr $ramdiskfile;"                               \
 550         "tftp $loadaddr $bootfile;"                                     \
 551         "tftp $fdtaddr $fdtfile;"                                       \
 552         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 553
 554 #endif /* __CONFIG_H */