include/configs/MPC8266ADS.h

   1 /*
   2  * (C) Copyright 2001
   3  * Stuart Hughes <stuarth@lineo.com>
   4  * This file is based on similar values for other boards found in other
   5  * U-Boot config files, and some that I found in the mpc8260ads manual.
   6  *
   7  * Note: my board is a PILOT rev.
   8  * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /*
  30  * Config header file for a MPC8266ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm
  31  */
  32
  33 /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
  34    !!                                                                 !!
  35    !!  This configuration requires JP3 to be in position 1-2 to work  !!
  36    !!  To make it work for the default, the TEXT_BASE define in       !!
  37    !!  board/mpc8266ads/config.mk must be changed from 0xfe000000 to  !!
  38    !!  0xfff00000                                                     !!
  39    !!  The CFG_HRCW_MASTER define below must also be changed to match !!
  40    !!                                                                 !!
  41    !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
  42  */
  43
  44 #ifndef __CONFIG_H
  45 #define __CONFIG_H
  46
  47 /*
  48  * High Level Configuration Options
  49  * (easy to change)
  50  */
  51
  52 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
  53 #define CONFIG_MPC8266ADS       1       /* ...on motorola ads board */
  54
  55 #define CONFIG_BOARD_PRE_INIT   1       /* Call board_pre_init  */
  56
  57 /* allow serial and ethaddr to be overwritten */
  58 #define CONFIG_ENV_OVERWRITE
  59
  60 /*
  61  * select serial console configuration
  62  *
  63  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  64  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  65  * for SCC).
  66  *
  67  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  68  * defined elsewhere (for example, on the cogent platform, there are serial
  69  * ports on the motherboard which are used for the serial console - see
  70  * cogent/cma101/serial.[ch]).
  71  */
  72 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  73 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  74 #undef  CONFIG_CONS_NONE                /* define if console on something else */
  75 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  76
  77 /*
  78  * select ethernet configuration
  79  *
  80  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  81  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  82  * for FCC)
  83  *
  84  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  85  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
  86  * from CONFIG_COMMANDS to remove support for networking.
  87  */
  88 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC   */
  89 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC   */
  90 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  91 #define CONFIG_ETHER_INDEX      2       /* which channel for ether  */
  92 #define CONFIG_MII                      /* MII PHY management           */
  93 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
  94 /*
  95  * Port pins used for bit-banged MII communictions (if applicable).
  96  */
  97 #define MDIO_PORT       2       /* Port C */
  98 #define MDIO_ACTIVE     (iop->pdir |=  0x00400000)
  99 #define MDIO_TRISTATE   (iop->pdir &= ~0x00400000)
 100 #define MDIO_READ       ((iop->pdat &  0x00400000) != 0)
 101
 102 #define MDIO(bit)       if(bit) iop->pdat |=  0x00400000; \
 103                         else    iop->pdat &= ~0x00400000
 104
 105 #define MDC(bit)        if(bit) iop->pdat |=  0x00200000; \
 106                         else    iop->pdat &= ~0x00200000
 107
 108 #define MIIDELAY        udelay(1)
 109
 110 #if (CONFIG_ETHER_INDEX == 2)
 111
 112 /*
 113  * - Rx-CLK is CLK13
 114  * - Tx-CLK is CLK14
 115  * - Select bus for bd/buffers (see 28-13)
 116  * - Half duplex
 117  */
 118 # define CFG_CMXFCR_MASK        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 119 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 120 # define CFG_CPMFCR_RAMTYPE     0
 121 # define CFG_FCC_PSMR           (FCC_PSMR_FDE | FCC_PSMR_LPB)
 122
 123 #endif  /* CONFIG_ETHER_INDEX */
 124
 125 /* other options */
 126 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 127 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 128 #define CFG_I2C_SLAVE           0x7F
 129 #define CFG_I2C_EEPROM_ADDR_LEN 1
 130
 131 /* PCI */
 132 #define CONFIG_PCI
 133 #define CONFIG_PCI_PNP
 134 #define CONFIG_PCI_BOOTDELAY 0
 135 #undef CONFIG_PCI_SCAN_SHOW
 136
 137 /*-----------------------------------------------------------------------
 138  * Definitions for Serial Presence Detect EEPROM address
 139  * (to get SDRAM settings)
 140  */
 141 #define SPD_EEPROM_ADDRESS      0x50
 142
 143
 144 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
 145 #define CONFIG_BAUDRATE         115200
 146
 147
 148 #define CONFIG_COMMANDS         (CFG_CMD_ALL & ~( \
 149                                  CFG_CMD_BEDBUG | \
 150                                  CFG_CMD_BMP    | \
 151                                  CFG_CMD_BSP    | \
 152                                  CFG_CMD_DATE   | \
 153                                  CFG_CMD_DHCP   | \
 154                                  CFG_CMD_DOC    | \
 155                                  CFG_CMD_DTT    | \
 156                                  CFG_CMD_EEPROM | \
 157                                  CFG_CMD_ELF    | \
 158                                  CFG_CMD_FDC    | \
 159                                  CFG_CMD_FDOS   | \
 160                                  CFG_CMD_HWFLOW | \
 161                                  CFG_CMD_IDE    | \
 162                                  CFG_CMD_JFFS2  | \
 163                                  CFG_CMD_KGDB   | \
 164                                  CFG_CMD_MMC    | \
 165                                  CFG_CMD_NAND   | \
 166                                  CFG_CMD_PCMCIA | \
 167                                  CFG_CMD_SCSI   | \
 168                                  CFG_CMD_SPI    | \
 169                                  CFG_CMD_VFD    | \
 170                                  CFG_CMD_USB    ) )
 171
 172 /* Define a command string that is automatically executed when no character
 173  * is read on the console interface withing "Boot Delay" after reset.
 174  */
 175 #define CONFIG_BOOT_ROOT_INITRD 0       /* Use ram disk for the root file system */
 176 #define CONFIG_BOOT_ROOT_NFS    1       /* Use a NFS mounted root file system */
 177
 178 #if CONFIG_BOOT_ROOT_INITRD
 179 #define CONFIG_BOOTCOMMAND \
 180         "version;" \
 181         "echo;" \
 182         "bootp;" \
 183         "setenv bootargs root=/dev/ram0 rw " \
 184         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
 185         "bootm"
 186 #endif /* CONFIG_BOOT_ROOT_INITRD */
 187
 188 #if CONFIG_BOOT_ROOT_NFS
 189 #define CONFIG_BOOTCOMMAND \
 190         "version;" \
 191         "echo;" \
 192         "bootp;" \
 193         "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
 194         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
 195         "bootm"
 196 #endif /* CONFIG_BOOT_ROOT_NFS */
 197
 198 /* Add support for a few extra bootp options like:
 199  *      - File size
 200  *      - DNS
 201  */
 202 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | \
 203                                  CONFIG_BOOTP_BOOTFILESIZE | \
 204                                  CONFIG_BOOTP_DNS)
 205
 206 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 207 #include <cmd_confdefs.h>
 208
 209
 210 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 211
 212 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 213 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 214 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 215 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 216 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 217 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 218 #endif
 219
 220 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 221
 222 /*
 223  * Miscellaneous configurable options
 224  */
 225 #define CFG_LONGHELP                    /* undef to save memory     */
 226 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt   */
 227 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 228 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size  */
 229 #else
 230 #define CFG_CBSIZE      256                     /* Console I/O Buffer Size  */
 231 #endif
 232 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 233 #define CFG_MAXARGS     16                      /* max number of command args   */
 234 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 235
 236 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 237 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 238
 239 #undef CONFIG_CLOCKS_IN_MHZ             /* clocks passsed to Linux in MHz */
 240                                         /* for versions < 2.4.5-pre5    */
 241
 242 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 243
 244 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 245
 246 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 247
 248 #define CFG_FLASH_BASE          0xFE000000
 249 #define FLASH_BASE              0xFE000000
 250 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 251 #define CFG_MAX_FLASH_SECT      32      /* max num of sects on one chip */
 252 #define CFG_FLASH_SIZE          8
 253 #define CFG_FLASH_ERASE_TOUT    8000    /* Timeout for Flash Erase (in ms)    */
 254 #define CFG_FLASH_WRITE_TOUT    5       /* Timeout for Flash Write (in ms)    */
 255
 256 #undef  CFG_FLASH_CHECKSUM
 257
 258 /* this is stuff came out of the Motorola docs */
 259 /* Only change this if you also change the Hardware configuration Word */
 260 #define CFG_DEFAULT_IMMR        0x0F010000
 261
 262 /* Set IMMR to 0xF0000000 or above to boot Linux  */
 263 #define CFG_IMMR                0xF0000000
 264 #define CFG_BCSR                0xF8000000
 265 #define CFG_PCI_INT             0xF8200000      /* PCI interrupt controller */
 266
 267 /* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
 268  */
 269 /*#define CONFIG_VERY_BIG_RAM   1*/
 270
 271 /* What should be the base address of SDRAM DIMM and how big is
 272  * it (in Mbytes)?  This will normally auto-configure via the SPD.
 273 */
 274 #define CFG_SDRAM_BASE 0x00000000
 275 #define CFG_SDRAM_SIZE 16
 276
 277 #define SDRAM_SPD_ADDR 0x50
 278
 279
 280 /*-----------------------------------------------------------------------
 281  * BR2,BR3 - Base Register
 282  *     Ref: Section 10.3.1 on page 10-14
 283  * OR2,OR3 - Option Register
 284  *     Ref: Section 10.3.2 on page 10-16
 285  *-----------------------------------------------------------------------
 286  */
 287
 288 /* Bank 2,3 - SDRAM DIMM
 289  */
 290
 291 /* The BR2 is configured as follows:
 292  *
 293  *     - Base address of 0x00000000
 294  *     - 64 bit port size (60x bus only)
 295  *     - Data errors checking is disabled
 296  *     - Read and write access
 297  *     - SDRAM 60x bus
 298  *     - Access are handled by the memory controller according to MSEL
 299  *     - Not used for atomic operations
 300  *     - No data pipelining is done
 301  *     - Valid
 302  */
 303 #define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
 304                          BRx_PS_64                      |\
 305                          BRx_MS_SDRAM_P                 |\
 306                          BRx_V)
 307
 308 #define CFG_BR3_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
 309                          BRx_PS_64                      |\
 310                          BRx_MS_SDRAM_P                 |\
 311                          BRx_V)
 312
 313 /* With a 64 MB DIMM, the OR2 is configured as follows:
 314  *
 315  *     - 64 MB
 316  *     - 4 internal banks per device
 317  *     - Row start address bit is A8 with PSDMR[PBI] = 0
 318  *     - 12 row address lines
 319  *     - Back-to-back page mode
 320  *     - Internal bank interleaving within save device enabled
 321  */
 322 #if (CFG_SDRAM_SIZE == 64)
 323 #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM_SIZE)      |\
 324                          ORxS_BPD_4                     |\
 325                          ORxS_ROWST_PBI0_A8             |\
 326                          ORxS_NUMR_12)
 327 #elif (CFG_SDRAM_SIZE == 16)
 328 #define CFG_OR2_PRELIM  (0xFF000C80)
 329 #else
 330 #error "INVALID SDRAM CONFIGURATION"
 331 #endif
 332
 333 /*-----------------------------------------------------------------------
 334  * PSDMR - 60x Bus SDRAM Mode Register
 335  *     Ref: Section 10.3.3 on page 10-21
 336  *-----------------------------------------------------------------------
 337  */
 338
 339 #if (CFG_SDRAM_SIZE == 64)
 340 /* With a 64 MB DIMM, the PSDMR is configured as follows:
 341  *
 342  *     - Bank Based Interleaving,
 343  *     - Refresh Enable,
 344  *     - Address Multiplexing where A5 is output on A14 pin
 345  *       (A6 on A15, and so on),
 346  *     - use address pins A14-A16 as bank select,
 347  *     - A9 is output on SDA10 during an ACTIVATE command,
 348  *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
 349  *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 350  *       is 3 clocks,
 351  *     - earliest timing for READ/WRITE command after ACTIVATE command is
 352  *       2 clocks,
 353  *     - earliest timing for PRECHARGE after last data was read is 1 clock,
 354  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
 355  *     - CAS Latency is 2.
 356  */
 357 #define CFG_PSDMR       (PSDMR_RFEN           |\
 358                          PSDMR_SDAM_A14_IS_A5 |\
 359                          PSDMR_BSMA_A14_A16   |\
 360                          PSDMR_SDA10_PBI0_A9  |\
 361                          PSDMR_RFRC_7_CLK     |\
 362                          PSDMR_PRETOACT_3W    |\
 363                          PSDMR_ACTTORW_2W     |\
 364                          PSDMR_LDOTOPRE_1C    |\
 365                          PSDMR_WRC_1C         |\
 366                          PSDMR_CL_2)
 367 #elif (CFG_SDRAM_SIZE == 16)
 368 /* With a 16 MB DIMM, the PSDMR is configured as follows:
 369  *
 370  *   configuration parameters found in Motorola documentation
 371  */
 372 #define CFG_PSDMR       (0x016EB452)
 373 #else
 374 #error "INVALID SDRAM CONFIGURATION"
 375 #endif
 376
 377
 378 #define RS232EN_1               0x02000002
 379 #define RS232EN_2               0x01000001
 380 #define FETHIEN                 0x08000008
 381 #define FETH_RST                0x04000004
 382
 383 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 384 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 385 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 386 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 387 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 388
 389
 390 /* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2)  */
 391 /* 0x0EB2B645 */
 392 #define CFG_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP )                              |\
 393                          ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 )           |\
 394                          ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 )  |\
 395                          ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )                   \
 396                         )
 397
 398 /* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3)  */
 399 /* #define CFG_HRCW_MASTER 0x0cb23645 */
 400
 401 /* This value should actually be situated in the first 256 bytes of the FLASH
 402         which on the standard MPC8266ADS board is at address 0xFF800000
 403         The linker script places it at 0xFFF00000 instead.
 404
 405         It still works, however, as long as the ADS board jumper JP3 is set to
 406         position 2-3 so the board is using the BCSR as Hardware Configuration Word
 407
 408         If you want to use the one defined here instead, ust copy the first 256 bytes from
 409         0xfff00000 to 0xff800000  (for 8MB flash)
 410
 411         - Rune
 412
 413 */
 414
 415 /* no slaves */
 416 #define CFG_HRCW_SLAVE1 0
 417 #define CFG_HRCW_SLAVE2 0
 418 #define CFG_HRCW_SLAVE3 0
 419 #define CFG_HRCW_SLAVE4 0
 420 #define CFG_HRCW_SLAVE5 0
 421 #define CFG_HRCW_SLAVE6 0
 422 #define CFG_HRCW_SLAVE7 0
 423
 424 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 425 #define BOOTFLAG_WARM   0x02    /* Software reboot           */
 426
 427 #define CFG_MONITOR_BASE    TEXT_BASE
 428 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 429 #   define CFG_RAMBOOT
 430 #endif
 431
 432 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 433 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 434 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 435
 436 #ifndef CFG_RAMBOOT
 437 #  define CFG_ENV_IS_IN_FLASH   1
 438 #    define CFG_ENV_ADDR        (CFG_MONITOR_BASE + 0x40000)
 439 #    define CFG_ENV_SECT_SIZE   0x40000
 440 #else
 441 #  define CFG_ENV_IS_IN_NVRAM   1
 442 #  define CFG_ENV_ADDR          (CFG_MONITOR_BASE - 0x1000)
 443 #  define CFG_ENV_SIZE          0x200
 444 #endif /* CFG_RAMBOOT */
 445
 446
 447 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 448 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 449 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 450 #endif
 451
 452
 453 /*-----------------------------------------------------------------------
 454  * HIDx - Hardware Implementation-dependent Registers                    2-11
 455  *-----------------------------------------------------------------------
 456  * HID0 also contains cache control - initially enable both caches and
 457  * invalidate contents, then the final state leaves only the instruction
 458  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 459  * but Soft reset does not.
 460  *
 461  * HID1 has only read-only information - nothing to set.
 462  */
 463 /*#define CFG_HID0_INIT         0 */
 464 #define CFG_HID0_INIT   (HID0_ICE  |\
 465                          HID0_DCE  |\
 466                          HID0_ICFI |\
 467                          HID0_DCI  |\
 468                          HID0_IFEM |\
 469                          HID0_ABE)
 470
 471 #define CFG_HID0_FINAL          (HID0_ICE | HID0_IFEM | HID0_ABE )
 472
 473 #define CFG_HID2                0
 474
 475 #define CFG_SYPCR               0xFFFFFFC3
 476 #define CFG_BCR                 0x004C0000
 477 #define CFG_SIUMCR              0x4E64C000
 478 #define CFG_SCCR                0x00000000
 479
 480 /*      local bus memory map
 481  *
 482  *      0x00000000-0x03FFFFFF    64MB   SDRAM
 483  *      0x80000000-0x9FFFFFFF   512MB   outbound prefetchable PCI memory window
 484  *      0xA0000000-0xBFFFFFFF   512MB   outbound non-prefetchable PCI memory window
 485  *      0xF0000000-0xF001FFFF   128KB   MPC8266 internal memory
 486  *      0xF4000000-0xF7FFFFFF    64MB   outbound PCI I/O window
 487  *      0xF8000000-0xF8007FFF    32KB   BCSR
 488  *      0xF8100000-0xF8107FFF    32KB   ATM UNI
 489  *      0xF8200000-0xF8207FFF    32KB   PCI interrupt controller
 490  *      0xF8300000-0xF8307FFF    32KB   EEPROM
 491  *      0xFE000000-0xFFFFFFFF    32MB   flash
 492  */
 493 #define CFG_BR0_PRELIM  0xFE001801              /* flash */
 494 #define CFG_OR0_PRELIM  0xFE000836
 495 #define CFG_BR1_PRELIM  (CFG_BCSR | 0x1801)     /* BCSR */
 496 #define CFG_OR1_PRELIM  0xFFFF8010
 497 #define CFG_BR4_PRELIM  0xF8300801              /* EEPROM */
 498 #define CFG_OR4_PRELIM  0xFFFF8846
 499 #define CFG_BR5_PRELIM  0xF8100801              /* PM5350 ATM UNI */
 500 #define CFG_OR5_PRELIM  0xFFFF8E36
 501 #define CFG_BR8_PRELIM  (CFG_PCI_INT | 0x1801)  /* PCI interrupt controller */
 502 #define CFG_OR8_PRELIM  0xFFFF8010
 503
 504 #define CFG_RMR                 0x0001
 505 #define CFG_TMCNTSC             (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 506 #define CFG_PISCR               (PISCR_PS|PISCR_PTF|PISCR_PTE)
 507 #define CFG_RCCR                0
 508 #define CFG_MPTPR               0x00001900
 509 #define CFG_PSRT                0x00000021
 510
 511 #define CFG_RESET_ADDRESS       0x04400000
 512
 513 /* PCI Memory map (if different from default map */
 514 #define CFG_PCI_SLV_MEM_LOCAL   CFG_SDRAM_BASE          /* Local base */
 515 #define CFG_PCI_SLV_MEM_BUS             0x00000000              /* PCI base */
 516 #define CFG_PICMR0_MASK_ATTRIB  (PICMR_MASK_512MB | PICMR_ENABLE | \
 517                                  PICMR_PREFETCH_EN)
 518
 519 /*
 520  * These are the windows that allow the CPU to access PCI address space.
 521  * All three PCI master windows, which allow the CPU to access PCI
 522  * prefetch, non prefetch, and IO space (see below), must all fit within
 523  * these windows.
 524  */
 525
 526 /* PCIBR0 */
 527 #define CFG_PCI_MSTR0_LOCAL             0x80000000              /* Local base */
 528 #define CFG_PCIMSK0_MASK                PCIMSK_1GB              /* Size of window */
 529 /* PCIBR1 */
 530 #define CFG_PCI_MSTR1_LOCAL             0xF4000000              /* Local base */
 531 #define CFG_PCIMSK1_MASK                PCIMSK_64MB             /* Size of window */
 532
 533 /*
 534  * Master window that allows the CPU to access PCI Memory (prefetch).
 535  * This window will be setup with the first set of Outbound ATU registers
 536  * in the bridge.
 537  */
 538
 539 #define CFG_PCI_MSTR_MEM_LOCAL  0x80000000          /* Local base */
 540 #define CFG_PCI_MSTR_MEM_BUS    0x80000000          /* PCI base   */
 541 #define CFG_CPU_PCI_MEM_START   PCI_MSTR_MEM_LOCAL
 542 #define CFG_PCI_MSTR_MEM_SIZE   0x20000000          /* 512MB */
 543 #define CFG_POCMR0_MASK_ATTRIB  (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 544
 545 /*
 546  * Master window that allows the CPU to access PCI Memory (non-prefetch).
 547  * This window will be setup with the second set of Outbound ATU registers
 548  * in the bridge.
 549  */
 550
 551 #define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
 552 #define CFG_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
 553 #define CFG_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
 554 #define CFG_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
 555 #define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
 556
 557 /*
 558  * Master window that allows the CPU to access PCI IO space.
 559  * This window will be setup with the third set of Outbound ATU registers
 560  * in the bridge.
 561  */
 562
 563 #define CFG_PCI_MSTR_IO_LOCAL       0xF4000000          /* Local base */
 564 #define CFG_PCI_MSTR_IO_BUS         0xF4000000          /* PCI base   */
 565 #define CFG_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
 566 #define CFG_PCI_MSTR_IO_SIZE        0x04000000          /* 64MB */
 567 #define CFG_POCMR2_MASK_ATTRIB      (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
 568
 569
 570 #endif /* __CONFIG_H */