include/configs/MPC8308RDB.h

   1 /*
   2  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
   4  *
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 /*
  29  * High Level Configuration Options
  30  */
  31 #define CONFIG_E300             1 /* E300 family */
  32 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  33 #define CONFIG_MPC8308          1 /* MPC8308 CPU specific */
  34 #define CONFIG_MPC8308RDB       1 /* MPC8308RDB board specific */
  35
  36 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  37
  38 #define CONFIG_MISC_INIT_R
  39
  40 /* new uImage format support */
  41 #define CONFIG_FIT                      1
  42 #define CONFIG_FIT_VERBOSE              1
  43
  44 #define CONFIG_MMC     1
  45
  46 #ifdef CONFIG_MMC
  47 #define CONFIG_FSL_ESDHC
  48 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  49 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  50 #define CONFIG_SYS_FSL_ESDHC_USE_PIO
  51
  52 #define CONFIG_CMD_MMC
  53 #define CONFIG_GENERIC_MMC
  54 #define CONFIG_CMD_FAT
  55 #define CONFIG_DOS_PARTITION
  56 #endif
  57
  58 /*
  59  * On-board devices
  60  *
  61  * TSEC1 is SoC TSEC
  62  * TSEC2 is VSC switch
  63  */
  64 #define CONFIG_TSEC1
  65 #define CONFIG_VSC7385_ENET
  66
  67 /*
  68  * System Clock Setup
  69  */
  70 #define CONFIG_83XX_CLKIN       33333333 /* in Hz */
  71 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  72
  73 /*
  74  * Hardware Reset Configuration Word
  75  * if CLKIN is 66.66MHz, then
  76  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  77  * We choose the A type silicon as default, so the core is 400Mhz.
  78  */
  79 #define CONFIG_SYS_HRCW_LOW (\
  80         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  81         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  82         HRCWL_SVCOD_DIV_2 |\
  83         HRCWL_CSB_TO_CLKIN_4X1 |\
  84         HRCWL_CORE_TO_CSB_3X1)
  85 /*
  86  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  87  * in 8308's HRCWH according to the manual, but original Freescale's
  88  * code has them and I've expirienced some problems using the board
  89  * with BDI3000 attached when I've tried to set these bits to zero
  90  * (UART doesn't work after the 'reset run' command).
  91  */
  92 #define CONFIG_SYS_HRCW_HIGH (\
  93         HRCWH_PCI_HOST |\
  94         HRCWH_PCI1_ARBITER_ENABLE |\
  95         HRCWH_CORE_ENABLE |\
  96         HRCWH_FROM_0X00000100 |\
  97         HRCWH_BOOTSEQ_DISABLE |\
  98         HRCWH_SW_WATCHDOG_DISABLE |\
  99         HRCWH_ROM_LOC_LOCAL_16BIT |\
 100         HRCWH_RL_EXT_LEGACY |\
 101         HRCWH_TSEC1M_IN_RGMII |\
 102         HRCWH_TSEC2M_IN_RGMII |\
 103         HRCWH_BIG_ENDIAN)
 104
 105 /*
 106  * System IO Config
 107  */
 108 #define CONFIG_SYS_SICRH (\
 109         SICRH_ESDHC_A_SD |\
 110         SICRH_ESDHC_B_SD |\
 111         SICRH_ESDHC_C_SD |\
 112         SICRH_GPIO_A_TSEC2 |\
 113         SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
 114         SICRH_IEEE1588_A_GPIO |\
 115         SICRH_USB |\
 116         SICRH_GTM_GPIO |\
 117         SICRH_IEEE1588_B_GPIO |\
 118         SICRH_ETSEC2_CRS |\
 119         SICRH_GPIOSEL_1 |\
 120         SICRH_TMROBI_V3P3 |\
 121         SICRH_TSOBI1_V2P5 |\
 122         SICRH_TSOBI2_V2P5)      /* 0x01b7d103 */
 123 #define CONFIG_SYS_SICRL (\
 124         SICRL_SPI_PF0 |\
 125         SICRL_UART_PF0 |\
 126         SICRL_IRQ_PF0 |\
 127         SICRL_I2C2_PF0 |\
 128         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000040 */
 129
 130 /*
 131  * IMMR new address
 132  */
 133 #define CONFIG_SYS_IMMR         0xE0000000
 134
 135 /*
 136  * SERDES
 137  */
 138 #define CONFIG_FSL_SERDES
 139 #define CONFIG_FSL_SERDES1      0xe3000
 140
 141 /*
 142  * Arbiter Setup
 143  */
 144 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
 145 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
 146 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
 147
 148 /*
 149  * DDR Setup
 150  */
 151 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 152 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 153 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 154 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 155 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 156                                 | DDRCDR_PZ_LOZ \
 157                                 | DDRCDR_NZ_LOZ \
 158                                 | DDRCDR_ODT \
 159                                 | DDRCDR_Q_DRN)
 160                                 /* 0x7b880001 */
 161 /*
 162  * Manually set up DDR parameters
 163  * consist of two chips HY5PS12621BFP-C4 from HYNIX
 164  */
 165
 166 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 167
 168 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 169 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 170                                 | CSCONFIG_ODT_RD_NEVER \
 171                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 172                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 173                                 /* 0x80010102 */
 174 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 175 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 176                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 177                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 178                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 179                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 180                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 181                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 182                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 183                                 /* 0x00220802 */
 184 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 185                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 186                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 187                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 188                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
 189                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 190                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 191                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 192                                 /* 0x27256222 */
 193 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 194                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 195                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 196                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 197                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 198                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 199                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 200                                 /* 0x121048c5 */
 201 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
 202                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 203                                 /* 0x03600100 */
 204 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 205                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 206                                 | SDRAM_CFG_DBW_32)
 207                                 /* 0x43080000 */
 208
 209 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 210 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 211                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 212                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 213 #define CONFIG_SYS_DDR_MODE2            0x00000000
 214
 215 /*
 216  * Memory test
 217  */
 218 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 219 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 220
 221 /*
 222  * The reserved memory
 223  */
 224 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 225
 226 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 227 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 228
 229 /*
 230  * Initial RAM Base Address Setup
 231  */
 232 #define CONFIG_SYS_INIT_RAM_LOCK        1
 233 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 234 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 235 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 236         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 237
 238 /*
 239  * Local Bus Configuration & Clock Setup
 240  */
 241 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 242 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 243 #define CONFIG_SYS_LBC_LBCR             0x00040000
 244
 245 /*
 246  * FLASH on the Local Bus
 247  */
 248 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 249 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 250 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 251
 252 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 253 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is 8M */
 254 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
 255
 256 /* Window base at flash base */
 257 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 258 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 259
 260 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 261                                 | BR_PS_16      /* 16 bit port */ \
 262                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 263                                 | BR_V)         /* valid */
 264 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 265                                 | OR_UPM_XAM \
 266                                 | OR_GPCM_CSNT \
 267                                 | OR_GPCM_ACS_DIV2 \
 268                                 | OR_GPCM_XACS \
 269                                 | OR_GPCM_SCY_15 \
 270                                 | OR_GPCM_TRLX_SET \
 271                                 | OR_GPCM_EHTR_SET)
 272
 273 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 274 /* 127 64KB sectors and 8 8KB top sectors per device */
 275 #define CONFIG_SYS_MAX_FLASH_SECT       135
 276
 277 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 278 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 279
 280 /*
 281  * NAND Flash on the Local Bus
 282  */
 283 #define CONFIG_SYS_NAND_BASE    0xE0600000              /* 0xE0600000 */
 284 #define CONFIG_SYS_NAND_WINDOW_SIZE     (32 * 1024)     /* 0x00008000 */
 285 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE \
 286                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 287                                 | BR_PS_8               /* 8 bit Port */ \
 288                                 | BR_MS_FCM             /* MSEL = FCM */ \
 289                                 | BR_V)                 /* valid */
 290 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 291                                 | OR_FCM_CSCT \
 292                                 | OR_FCM_CST \
 293                                 | OR_FCM_CHT \
 294                                 | OR_FCM_SCY_1 \
 295                                 | OR_FCM_TRLX \
 296                                 | OR_FCM_EHTR)
 297                                 /* 0xFFFF8396 */
 298
 299 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 300 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 301
 302 #ifdef CONFIG_VSC7385_ENET
 303 #define CONFIG_TSEC2
 304                                         /* VSC7385 Base address on CS2 */
 305 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 306 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024) /* 0x00020000 */
 307 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 308                                         | BR_PS_8       /* 8-bit port */ \
 309                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 310                                         | BR_V)         /* valid */
 311                                         /* 0xF0000801 */
 312 #define CONFIG_SYS_OR2_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
 313                                         | OR_GPCM_CSNT \
 314                                         | OR_GPCM_XACS \
 315                                         | OR_GPCM_SCY_15 \
 316                                         | OR_GPCM_SETA \
 317                                         | OR_GPCM_TRLX_SET \
 318                                         | OR_GPCM_EHTR_SET)
 319                                         /* 0xFFFE09FF */
 320 /* Access window base at VSC7385 base */
 321 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 322 /* Access window size 128K */
 323 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 324 /* The flash address and size of the VSC7385 firmware image */
 325 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
 326 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 327 #endif
 328 /*
 329  * Serial Port
 330  */
 331 #define CONFIG_CONS_INDEX       1
 332 #define CONFIG_SYS_NS16550
 333 #define CONFIG_SYS_NS16550_SERIAL
 334 #define CONFIG_SYS_NS16550_REG_SIZE     1
 335 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 336
 337 #define CONFIG_SYS_BAUDRATE_TABLE  \
 338         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 339
 340 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 341 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 342
 343 /* Use the HUSH parser */
 344 #define CONFIG_SYS_HUSH_PARSER
 345
 346 /* Pass open firmware flat tree */
 347 #define CONFIG_OF_LIBFDT        1
 348 #define CONFIG_OF_BOARD_SETUP   1
 349 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 350
 351 /* I2C */
 352 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 353 #define CONFIG_FSL_I2C
 354 #define CONFIG_I2C_MULTI_BUS
 355 #define CONFIG_SYS_I2C_SPEED    400000 /* I2C speed and slave address */
 356 #define CONFIG_SYS_I2C_SLAVE    0x7F
 357 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } /* Don't probe these addrs */
 358 #define CONFIG_SYS_I2C_OFFSET   0x3000
 359 #define CONFIG_SYS_I2C2_OFFSET  0x3100
 360
 361 /*
 362  * SPI on header J8
 363  *
 364  * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
 365  * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
 366  */
 367 #ifdef CONFIG_MPC8XXX_SPI
 368 #define CONFIG_CMD_SPI
 369 #define CONFIG_USE_SPIFLASH
 370 #define CONFIG_SPI_FLASH
 371 #define CONFIG_SPI_FLASH_SPANSION
 372 #define CONFIG_CMD_SF
 373 #endif
 374
 375 /*
 376  * Board info - revision and where boot from
 377  */
 378 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
 379
 380 /*
 381  * Config on-board RTC
 382  */
 383 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
 384 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 385
 386 /*
 387  * General PCI
 388  * Addresses are mapped 1-1.
 389  */
 390 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 391 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 392 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 393 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 394 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 395 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 396 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 397 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 398 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 399
 400 /* enable PCIE clock */
 401 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 402
 403 #define CONFIG_PCI
 404 #define CONFIG_PCIE
 405
 406 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 407
 408 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 409 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 410
 411 /*
 412  * TSEC
 413  */
 414 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 415 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 416 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 417 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 418 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 419
 420 /*
 421  * TSEC ethernet configuration
 422  */
 423 #define CONFIG_MII              1 /* MII PHY management */
 424 #define CONFIG_TSEC1_NAME       "eTSEC0"
 425 #define CONFIG_TSEC2_NAME       "eTSEC1"
 426 #define TSEC1_PHY_ADDR          2
 427 #define TSEC2_PHY_ADDR          1
 428 #define TSEC1_PHYIDX            0
 429 #define TSEC2_PHYIDX            0
 430 #define TSEC1_FLAGS             TSEC_GIGABIT
 431 #define TSEC2_FLAGS             TSEC_GIGABIT
 432
 433 /* Options are: eTSEC[0-1] */
 434 #define CONFIG_ETHPRIME         "eTSEC0"
 435
 436 /*
 437  * Environment
 438  */
 439 #define CONFIG_ENV_IS_IN_FLASH  1
 440 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 441                                  CONFIG_SYS_MONITOR_LEN)
 442 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 443 #define CONFIG_ENV_SIZE         0x2000
 444 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 445 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 446
 447 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 448 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 449
 450 /*
 451  * BOOTP options
 452  */
 453 #define CONFIG_BOOTP_BOOTFILESIZE
 454 #define CONFIG_BOOTP_BOOTPATH
 455 #define CONFIG_BOOTP_GATEWAY
 456 #define CONFIG_BOOTP_HOSTNAME
 457
 458 /*
 459  * Command line configuration.
 460  */
 461 #include <config_cmd_default.h>
 462
 463 #define CONFIG_CMD_DATE
 464 #define CONFIG_CMD_DHCP
 465 #define CONFIG_CMD_I2C
 466 #define CONFIG_CMD_MII
 467 #define CONFIG_CMD_NET
 468 #define CONFIG_CMD_PCI
 469 #define CONFIG_CMD_PING
 470
 471 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 472
 473 /*
 474  * Miscellaneous configurable options
 475  */
 476 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 477 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 478 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt */
 479
 480 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 481
 482 /* Print Buffer Size */
 483 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 484 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 485 /* Boot Argument Buffer Size */
 486 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 487 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 488
 489 /*
 490  * For booting Linux, the board info and command line data
 491  * have to be in the first 256 MB of memory, since this is
 492  * the maximum mapped by the Linux kernel during initialization.
 493  */
 494 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 495
 496 /*
 497  * Core HID Setup
 498  */
 499 #define CONFIG_SYS_HID0_INIT    0x000000000
 500 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 501                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 502                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 503 #define CONFIG_SYS_HID2         HID2_HBE
 504
 505 /*
 506  * MMU Setup
 507  */
 508
 509 /* DDR: cache cacheable */
 510 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 511                                         BATL_MEMCOHERENCE)
 512 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
 513                                         BATU_VS | BATU_VP)
 514 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 515 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 516
 517 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 518 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 519                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 520 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
 521                                         BATU_VP)
 522 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 523 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 524
 525 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 526 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 527                                         BATL_MEMCOHERENCE)
 528 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
 529                                         BATU_VS | BATU_VP)
 530 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 531                                         BATL_CACHEINHIBIT | \
 532                                         BATL_GUARDEDSTORAGE)
 533 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 534
 535 /* Stack in dcache: cacheable, no memory coherence */
 536 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 537 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 538                                         BATU_VS | BATU_VP)
 539 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 540 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 541
 542 /*
 543  * Environment Configuration
 544  */
 545
 546 #define CONFIG_ENV_OVERWRITE
 547
 548 #if defined(CONFIG_TSEC_ENET)
 549 #define CONFIG_HAS_ETH0
 550 #define CONFIG_HAS_ETH1
 551 #endif
 552
 553 #define CONFIG_BAUDRATE 115200
 554
 555 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 556
 557 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
 558
 559 #define xstr(s) str(s)
 560 #define str(s)  #s
 561
 562 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 563         "netdev=eth0\0"                                                 \
 564         "consoledev=ttyS0\0"                                            \
 565         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 566                 "nfsroot=${serverip}:${rootpath}\0"                     \
 567         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 568         "addip=setenv bootargs ${bootargs} "                            \
 569                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 570                 ":${hostname}:${netdev}:off panic=1\0"                  \
 571         "addtty=setenv bootargs ${bootargs}"                            \
 572                 " console=${consoledev},${baudrate}\0"                  \
 573         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 574         "addmisc=setenv bootargs ${bootargs}\0"                         \
 575         "kernel_addr=FE080000\0"                                        \
 576         "fdt_addr=FE280000\0"                                           \
 577         "ramdisk_addr=FE290000\0"                                       \
 578         "u-boot=mpc8308rdb/u-boot.bin\0"                                \
 579         "kernel_addr_r=1000000\0"                                       \
 580         "fdt_addr_r=C00000\0"                                           \
 581         "hostname=mpc8308rdb\0"                                         \
 582         "bootfile=mpc8308rdb/uImage\0"                                  \
 583         "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0"                           \
 584         "rootpath=/opt/eldk-4.2/ppc_6xx\0"                              \
 585         "flash_self=run ramargs addip addtty addmtd addmisc;"           \
 586                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 587         "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
 588                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 589         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 590                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 591                 "run nfsargs addip addtty addmtd addmisc;"              \
 592                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 593         "bootcmd=run flash_self\0"                                      \
 594         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 595         "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE)             \
 596                 " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE)      \
 597                 " +${filesize};cp.b ${fileaddr} "                       \
 598                 xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"          \
 599         "upd=run load update\0"                                         \
 600
 601 #endif  /* __CONFIG_H */