include/configs/MPC8313ERDB.h

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 /*
   7  * mpc8313epb board configuration file
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * High Level Configuration Options
  15  */
  16 #define CONFIG_E300             1
  17 #define CONFIG_MPC831x          1
  18 #define CONFIG_MPC8313          1
  19 #define CONFIG_MPC8313ERDB      1
  20
  21 #ifdef CONFIG_NAND
  22 #define CONFIG_SPL_INIT_MINIMAL
  23 #define CONFIG_SPL_FLUSH_IMAGE
  24 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  25 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
  26
  27 #ifdef CONFIG_SPL_BUILD
  28 #define CONFIG_NS16550_MIN_FUNCTIONS
  29 #endif
  30
  31 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  32 #define CONFIG_SPL_MAX_SIZE     (4 * 1024)
  33 #define CONFIG_SPL_PAD_TO       0x4000
  34
  35 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
  36 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
  37 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  38 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
  39 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  40 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  41
  42 #ifdef CONFIG_SPL_BUILD
  43 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  44 #endif
  45
  46 #endif /* CONFIG_NAND */
  47
  48 #ifndef CONFIG_SYS_MONITOR_BASE
  49 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  50 #endif
  51
  52 #define CONFIG_PCI_INDIRECT_BRIDGE
  53 #define CONFIG_FSL_ELBC 1
  54
  55 #define CONFIG_MISC_INIT_R
  56
  57 /*
  58  * On-board devices
  59  *
  60  * TSEC1 is VSC switch
  61  * TSEC2 is SoC TSEC
  62  */
  63 #define CONFIG_VSC7385_ENET
  64 #define CONFIG_TSEC2
  65
  66 #ifdef CONFIG_SYS_66MHZ
  67 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
  68 #elif defined(CONFIG_SYS_33MHZ)
  69 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
  70 #else
  71 #error Unknown oscillator frequency.
  72 #endif
  73
  74 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  75
  76 #define CONFIG_BOARD_EARLY_INIT_R               /* call board_early_init_r */
  77
  78 #define CONFIG_SYS_IMMR         0xE0000000
  79
  80 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
  81 #define CONFIG_DEFAULT_IMMR     CONFIG_SYS_IMMR
  82 #endif
  83
  84 #define CONFIG_SYS_MEMTEST_START        0x00001000
  85 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  86
  87 /* Early revs of this board will lock up hard when attempting
  88  * to access the PMC registers, unless a JTAG debugger is
  89  * connected, or some resistor modifications are made.
  90  */
  91 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  92
  93 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  94 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
  95
  96 /*
  97  * Device configurations
  98  */
  99
 100 /* Vitesse 7385 */
 101
 102 #ifdef CONFIG_VSC7385_ENET
 103
 104 #define CONFIG_TSEC1
 105
 106 /* The flash address and size of the VSC7385 firmware image */
 107 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
 108 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 109
 110 #endif
 111
 112 /*
 113  * DDR Setup
 114  */
 115 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
 116 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 117 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 118
 119 /*
 120  * Manually set up DDR parameters, as this board does not
 121  * seem to have the SPD connected to I2C.
 122  */
 123 #define CONFIG_SYS_DDR_SIZE     128             /* MB */
 124 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 125                                 | CSCONFIG_ODT_RD_NEVER \
 126                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 127                                 | CSCONFIG_ROW_BIT_13 \
 128                                 | CSCONFIG_COL_BIT_10)
 129                                 /* 0x80010102 */
 130
 131 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 132 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 133                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 134                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 135                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 136                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 137                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 138                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 139                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 140                                 /* 0x00220802 */
 141 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 142                                 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 143                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 144                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 145                                 | (10 << TIMING_CFG1_REFREC_SHIFT) \
 146                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 147                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 148                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 149                                 /* 0x3835a322 */
 150 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 151                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 152                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 153                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 154                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 155                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 156                                 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
 157                                 /* 0x129048c6 */ /* P9-45,may need tuning */
 158 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
 159                                 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 160                                 /* 0x05100500 */
 161 #if defined(CONFIG_DDR_2T_TIMING)
 162 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 163                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 164                                 | SDRAM_CFG_DBW_32 \
 165                                 | SDRAM_CFG_2T_EN)
 166                                 /* 0x43088000 */
 167 #else
 168 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 169                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 170                                 | SDRAM_CFG_DBW_32)
 171                                 /* 0x43080000 */
 172 #endif
 173 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 174 /* set burst length to 8 for 32-bit data path */
 175 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 176                                 | (0x0632 << SDRAM_MODE_SD_SHIFT))
 177                                 /* 0x44480632 */
 178 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
 179
 180 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 181                                 /*0x02000000*/
 182 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 183                                 | DDRCDR_PZ_NOMZ \
 184                                 | DDRCDR_NZ_NOMZ \
 185                                 | DDRCDR_M_ODR)
 186
 187 /*
 188  * FLASH on the Local Bus
 189  */
 190 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 191 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 192 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 193 #define CONFIG_SYS_FLASH_SIZE           8       /* flash size in MB */
 194 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 195 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 196 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* buffer up multiple bytes */
 197
 198 #define CONFIG_SYS_NOR_BR_PRELIM        (CONFIG_SYS_FLASH_BASE \
 199                                         | BR_PS_16      /* 16 bit port */ \
 200                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 201                                         | BR_V)         /* valid */
 202 #define CONFIG_SYS_NOR_OR_PRELIM        (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 203                                 | OR_GPCM_XACS \
 204                                 | OR_GPCM_SCY_9 \
 205                                 | OR_GPCM_EHTR \
 206                                 | OR_GPCM_EAD)
 207                                 /* 0xFF006FF7   TODO SLOW 16 MB flash size */
 208                                         /* window base at flash base */
 209 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 210                                         /* 16 MB window size */
 211 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
 212
 213 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 214 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* sectors per device */
 215
 216 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 217 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 218
 219 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
 220         !defined(CONFIG_SPL_BUILD)
 221 #define CONFIG_SYS_RAMBOOT
 222 #endif
 223
 224 #define CONFIG_SYS_INIT_RAM_LOCK        1
 225 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 226 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 227
 228 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 229                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 230 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 231
 232 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 233 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 234 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 235
 236 /*
 237  * Local Bus LCRR and LBCR regs
 238  */
 239 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
 240 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 241 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
 242                                 | (0xFF << LBCR_BMT_SHIFT) \
 243                                 | 0xF)  /* 0x0004ff0f */
 244
 245                                 /* LB refresh timer prescal, 266MHz/32 */
 246 #define CONFIG_SYS_LBC_MRTPR    0x20000000  /*TODO */
 247
 248 /* drivers/mtd/nand/nand.c */
 249 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
 250 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 251 #else
 252 #define CONFIG_SYS_NAND_BASE            0xE2800000
 253 #endif
 254
 255 #define CONFIG_MTD_DEVICE
 256 #define CONFIG_MTD_PARTITION
 257
 258 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 259 #define CONFIG_NAND_FSL_ELBC 1
 260 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 261 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 262
 263 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE \
 264                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 265                                 | BR_PS_8               /* 8 bit port */ \
 266                                 | BR_MS_FCM             /* MSEL = FCM */ \
 267                                 | BR_V)                 /* valid */
 268 #define CONFIG_SYS_NAND_OR_PRELIM       \
 269                                 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 270                                 | OR_FCM_CSCT \
 271                                 | OR_FCM_CST \
 272                                 | OR_FCM_CHT \
 273                                 | OR_FCM_SCY_1 \
 274                                 | OR_FCM_TRLX \
 275                                 | OR_FCM_EHTR)
 276                                 /* 0xFFFF8396 */
 277
 278 #ifdef CONFIG_NAND
 279 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 280 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 281 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 282 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 283 #else
 284 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 285 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 286 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 287 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 288 #endif
 289
 290 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 291 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 292
 293 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 294 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 295
 296 /* local bus write LED / read status buffer (BCSR) mapping */
 297 #define CONFIG_SYS_BCSR_ADDR            0xFA000000
 298 #define CONFIG_SYS_BCSR_SIZE            (32 * 1024)     /* 0x00008000 */
 299                                         /* map at 0xFA000000 on LCS3 */
 300 #define CONFIG_SYS_BR3_PRELIM           (CONFIG_SYS_BCSR_ADDR \
 301                                         | BR_PS_8       /* 8 bit port */ \
 302                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 303                                         | BR_V)         /* valid */
 304                                         /* 0xFA000801 */
 305 #define CONFIG_SYS_OR3_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
 306                                         | OR_GPCM_CSNT \
 307                                         | OR_GPCM_ACS_DIV2 \
 308                                         | OR_GPCM_XACS \
 309                                         | OR_GPCM_SCY_15 \
 310                                         | OR_GPCM_TRLX_SET \
 311                                         | OR_GPCM_EHTR_SET \
 312                                         | OR_GPCM_EAD)
 313                                         /* 0xFFFF8FF7 */
 314 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_BCSR_ADDR
 315 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 316
 317 /* Vitesse 7385 */
 318
 319 #ifdef CONFIG_VSC7385_ENET
 320
 321                                         /* VSC7385 Base address on LCS2 */
 322 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 323 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024)    /* 0x00020000 */
 324
 325 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 326                                         | BR_PS_8       /* 8 bit port */ \
 327                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 328                                         | BR_V)         /* valid */
 329 #define CONFIG_SYS_OR2_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
 330                                         | OR_GPCM_CSNT \
 331                                         | OR_GPCM_XACS \
 332                                         | OR_GPCM_SCY_15 \
 333                                         | OR_GPCM_SETA \
 334                                         | OR_GPCM_TRLX_SET \
 335                                         | OR_GPCM_EHTR_SET \
 336                                         | OR_GPCM_EAD)
 337                                         /* 0xFFFE09FF */
 338
 339                                         /* Access window base at VSC7385 base */
 340 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 341 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 342
 343 #endif
 344
 345 #define CONFIG_MPC83XX_GPIO 1
 346
 347 /*
 348  * Serial Port
 349  */
 350 #define CONFIG_CONS_INDEX       1
 351 #define CONFIG_SYS_NS16550_SERIAL
 352 #define CONFIG_SYS_NS16550_REG_SIZE     1
 353
 354 #define CONFIG_SYS_BAUDRATE_TABLE       \
 355         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 356
 357 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 358 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 359
 360 /* I2C */
 361 #define CONFIG_SYS_I2C
 362 #define CONFIG_SYS_I2C_FSL
 363 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 364 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 365 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 366 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 367 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 368 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 369 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 370
 371 /*
 372  * General PCI
 373  * Addresses are mapped 1-1.
 374  */
 375 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 376 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 377 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 378 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 379 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 380 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 381 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 382 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 383 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 384
 385 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 386
 387 /*
 388  * TSEC
 389  */
 390 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 391
 392 #define CONFIG_GMII                     /* MII PHY management */
 393
 394 #ifdef CONFIG_TSEC1
 395 #define CONFIG_HAS_ETH0
 396 #define CONFIG_TSEC1_NAME       "TSEC0"
 397 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 398 #define TSEC1_PHY_ADDR          0x1c
 399 #define TSEC1_FLAGS             TSEC_GIGABIT
 400 #define TSEC1_PHYIDX            0
 401 #endif
 402
 403 #ifdef CONFIG_TSEC2
 404 #define CONFIG_HAS_ETH1
 405 #define CONFIG_TSEC2_NAME       "TSEC1"
 406 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 407 #define TSEC2_PHY_ADDR          4
 408 #define TSEC2_FLAGS             TSEC_GIGABIT
 409 #define TSEC2_PHYIDX            0
 410 #endif
 411
 412 /* Options are: TSEC[0-1] */
 413 #define CONFIG_ETHPRIME                 "TSEC1"
 414
 415 /*
 416  * Configure on-board RTC
 417  */
 418 #define CONFIG_RTC_DS1337
 419 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 420
 421 /*
 422  * Environment
 423  */
 424 #if defined(CONFIG_NAND)
 425         #define CONFIG_ENV_OFFSET               (512 * 1024)
 426         #define CONFIG_ENV_SECT_SIZE    CONFIG_SYS_NAND_BLOCK_SIZE
 427         #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 428         #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 429         #define CONFIG_ENV_RANGE                (CONFIG_ENV_SECT_SIZE * 4)
 430         #define CONFIG_ENV_OFFSET_REDUND        \
 431                                         (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 432 #elif !defined(CONFIG_SYS_RAMBOOT)
 433         #define CONFIG_ENV_ADDR         \
 434                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 435         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 436         #define CONFIG_ENV_SIZE         0x2000
 437
 438 /* Address and size of Redundant Environment Sector */
 439 #else
 440         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 441         #define CONFIG_ENV_SIZE         0x2000
 442 #endif
 443
 444 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 445 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 446
 447 /*
 448  * BOOTP options
 449  */
 450 #define CONFIG_BOOTP_BOOTFILESIZE
 451 #define CONFIG_BOOTP_BOOTPATH
 452 #define CONFIG_BOOTP_GATEWAY
 453 #define CONFIG_BOOTP_HOSTNAME
 454
 455 /*
 456  * Command line configuration.
 457  */
 458
 459 #define CONFIG_CMDLINE_EDITING 1
 460 #define CONFIG_AUTO_COMPLETE    /* add autocompletion support   */
 461
 462 /*
 463  * Miscellaneous configurable options
 464  */
 465 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 466 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 467 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 468
 469                                 /* Boot Argument Buffer Size */
 470 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 471
 472 /*
 473  * For booting Linux, the board info and command line data
 474  * have to be in the first 256 MB of memory, since this is
 475  * the maximum mapped by the Linux kernel during initialization.
 476  */
 477                                 /* Initial Memory map for Linux*/
 478 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 479 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 480
 481 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST  */
 482
 483 #ifdef CONFIG_SYS_66MHZ
 484
 485 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
 486 /* 0x62040000 */
 487 #define CONFIG_SYS_HRCW_LOW (\
 488         0x20000000 /* reserved, must be set */ |\
 489         HRCWL_DDRCM |\
 490         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 491         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 492         HRCWL_CSB_TO_CLKIN_2X1 |\
 493         HRCWL_CORE_TO_CSB_2X1)
 494
 495 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
 496
 497 #elif defined(CONFIG_SYS_33MHZ)
 498
 499 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
 500 /* 0x65040000 */
 501 #define CONFIG_SYS_HRCW_LOW (\
 502         0x20000000 /* reserved, must be set */ |\
 503         HRCWL_DDRCM |\
 504         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 505         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 506         HRCWL_CSB_TO_CLKIN_5X1 |\
 507         HRCWL_CORE_TO_CSB_2X1)
 508
 509 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
 510
 511 #endif
 512
 513 #define CONFIG_SYS_HRCW_HIGH_BASE (\
 514         HRCWH_PCI_HOST |\
 515         HRCWH_PCI1_ARBITER_ENABLE |\
 516         HRCWH_CORE_ENABLE |\
 517         HRCWH_BOOTSEQ_DISABLE |\
 518         HRCWH_SW_WATCHDOG_DISABLE |\
 519         HRCWH_TSEC1M_IN_RGMII |\
 520         HRCWH_TSEC2M_IN_RGMII |\
 521         HRCWH_BIG_ENDIAN)
 522
 523 #ifdef CONFIG_NAND
 524 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 525                        HRCWH_FROM_0XFFF00100 |\
 526                        HRCWH_ROM_LOC_NAND_SP_8BIT |\
 527                        HRCWH_RL_EXT_NAND)
 528 #else
 529 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
 530                        HRCWH_FROM_0X00000100 |\
 531                        HRCWH_ROM_LOC_LOCAL_16BIT |\
 532                        HRCWH_RL_EXT_LEGACY)
 533 #endif
 534
 535 /* System IO Config */
 536 #define CONFIG_SYS_SICRH        (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
 537                         /* Enable Internal USB Phy and GPIO on LCD Connector */
 538 #define CONFIG_SYS_SICRL        (SICRL_USBDR_10 | SICRL_LBC)
 539
 540 #define CONFIG_SYS_HID0_INIT    0x000000000
 541 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 542                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 543                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 544
 545 #define CONFIG_SYS_HID2 HID2_HBE
 546
 547 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 548
 549 /* DDR @ 0x00000000 */
 550 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
 551 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 552                                 | BATU_BL_256M \
 553                                 | BATU_VS \
 554                                 | BATU_VP)
 555
 556 /* PCI @ 0x80000000 */
 557 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
 558 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 559                                 | BATU_BL_256M \
 560                                 | BATU_VS \
 561                                 | BATU_VP)
 562 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 563                                 | BATL_PP_RW \
 564                                 | BATL_CACHEINHIBIT \
 565                                 | BATL_GUARDEDSTORAGE)
 566 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 567                                 | BATU_BL_256M \
 568                                 | BATU_VS \
 569                                 | BATU_VP)
 570
 571 /* PCI2 not supported on 8313 */
 572 #define CONFIG_SYS_IBAT3L       (0)
 573 #define CONFIG_SYS_IBAT3U       (0)
 574 #define CONFIG_SYS_IBAT4L       (0)
 575 #define CONFIG_SYS_IBAT4U       (0)
 576
 577 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 578 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 579                                 | BATL_PP_RW \
 580                                 | BATL_CACHEINHIBIT \
 581                                 | BATL_GUARDEDSTORAGE)
 582 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 583                                 | BATU_BL_256M \
 584                                 | BATU_VS \
 585                                 | BATU_VP)
 586
 587 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 588 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 589 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 590
 591 #define CONFIG_SYS_IBAT7L       (0)
 592 #define CONFIG_SYS_IBAT7U       (0)
 593
 594 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 595 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 596 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 597 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 598 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 599 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 600 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 601 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 602 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 603 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 604 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 605 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 606 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 607 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 608 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 609 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 610
 611 /*
 612  * Environment Configuration
 613  */
 614 #define CONFIG_ENV_OVERWRITE
 615
 616 #define CONFIG_NETDEV           "eth1"
 617
 618 #define CONFIG_HOSTNAME         mpc8313erdb
 619 #define CONFIG_ROOTPATH         "/nfs/root/path"
 620 #define CONFIG_BOOTFILE         "uImage"
 621                                 /* U-Boot image on TFTP server */
 622 #define CONFIG_UBOOTPATH        "u-boot.bin"
 623 #define CONFIG_FDTFILE          "mpc8313erdb.dtb"
 624
 625                                 /* default location for tftp and bootm */
 626 #define CONFIG_LOADADDR         800000
 627
 628 #define CONFIG_EXTRA_ENV_SETTINGS \
 629         "netdev=" CONFIG_NETDEV "\0"                                    \
 630         "ethprime=TSEC1\0"                                              \
 631         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 632         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 633                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 634                         " +$filesize; " \
 635                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 636                         " +$filesize; " \
 637                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 638                         " $filesize; "  \
 639                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 640                         " +$filesize; " \
 641                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 642                         " $filesize\0"  \
 643         "fdtaddr=780000\0"                                              \
 644         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 645         "console=ttyS0\0"                                               \
 646         "setbootargs=setenv bootargs "                                  \
 647                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 648         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 649                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 650                                                         "$netdev:off " \
 651                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 652
 653 #define CONFIG_NFSBOOTCOMMAND                                           \
 654         "setenv rootdev /dev/nfs;"                                      \
 655         "run setbootargs;"                                              \
 656         "run setipargs;"                                                \
 657         "tftp $loadaddr $bootfile;"                                     \
 658         "tftp $fdtaddr $fdtfile;"                                       \
 659         "bootm $loadaddr - $fdtaddr"
 660
 661 #define CONFIG_RAMBOOTCOMMAND                                           \
 662         "setenv rootdev /dev/ram;"                                      \
 663         "run setbootargs;"                                              \
 664         "tftp $ramdiskaddr $ramdiskfile;"                               \
 665         "tftp $loadaddr $bootfile;"                                     \
 666         "tftp $fdtaddr $fdtfile;"                                       \
 667         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 668
 669 #endif  /* __CONFIG_H */