]> git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/MPC832XEMDS.h
b3322ae719452eb437ad2fb2f25efb11ff1f9ed3
[people/ms/u-boot.git] / include / configs / MPC832XEMDS.h
1 /*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 #define CONFIG_DISPLAY_BOARDINFO
11
12 /*
13 * High Level Configuration Options
14 */
15 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_QE 1 /* Has QE */
17 #define CONFIG_MPC832x 1 /* MPC832x CPU specific */
18 #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
19
20 #define CONFIG_SYS_TEXT_BASE 0xFE000000
21
22 /*
23 * System Clock Setup
24 */
25 #ifdef CONFIG_PCISLAVE
26 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */
27 #else
28 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
29 #endif
30
31 #ifndef CONFIG_SYS_CLK_FREQ
32 #define CONFIG_SYS_CLK_FREQ 66000000
33 #endif
34
35 /*
36 * Hardware Reset Configuration Word
37 */
38 #define CONFIG_SYS_HRCW_LOW (\
39 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
40 HRCWL_DDR_TO_SCB_CLK_2X1 |\
41 HRCWL_VCO_1X2 |\
42 HRCWL_CSB_TO_CLKIN_2X1 |\
43 HRCWL_CORE_TO_CSB_2X1 |\
44 HRCWL_CE_PLL_VCO_DIV_2 |\
45 HRCWL_CE_PLL_DIV_1X1 |\
46 HRCWL_CE_TO_PLL_1X3)
47
48 #ifdef CONFIG_PCISLAVE
49 #define CONFIG_SYS_HRCW_HIGH (\
50 HRCWH_PCI_AGENT |\
51 HRCWH_PCI1_ARBITER_DISABLE |\
52 HRCWH_CORE_ENABLE |\
53 HRCWH_FROM_0XFFF00100 |\
54 HRCWH_BOOTSEQ_DISABLE |\
55 HRCWH_SW_WATCHDOG_DISABLE |\
56 HRCWH_ROM_LOC_LOCAL_16BIT |\
57 HRCWH_BIG_ENDIAN |\
58 HRCWH_LALE_NORMAL)
59 #else
60 #define CONFIG_SYS_HRCW_HIGH (\
61 HRCWH_PCI_HOST |\
62 HRCWH_PCI1_ARBITER_ENABLE |\
63 HRCWH_CORE_ENABLE |\
64 HRCWH_FROM_0X00000100 |\
65 HRCWH_BOOTSEQ_DISABLE |\
66 HRCWH_SW_WATCHDOG_DISABLE |\
67 HRCWH_ROM_LOC_LOCAL_16BIT |\
68 HRCWH_BIG_ENDIAN |\
69 HRCWH_LALE_NORMAL)
70 #endif
71
72 /*
73 * System IO Config
74 */
75 #define CONFIG_SYS_SICRL 0x00000000
76
77 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
78 #define CONFIG_BOARD_EARLY_INIT_R
79
80 /*
81 * IMMR new address
82 */
83 #define CONFIG_SYS_IMMR 0xE0000000
84
85 /*
86 * DDR Setup
87 */
88 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
89 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
90 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
91 #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
92
93 #undef CONFIG_SPD_EEPROM
94 #if defined(CONFIG_SPD_EEPROM)
95 /* Determine DDR configuration from I2C interface
96 */
97 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
98 #else
99 /* Manually set up DDR parameters
100 */
101 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
102 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
103 | CSCONFIG_AP \
104 | CSCONFIG_ODT_WR_CFG \
105 | CSCONFIG_ROW_BIT_13 \
106 | CSCONFIG_COL_BIT_10)
107 /* 0x80840102 */
108 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
109 | (0 << TIMING_CFG0_WRT_SHIFT) \
110 | (0 << TIMING_CFG0_RRT_SHIFT) \
111 | (0 << TIMING_CFG0_WWT_SHIFT) \
112 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
113 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
114 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
115 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
116 /* 0x00220802 */
117 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
118 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
119 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
120 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
121 | (13 << TIMING_CFG1_REFREC_SHIFT) \
122 | (3 << TIMING_CFG1_WRREC_SHIFT) \
123 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
124 | (2 << TIMING_CFG1_WRTORD_SHIFT))
125 /* 0x3935D322 */
126 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
127 | (31 << TIMING_CFG2_CPO_SHIFT) \
128 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
129 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
130 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
131 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
132 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
133 /* 0x0F9048CA */
134 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
135 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
136 /* 0x02000000 */
137 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
138 | (0x0232 << SDRAM_MODE_SD_SHIFT))
139 /* 0x44400232 */
140 #define CONFIG_SYS_DDR_MODE2 0x8000c000
141 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
142 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
143 /* 0x03200064 */
144 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
145 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
146 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
147 | SDRAM_CFG_32_BE)
148 /* 0x43080000 */
149 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
150 #endif
151
152 /*
153 * Memory test
154 */
155 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
156 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
157 #define CONFIG_SYS_MEMTEST_END 0x00100000
158
159 /*
160 * The reserved memory
161 */
162 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
163
164 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
165 #define CONFIG_SYS_RAMBOOT
166 #else
167 #undef CONFIG_SYS_RAMBOOT
168 #endif
169
170 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
171 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
172 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
173
174 /*
175 * Initial RAM Base Address Setup
176 */
177 #define CONFIG_SYS_INIT_RAM_LOCK 1
178 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
179 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
180 #define CONFIG_SYS_GBL_DATA_OFFSET \
181 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
182
183 /*
184 * Local Bus Configuration & Clock Setup
185 */
186 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
187 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
188 #define CONFIG_SYS_LBC_LBCR 0x00000000
189
190 /*
191 * FLASH on the Local Bus
192 */
193 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
194 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
195 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
196 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
197 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
198
199 /* Window base at flash base */
200 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
201 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
202
203 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
204 | BR_PS_16 /* 16 bit port */ \
205 | BR_MS_GPCM /* MSEL = GPCM */ \
206 | BR_V) /* valid */
207 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
208 | OR_GPCM_XAM \
209 | OR_GPCM_CSNT \
210 | OR_GPCM_ACS_DIV2 \
211 | OR_GPCM_XACS \
212 | OR_GPCM_SCY_15 \
213 | OR_GPCM_TRLX_SET \
214 | OR_GPCM_EHTR_SET \
215 | OR_GPCM_EAD)
216 /* 0xfe006ff7 */
217
218 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
219 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
220
221 #undef CONFIG_SYS_FLASH_CHECKSUM
222
223 /*
224 * BCSR on the Local Bus
225 */
226 #define CONFIG_SYS_BCSR 0xF8000000
227 /* Access window base at BCSR base */
228 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
229 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
230
231 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
232 | BR_PS_8 \
233 | BR_MS_GPCM \
234 | BR_V)
235 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
236 | OR_GPCM_XAM \
237 | OR_GPCM_CSNT \
238 | OR_GPCM_XACS \
239 | OR_GPCM_SCY_15 \
240 | OR_GPCM_TRLX_SET \
241 | OR_GPCM_EHTR_SET \
242 | OR_GPCM_EAD)
243 /* 0xFFFFE9F7 */
244
245 /*
246 * Windows to access PIB via local bus
247 */
248 /* PIB window base 0xF8008000 */
249 #define CONFIG_SYS_PIB_BASE 0xF8008000
250 #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
251 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE
252 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
253
254 /*
255 * CS2 on Local Bus, to PIB
256 */
257 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \
258 | BR_PS_8 \
259 | BR_MS_GPCM \
260 | BR_V)
261 /* 0xF8008801 */
262 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
263 | OR_GPCM_XAM \
264 | OR_GPCM_CSNT \
265 | OR_GPCM_XACS \
266 | OR_GPCM_SCY_15 \
267 | OR_GPCM_TRLX_SET \
268 | OR_GPCM_EHTR_SET \
269 | OR_GPCM_EAD)
270 /* 0xffffe9f7 */
271
272 /*
273 * CS3 on Local Bus, to PIB
274 */
275 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \
276 CONFIG_SYS_PIB_WINDOW_SIZE) \
277 | BR_PS_8 \
278 | BR_MS_GPCM \
279 | BR_V)
280 /* 0xF8010801 */
281 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
282 | OR_GPCM_XAM \
283 | OR_GPCM_CSNT \
284 | OR_GPCM_XACS \
285 | OR_GPCM_SCY_15 \
286 | OR_GPCM_TRLX_SET \
287 | OR_GPCM_EHTR_SET \
288 | OR_GPCM_EAD)
289 /* 0xffffe9f7 */
290
291 /*
292 * Serial Port
293 */
294 #define CONFIG_CONS_INDEX 1
295 #define CONFIG_SYS_NS16550_SERIAL
296 #define CONFIG_SYS_NS16550_REG_SIZE 1
297 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
298
299 #define CONFIG_SYS_BAUDRATE_TABLE \
300 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
301
302 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
303 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
304
305 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
306 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
307 /* Use the HUSH parser */
308 #define CONFIG_SYS_HUSH_PARSER
309
310 /* pass open firmware flat tree */
311 #define CONFIG_OF_LIBFDT 1
312 #define CONFIG_OF_BOARD_SETUP 1
313 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
314
315 /* I2C */
316 #define CONFIG_SYS_I2C
317 #define CONFIG_SYS_I2C_FSL
318 #define CONFIG_SYS_FSL_I2C_SPEED 400000
319 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
320 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
321 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
322
323 /*
324 * Config on-board RTC
325 */
326 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
327 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
328
329 /*
330 * General PCI
331 * Addresses are mapped 1-1.
332 */
333 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
334 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
335 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
336 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
337 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
338 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
339 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
340 #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
341 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
342
343 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
344 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
345 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
346
347
348 #ifdef CONFIG_PCI
349 #define CONFIG_PCI_INDIRECT_BRIDGE
350
351 #define CONFIG_PCI_PNP /* do pci plug-and-play */
352 #define CONFIG_83XX_PCI_STREAMING
353
354 #undef CONFIG_EEPRO100
355 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
356 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
357
358 #endif /* CONFIG_PCI */
359
360 /*
361 * QE UEC ethernet configuration
362 */
363 #define CONFIG_UEC_ETH
364 #define CONFIG_ETHPRIME "UEC0"
365
366 #define CONFIG_UEC_ETH1 /* ETH3 */
367
368 #ifdef CONFIG_UEC_ETH1
369 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
370 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
371 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
372 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
373 #define CONFIG_SYS_UEC1_PHY_ADDR 3
374 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
375 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
376 #endif
377
378 #define CONFIG_UEC_ETH2 /* ETH4 */
379
380 #ifdef CONFIG_UEC_ETH2
381 #define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
382 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
383 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
384 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
385 #define CONFIG_SYS_UEC2_PHY_ADDR 4
386 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
387 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
388 #endif
389
390 /*
391 * Environment
392 */
393 #ifndef CONFIG_SYS_RAMBOOT
394 #define CONFIG_ENV_IS_IN_FLASH 1
395 #define CONFIG_ENV_ADDR \
396 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
397 #define CONFIG_ENV_SECT_SIZE 0x20000
398 #define CONFIG_ENV_SIZE 0x2000
399 #else
400 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
401 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
402 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
403 #define CONFIG_ENV_SIZE 0x2000
404 #endif
405
406 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
407 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
408
409 /*
410 * BOOTP options
411 */
412 #define CONFIG_BOOTP_BOOTFILESIZE
413 #define CONFIG_BOOTP_BOOTPATH
414 #define CONFIG_BOOTP_GATEWAY
415 #define CONFIG_BOOTP_HOSTNAME
416
417
418 /*
419 * Command line configuration.
420 */
421 #define CONFIG_CMD_PING
422 #define CONFIG_CMD_I2C
423 #define CONFIG_CMD_ASKENV
424
425 #if defined(CONFIG_PCI)
426 #define CONFIG_CMD_PCI
427 #endif
428
429 #undef CONFIG_WATCHDOG /* watchdog disabled */
430
431 /*
432 * Miscellaneous configurable options
433 */
434 #define CONFIG_SYS_LONGHELP /* undef to save memory */
435 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
436
437 #if defined(CONFIG_CMD_KGDB)
438 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
439 #else
440 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
441 #endif
442
443 /* Print Buffer Size */
444 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
445 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
446 /* Boot Argument Buffer Size */
447 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
448
449 /*
450 * For booting Linux, the board info and command line data
451 * have to be in the first 256 MB of memory, since this is
452 * the maximum mapped by the Linux kernel during initialization.
453 */
454 /* Initial Memory map for Linux */
455 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
456
457 /*
458 * Core HID Setup
459 */
460 #define CONFIG_SYS_HID0_INIT 0x000000000
461 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
462 HID0_ENABLE_INSTRUCTION_CACHE)
463 #define CONFIG_SYS_HID2 HID2_HBE
464
465 /*
466 * MMU Setup
467 */
468
469 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
470
471 /* DDR: cache cacheable */
472 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
473 | BATL_PP_RW \
474 | BATL_MEMCOHERENCE)
475 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
476 | BATU_BL_256M \
477 | BATU_VS \
478 | BATU_VP)
479 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
480 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
481
482 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
483 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
484 | BATL_PP_RW \
485 | BATL_CACHEINHIBIT \
486 | BATL_GUARDEDSTORAGE)
487 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
488 | BATU_BL_4M \
489 | BATU_VS \
490 | BATU_VP)
491 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
492 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
493
494 /* BCSR: cache-inhibit and guarded */
495 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
496 | BATL_PP_RW \
497 | BATL_CACHEINHIBIT \
498 | BATL_GUARDEDSTORAGE)
499 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
500 | BATU_BL_128K \
501 | BATU_VS \
502 | BATU_VP)
503 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
504 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
505
506 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
507 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
508 | BATL_PP_RW \
509 | BATL_MEMCOHERENCE)
510 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
511 | BATU_BL_32M \
512 | BATU_VS \
513 | BATU_VP)
514 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
515 | BATL_PP_RW \
516 | BATL_CACHEINHIBIT \
517 | BATL_GUARDEDSTORAGE)
518 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
519
520 #define CONFIG_SYS_IBAT4L (0)
521 #define CONFIG_SYS_IBAT4U (0)
522 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
523 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
524
525 /* Stack in dcache: cacheable, no memory coherence */
526 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
527 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
528 | BATU_BL_128K \
529 | BATU_VS \
530 | BATU_VP)
531 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
532 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
533
534 #ifdef CONFIG_PCI
535 /* PCI MEM space: cacheable */
536 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
537 | BATL_PP_RW \
538 | BATL_MEMCOHERENCE)
539 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
540 | BATU_BL_256M \
541 | BATU_VS \
542 | BATU_VP)
543 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
544 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
545 /* PCI MMIO space: cache-inhibit and guarded */
546 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
547 | BATL_PP_RW \
548 | BATL_CACHEINHIBIT \
549 | BATL_GUARDEDSTORAGE)
550 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
551 | BATU_BL_256M \
552 | BATU_VS \
553 | BATU_VP)
554 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
555 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
556 #else
557 #define CONFIG_SYS_IBAT6L (0)
558 #define CONFIG_SYS_IBAT6U (0)
559 #define CONFIG_SYS_IBAT7L (0)
560 #define CONFIG_SYS_IBAT7U (0)
561 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
562 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
563 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
564 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
565 #endif
566
567 #if defined(CONFIG_CMD_KGDB)
568 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
569 #endif
570
571 /*
572 * Environment Configuration
573 */ #define CONFIG_ENV_OVERWRITE
574
575 #if defined(CONFIG_UEC_ETH)
576 #define CONFIG_HAS_ETH0
577 #define CONFIG_HAS_ETH1
578 #endif
579
580 #define CONFIG_BAUDRATE 115200
581
582 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
583
584 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
585 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
586
587 #define CONFIG_EXTRA_ENV_SETTINGS \
588 "netdev=eth0\0" \
589 "consoledev=ttyS0\0" \
590 "ramdiskaddr=1000000\0" \
591 "ramdiskfile=ramfs.83xx\0" \
592 "fdtaddr=780000\0" \
593 "fdtfile=mpc832x_mds.dtb\0" \
594 ""
595
596 #define CONFIG_NFSBOOTCOMMAND \
597 "setenv bootargs root=/dev/nfs rw " \
598 "nfsroot=$serverip:$rootpath " \
599 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
600 "$netdev:off " \
601 "console=$consoledev,$baudrate $othbootargs;" \
602 "tftp $loadaddr $bootfile;" \
603 "tftp $fdtaddr $fdtfile;" \
604 "bootm $loadaddr - $fdtaddr"
605
606 #define CONFIG_RAMBOOTCOMMAND \
607 "setenv bootargs root=/dev/ram rw " \
608 "console=$consoledev,$baudrate $othbootargs;" \
609 "tftp $ramdiskaddr $ramdiskfile;" \
610 "tftp $loadaddr $bootfile;" \
611 "tftp $fdtaddr $fdtfile;" \
612 "bootm $loadaddr $ramdiskaddr $fdtaddr"
613
614
615 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
616
617 #endif /* __CONFIG_H */