include/configs/MPC8349EMDS.h

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * mpc8349emds board configuration file
  26  *
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  */
  35 #define CONFIG_E300             1       /* E300 Family */
  36 #define CONFIG_MPC83xx          1       /* MPC83xx family */
  37 #define CONFIG_MPC834x          1       /* MPC834x family */
  38 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  39 #define CONFIG_MPC8349EMDS      1       /* MPC8349EMDS board specific */
  40
  41 #define PCI_66M
  42 #ifdef PCI_66M
  43 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  44 #else
  45 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  46 #endif
  47
  48 #ifdef CONFIG_PCISLAVE
  49 #define CONFIG_PCI
  50 #define CONFIG_83XX_PCICLK      66666666        /* in Hz */
  51 #endif /* CONFIG_PCISLAVE */
  52
  53 #ifndef CONFIG_SYS_CLK_FREQ
  54 #ifdef PCI_66M
  55 #define CONFIG_SYS_CLK_FREQ     66000000
  56 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  57 #else
  58 #define CONFIG_SYS_CLK_FREQ     33000000
  59 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  60 #endif
  61 #endif
  62
  63 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_pre_init */
  64
  65 #define CONFIG_SYS_IMMR         0xE0000000
  66
  67 #undef CONFIG_SYS_DRAM_TEST                             /* memory test, takes time */
  68 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  69 #define CONFIG_SYS_MEMTEST_END          0x00100000
  70
  71 /*
  72  * DDR Setup
  73  */
  74 #define CONFIG_DDR_ECC                  /* support DDR ECC function */
  75 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  76 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  77
  78 /*
  79  * 32-bit data path mode.
  80  *
  81  * Please note that using this mode for devices with the real density of 64-bit
  82  * effectively reduces the amount of available memory due to the effect of
  83  * wrapping around while translating address to row/columns, for example in the
  84  * 256MB module the upper 128MB get aliased with contents of the lower
  85  * 128MB); normally this define should be used for devices with real 32-bit
  86  * data path.
  87  */
  88 #undef CONFIG_DDR_32BIT
  89
  90 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
  91 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  92 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  93 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  94                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  95 #undef  CONFIG_DDR_2T_TIMING
  96
  97 /*
  98  * DDRCDR - DDR Control Driver Register
  99  */
 100 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
 101
 102 #if defined(CONFIG_SPD_EEPROM)
 103 /*
 104  * Determine DDR configuration from I2C interface.
 105  */
 106 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
 107 #else
 108 /*
 109  * Manually set up DDR parameters
 110  */
 111 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 112 #if defined(CONFIG_DDR_II)
 113 #define CONFIG_SYS_DDRCDR               0x80080001
 114 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
 115 #define CONFIG_SYS_DDR_CS2_CONFIG       0x80330102
 116 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
 117 #define CONFIG_SYS_DDR_TIMING_1 0x38357322
 118 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
 119 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 120 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
 121 #define CONFIG_SYS_DDR_MODE             0x47d00432
 122 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 123 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
 124 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 125 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 126 #else
 127 #define CONFIG_SYS_DDR_CONFIG           (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 128 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
 129 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 130 #define CONFIG_SYS_DDR_CONTROL          0xc2000000      /* unbuffered,no DYN_PWR */
 131 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
 132
 133 #if defined(CONFIG_DDR_32BIT)
 134 /* set burst length to 8 for 32-bit data path */
 135 #define CONFIG_SYS_DDR_MODE             0x00000023      /* DLL,normal,seq,4/2.5, 8 burst len */
 136 #else
 137 /* the default burst length is 4 - for 64-bit data path */
 138 #define CONFIG_SYS_DDR_MODE             0x00000022      /* DLL,normal,seq,4/2.5, 4 burst len */
 139 #endif
 140 #endif
 141 #endif
 142
 143 /*
 144  * SDRAM on the Local Bus
 145  */
 146 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
 147 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 148
 149 /*
 150  * FLASH on the Local Bus
 151  */
 152 #define CONFIG_SYS_FLASH_CFI                            /* use the Common Flash Interface */
 153 #define CONFIG_FLASH_CFI_DRIVER                 /* use the CFI driver */
 154 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 155 #define CONFIG_SYS_FLASH_SIZE           32              /* max flash size in MB */
 156 #define CONFIG_SYS_FLASH_PROTECTION     1               /* Use h/w Flash protection. */
 157 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 158
 159 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE |        /* flash Base address */ \
 160                                 (2 << BR_PS_SHIFT) |    /* 16 bit port size */   \
 161                                 BR_V)                   /* valid */
 162 #define CONFIG_SYS_OR0_PRELIM           ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 163                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 164                                 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 165 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE   /* window base at flash base */
 166 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000018      /* 32 MB window size */
 167
 168 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 169 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* max sectors per device */
 170
 171 #undef CONFIG_SYS_FLASH_CHECKSUM
 172 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 173 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 174
 175 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 176
 177 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 178 #define CONFIG_SYS_RAMBOOT
 179 #else
 180 #undef  CONFIG_SYS_RAMBOOT
 181 #endif
 182
 183 /*
 184  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
 185  */
 186 #define CONFIG_SYS_BCSR         0xE2400000
 187 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR         /* Access window base at BCSR base */
 188 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000E              /* Access window size 32K */
 189 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR|0x00000801)    /* Port-size=8bit, MSEL=GPCM */
 190 #define CONFIG_SYS_OR1_PRELIM           0xFFFFE8F0              /* length 32K */
 191
 192 #define CONFIG_SYS_INIT_RAM_LOCK        1
 193 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000              /* Initial RAM address */
 194 #define CONFIG_SYS_INIT_RAM_END 0x1000                  /* End of used area in RAM*/
 195
 196 #define CONFIG_SYS_GBL_DATA_SIZE        0x100                   /* num bytes initial data */
 197 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 198 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 199
 200 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)            /* Reserve 384 kB for Mon */
 201 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)            /* Reserved for malloc */
 202
 203 /*
 204  * Local Bus LCRR and LBCR regs
 205  *    LCRR:  DLL bypass, Clock divider is 4
 206  * External Local Bus rate is
 207  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 208  */
 209 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 210 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_4
 211 #define CONFIG_SYS_LBC_LBCR     0x00000000
 212
 213 /*
 214  * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
 215  * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
 216  */
 217 #undef CONFIG_SYS_LB_SDRAM
 218
 219 #ifdef CONFIG_SYS_LB_SDRAM
 220 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
 221 /*
 222  * Base Register 2 and Option Register 2 configure SDRAM.
 223  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 224  *
 225  * For BR2, need:
 226  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 227  *    port-size = 32-bits = BR2[19:20] = 11
 228  *    no parity checking = BR2[21:22] = 00
 229  *    SDRAM for MSEL = BR2[24:26] = 011
 230  *    Valid = BR[31] = 1
 231  *
 232  * 0    4    8    12   16   20   24   28
 233  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 234  *
 235  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 236  * FIXME: the top 17 bits of BR2.
 237  */
 238
 239 #define CONFIG_SYS_BR2_PRELIM           0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
 240 #define CONFIG_SYS_LBLAWBAR2_PRELIM     0xF0000000
 241 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000019 /* 64M */
 242
 243 /*
 244  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 245  *
 246  * For OR2, need:
 247  *    64MB mask for AM, OR2[0:7] = 1111 1100
 248  *                 XAM, OR2[17:18] = 11
 249  *    9 columns OR2[19-21] = 010
 250  *    13 rows   OR2[23-25] = 100
 251  *    EAD set for extra time OR[31] = 1
 252  *
 253  * 0    4    8    12   16   20   24   28
 254  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 255  */
 256
 257 #define CONFIG_SYS_OR2_PRELIM   0xFC006901
 258
 259 #define CONFIG_SYS_LBC_LSRT     0x32000000    /* LB sdram refresh timer, about 6us */
 260 #define CONFIG_SYS_LBC_MRTPR    0x20000000    /* LB refresh timer prescal, 266MHz/32 */
 261
 262 #define CONFIG_SYS_LBC_LSDMR_COMMON    ( LSDMR_RFEN            \
 263                                 | LSDMR_BSMA1516        \
 264                                 | LSDMR_RFCR8           \
 265                                 | LSDMR_PRETOACT6       \
 266                                 | LSDMR_ACTTORW3        \
 267                                 | LSDMR_BL8             \
 268                                 | LSDMR_WRC3            \
 269                                 | LSDMR_CL3             \
 270                                 )
 271
 272 /*
 273  * SDRAM Controller configuration sequence.
 274  */
 275 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 276 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 277 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 278 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 279 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 280 #endif
 281
 282 /*
 283  * Serial Port
 284  */
 285 #define CONFIG_CONS_INDEX     1
 286 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 287 #define CONFIG_SYS_NS16550
 288 #define CONFIG_SYS_NS16550_SERIAL
 289 #define CONFIG_SYS_NS16550_REG_SIZE    1
 290 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 291
 292 #define CONFIG_SYS_BAUDRATE_TABLE  \
 293         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 294
 295 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 296 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 297
 298 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 299 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 300 /* Use the HUSH parser */
 301 #define CONFIG_SYS_HUSH_PARSER
 302 #ifdef  CONFIG_SYS_HUSH_PARSER
 303 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 304 #endif
 305
 306 /* pass open firmware flat tree */
 307 #define CONFIG_OF_LIBFDT        1
 308 #define CONFIG_OF_BOARD_SETUP   1
 309 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 310
 311 /* I2C */
 312 #define CONFIG_HARD_I2C                 /* I2C with hardware support*/
 313 #undef CONFIG_SOFT_I2C                  /* I2C bit-banged */
 314 #define CONFIG_FSL_I2C
 315 #define CONFIG_I2C_MULTI_BUS
 316 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 317 #define CONFIG_SYS_I2C_SLAVE            0x7F
 318 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}      /* Don't probe these addrs */
 319 #define CONFIG_SYS_I2C_OFFSET           0x3000
 320 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 321
 322 /* SPI */
 323 #define CONFIG_MPC8XXX_SPI
 324 #undef CONFIG_SOFT_SPI                  /* SPI bit-banged */
 325
 326 /* GPIOs.  Used as SPI chip selects */
 327 #define CONFIG_SYS_GPIO1_PRELIM
 328 #define CONFIG_SYS_GPIO1_DIR            0xC0000000  /* SPI CS on 0, LED on 1 */
 329 #define CONFIG_SYS_GPIO1_DAT            0xC0000000  /* Both are active LOW */
 330
 331 /* TSEC */
 332 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 333 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 334 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 335 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 336
 337 /* USB */
 338 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY       1 /* Use SYS board PHY */
 339
 340 /*
 341  * General PCI
 342  * Addresses are mapped 1-1.
 343  */
 344 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 345 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 346 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 347 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 348 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 349 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 350 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 351 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 352 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 353
 354 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 355 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 356 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 357 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 358 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 359 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 360 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
 361 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
 362 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 363
 364 #if defined(CONFIG_PCI)
 365
 366 #define PCI_ONE_PCI1
 367 #if defined(PCI_64BIT)
 368 #undef PCI_ALL_PCI1
 369 #undef PCI_TWO_PCI1
 370 #undef PCI_ONE_PCI1
 371 #endif
 372
 373 #define CONFIG_NET_MULTI
 374 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 375 #define CONFIG_83XX_PCI_STREAMING
 376
 377 #undef CONFIG_EEPRO100
 378 #undef CONFIG_TULIP
 379
 380 #if !defined(CONFIG_PCI_PNP)
 381         #define PCI_ENET0_IOADDR        0xFIXME
 382         #define PCI_ENET0_MEMADDR       0xFIXME
 383         #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 384 #endif
 385
 386 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 387 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 388
 389 #endif  /* CONFIG_PCI */
 390
 391 /*
 392  * TSEC configuration
 393  */
 394 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 395
 396 #if defined(CONFIG_TSEC_ENET)
 397 #ifndef CONFIG_NET_MULTI
 398 #define CONFIG_NET_MULTI        1
 399 #endif
 400
 401 #define CONFIG_GMII             1       /* MII PHY management */
 402 #define CONFIG_TSEC1    1
 403 #define CONFIG_TSEC1_NAME       "TSEC0"
 404 #define CONFIG_TSEC2    1
 405 #define CONFIG_TSEC2_NAME       "TSEC1"
 406 #define TSEC1_PHY_ADDR          0
 407 #define TSEC2_PHY_ADDR          1
 408 #define TSEC1_PHYIDX            0
 409 #define TSEC2_PHYIDX            0
 410 #define TSEC1_FLAGS             TSEC_GIGABIT
 411 #define TSEC2_FLAGS             TSEC_GIGABIT
 412
 413 /* Options are: TSEC[0-1] */
 414 #define CONFIG_ETHPRIME         "TSEC0"
 415
 416 #endif  /* CONFIG_TSEC_ENET */
 417
 418 /*
 419  * Configure on-board RTC
 420  */
 421 #define CONFIG_RTC_DS1374                       /* use ds1374 rtc via i2c       */
 422 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68              */
 423
 424 /*
 425  * Environment
 426  */
 427 #ifndef CONFIG_SYS_RAMBOOT
 428         #define CONFIG_ENV_IS_IN_FLASH  1
 429         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 430         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 431         #define CONFIG_ENV_SIZE         0x2000
 432
 433 /* Address and size of Redundant Environment Sector     */
 434 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 435 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 436
 437 #else
 438         #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 439         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 440         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 441         #define CONFIG_ENV_SIZE         0x2000
 442 #endif
 443
 444 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 445 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 446
 447
 448 /*
 449  * BOOTP options
 450  */
 451 #define CONFIG_BOOTP_BOOTFILESIZE
 452 #define CONFIG_BOOTP_BOOTPATH
 453 #define CONFIG_BOOTP_GATEWAY
 454 #define CONFIG_BOOTP_HOSTNAME
 455
 456
 457 /*
 458  * Command line configuration.
 459  */
 460 #include <config_cmd_default.h>
 461
 462 #define CONFIG_CMD_PING
 463 #define CONFIG_CMD_I2C
 464 #define CONFIG_CMD_DATE
 465 #define CONFIG_CMD_MII
 466
 467 #if defined(CONFIG_PCI)
 468     #define CONFIG_CMD_PCI
 469 #endif
 470
 471 #if defined(CONFIG_SYS_RAMBOOT)
 472     #undef CONFIG_CMD_SAVEENV
 473     #undef CONFIG_CMD_LOADS
 474 #endif
 475
 476
 477 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 478
 479 /*
 480  * Miscellaneous configurable options
 481  */
 482 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 483 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 484 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 485
 486 #if defined(CONFIG_CMD_KGDB)
 487         #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 488 #else
 489         #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 490 #endif
 491
 492 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 493 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 494 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 495 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 496
 497 /*
 498  * For booting Linux, the board info and command line data
 499  * have to be in the first 8 MB of memory, since this is
 500  * the maximum mapped by the Linux kernel during initialization.
 501  */
 502 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 503
 504 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 505
 506 #if 1 /*528/264*/
 507 #define CONFIG_SYS_HRCW_LOW (\
 508         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 509         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 510         HRCWL_CSB_TO_CLKIN |\
 511         HRCWL_VCO_1X2 |\
 512         HRCWL_CORE_TO_CSB_2X1)
 513 #elif 0 /*396/132*/
 514 #define CONFIG_SYS_HRCW_LOW (\
 515         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 516         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 517         HRCWL_CSB_TO_CLKIN |\
 518         HRCWL_VCO_1X4 |\
 519         HRCWL_CORE_TO_CSB_3X1)
 520 #elif 0 /*264/132*/
 521 #define CONFIG_SYS_HRCW_LOW (\
 522         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 523         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 524         HRCWL_CSB_TO_CLKIN |\
 525         HRCWL_VCO_1X4 |\
 526         HRCWL_CORE_TO_CSB_2X1)
 527 #elif 0 /*132/132*/
 528 #define CONFIG_SYS_HRCW_LOW (\
 529         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 530         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 531         HRCWL_CSB_TO_CLKIN |\
 532         HRCWL_VCO_1X4 |\
 533         HRCWL_CORE_TO_CSB_1X1)
 534 #elif 0 /*264/264 */
 535 #define CONFIG_SYS_HRCW_LOW (\
 536         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 537         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 538         HRCWL_CSB_TO_CLKIN |\
 539         HRCWL_VCO_1X4 |\
 540         HRCWL_CORE_TO_CSB_1X1)
 541 #endif
 542
 543 #ifdef CONFIG_PCISLAVE
 544 #define CONFIG_SYS_HRCW_HIGH (\
 545         HRCWH_PCI_AGENT |\
 546         HRCWH_64_BIT_PCI |\
 547         HRCWH_PCI1_ARBITER_DISABLE |\
 548         HRCWH_PCI2_ARBITER_DISABLE |\
 549         HRCWH_CORE_ENABLE |\
 550         HRCWH_FROM_0X00000100 |\
 551         HRCWH_BOOTSEQ_DISABLE |\
 552         HRCWH_SW_WATCHDOG_DISABLE |\
 553         HRCWH_ROM_LOC_LOCAL_16BIT |\
 554         HRCWH_TSEC1M_IN_GMII |\
 555         HRCWH_TSEC2M_IN_GMII )
 556 #else
 557 #if defined(PCI_64BIT)
 558 #define CONFIG_SYS_HRCW_HIGH (\
 559         HRCWH_PCI_HOST |\
 560         HRCWH_64_BIT_PCI |\
 561         HRCWH_PCI1_ARBITER_ENABLE |\
 562         HRCWH_PCI2_ARBITER_DISABLE |\
 563         HRCWH_CORE_ENABLE |\
 564         HRCWH_FROM_0X00000100 |\
 565         HRCWH_BOOTSEQ_DISABLE |\
 566         HRCWH_SW_WATCHDOG_DISABLE |\
 567         HRCWH_ROM_LOC_LOCAL_16BIT |\
 568         HRCWH_TSEC1M_IN_GMII |\
 569         HRCWH_TSEC2M_IN_GMII )
 570 #else
 571 #define CONFIG_SYS_HRCW_HIGH (\
 572         HRCWH_PCI_HOST |\
 573         HRCWH_32_BIT_PCI |\
 574         HRCWH_PCI1_ARBITER_ENABLE |\
 575         HRCWH_PCI2_ARBITER_ENABLE |\
 576         HRCWH_CORE_ENABLE |\
 577         HRCWH_FROM_0X00000100 |\
 578         HRCWH_BOOTSEQ_DISABLE |\
 579         HRCWH_SW_WATCHDOG_DISABLE |\
 580         HRCWH_ROM_LOC_LOCAL_16BIT |\
 581         HRCWH_TSEC1M_IN_GMII |\
 582         HRCWH_TSEC2M_IN_GMII )
 583 #endif /* PCI_64BIT */
 584 #endif /* CONFIG_PCISLAVE */
 585
 586 /*
 587  * System performance
 588  */
 589 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 590 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
 591 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 592 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 593 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 594 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 595
 596 /* System IO Config */
 597 #define CONFIG_SYS_SICRH 0
 598 #define CONFIG_SYS_SICRL SICRL_LDP_A
 599
 600 #define CONFIG_SYS_HID0_INIT    0x000000000
 601 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 602                                  HID0_ENABLE_INSTRUCTION_CACHE)
 603
 604 /* #define CONFIG_SYS_HID0_FINAL                (\
 605         HID0_ENABLE_INSTRUCTION_CACHE |\
 606         HID0_ENABLE_M_BIT |\
 607         HID0_ENABLE_ADDRESS_BROADCAST ) */
 608
 609
 610 #define CONFIG_SYS_HID2 HID2_HBE
 611 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 612
 613 /* DDR @ 0x00000000 */
 614 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 615 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 616
 617 /* PCI @ 0x80000000 */
 618 #ifdef CONFIG_PCI
 619 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 620 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 621 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 622 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 623 #else
 624 #define CONFIG_SYS_IBAT1L       (0)
 625 #define CONFIG_SYS_IBAT1U       (0)
 626 #define CONFIG_SYS_IBAT2L       (0)
 627 #define CONFIG_SYS_IBAT2U       (0)
 628 #endif
 629
 630 #ifdef CONFIG_MPC83XX_PCI2
 631 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 632 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 633 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 634 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 635 #else
 636 #define CONFIG_SYS_IBAT3L       (0)
 637 #define CONFIG_SYS_IBAT3U       (0)
 638 #define CONFIG_SYS_IBAT4L       (0)
 639 #define CONFIG_SYS_IBAT4U       (0)
 640 #endif
 641
 642 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 643 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 644 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 645
 646 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 647 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
 648                                  BATL_GUARDEDSTORAGE)
 649 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 650
 651 #define CONFIG_SYS_IBAT7L       (0)
 652 #define CONFIG_SYS_IBAT7U       (0)
 653
 654 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 655 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 656 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 657 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 658 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 659 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 660 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 661 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 662 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 663 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 664 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 665 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 666 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 667 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 668 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 669 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 670
 671 /*
 672  * Internal Definitions
 673  *
 674  * Boot Flags
 675  */
 676 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH */
 677 #define BOOTFLAG_WARM   0x02    /* Software reboot */
 678
 679 #if defined(CONFIG_CMD_KGDB)
 680 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 681 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 682 #endif
 683
 684 /*
 685  * Environment Configuration
 686  */
 687 #define CONFIG_ENV_OVERWRITE
 688
 689 #if defined(CONFIG_TSEC_ENET)
 690 #define CONFIG_HAS_ETH1
 691 #define CONFIG_HAS_ETH0
 692 #endif
 693
 694 #define CONFIG_HOSTNAME         mpc8349emds
 695 #define CONFIG_ROOTPATH         /nfsroot/rootfs
 696 #define CONFIG_BOOTFILE         uImage
 697
 698 #define CONFIG_LOADADDR         800000  /* default location for tftp and bootm */
 699
 700 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 701 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 702
 703 #define CONFIG_BAUDRATE  115200
 704
 705 #define CONFIG_PREBOOT  "echo;" \
 706         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 707         "echo"
 708
 709 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 710         "netdev=eth0\0"                                                 \
 711         "hostname=mpc8349emds\0"                                        \
 712         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 713                 "nfsroot=${serverip}:${rootpath}\0"                     \
 714         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 715         "addip=setenv bootargs ${bootargs} "                            \
 716                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 717                 ":${hostname}:${netdev}:off panic=1\0"                  \
 718         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 719         "flash_nfs=run nfsargs addip addtty;"                           \
 720                 "bootm ${kernel_addr}\0"                                \
 721         "flash_self=run ramargs addip addtty;"                          \
 722                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 723         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 724                 "bootm\0"                                               \
 725         "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"           \
 726         "update=protect off fe000000 fe03ffff; "                        \
 727                 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"     \
 728         "upd=run load update\0"                                         \
 729         "fdtaddr=780000\0"                                              \
 730         "fdtfile=mpc834x_mds.dtb\0"                                     \
 731         ""
 732
 733 #define CONFIG_NFSBOOTCOMMAND                                           \
 734    "setenv bootargs root=/dev/nfs rw "                                  \
 735       "nfsroot=$serverip:$rootpath "                                    \
 736       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 737       "console=$consoledev,$baudrate $othbootargs;"                     \
 738    "tftp $loadaddr $bootfile;"                                          \
 739    "tftp $fdtaddr $fdtfile;"                                            \
 740    "bootm $loadaddr - $fdtaddr"
 741
 742 #define CONFIG_RAMBOOTCOMMAND                                           \
 743    "setenv bootargs root=/dev/ram rw "                                  \
 744       "console=$consoledev,$baudrate $othbootargs;"                     \
 745    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 746    "tftp $loadaddr $bootfile;"                                          \
 747    "tftp $fdtaddr $fdtfile;"                                            \
 748    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 749
 750 #define CONFIG_BOOTCOMMAND      "run flash_self"
 751
 752 #endif  /* __CONFIG_H */