include/configs/MPC8349EMDS.h

   1 /*
   2  * (C) Copyright 2006-2010
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * mpc8349emds board configuration file
  26  *
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  */
  35 #define CONFIG_E300             1       /* E300 Family */
  36 #define CONFIG_MPC83xx          1       /* MPC83xx family */
  37 #define CONFIG_MPC834x          1       /* MPC834x family */
  38 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  39 #define CONFIG_MPC8349EMDS      1       /* MPC8349EMDS board specific */
  40
  41 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  42
  43 #define CONFIG_PCI_66M
  44 #ifdef CONFIG_PCI_66M
  45 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  46 #else
  47 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  48 #endif
  49
  50 #ifdef CONFIG_PCISLAVE
  51 #define CONFIG_PCI
  52 #define CONFIG_83XX_PCICLK      66666666        /* in Hz */
  53 #endif /* CONFIG_PCISLAVE */
  54
  55 #ifndef CONFIG_SYS_CLK_FREQ
  56 #ifdef CONFIG_PCI_66M
  57 #define CONFIG_SYS_CLK_FREQ     66000000
  58 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  59 #else
  60 #define CONFIG_SYS_CLK_FREQ     33000000
  61 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  62 #endif
  63 #endif
  64
  65 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_pre_init */
  66
  67 #define CONFIG_SYS_IMMR         0xE0000000
  68
  69 #undef CONFIG_SYS_DRAM_TEST                             /* memory test, takes time */
  70 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  71 #define CONFIG_SYS_MEMTEST_END          0x00100000
  72
  73 /*
  74  * DDR Setup
  75  */
  76 #define CONFIG_DDR_ECC                  /* support DDR ECC function */
  77 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  78 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  79
  80 /*
  81  * define CONFIG_FSL_DDR2 to use unified DDR driver
  82  * undefine it to use old spd_sdram.c
  83  */
  84 #define CONFIG_FSL_DDR2
  85 #ifdef CONFIG_FSL_DDR2
  86 #define CONFIG_SYS_SPD_BUS_NUM  0
  87 #define SPD_EEPROM_ADDRESS1     0x52
  88 #define SPD_EEPROM_ADDRESS2     0x51
  89 #define CONFIG_NUM_DDR_CONTROLLERS      1
  90 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
  91 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  92 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  93 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  94 #endif
  95
  96 /*
  97  * 32-bit data path mode.
  98  *
  99  * Please note that using this mode for devices with the real density of 64-bit
 100  * effectively reduces the amount of available memory due to the effect of
 101  * wrapping around while translating address to row/columns, for example in the
 102  * 256MB module the upper 128MB get aliased with contents of the lower
 103  * 128MB); normally this define should be used for devices with real 32-bit
 104  * data path.
 105  */
 106 #undef CONFIG_DDR_32BIT
 107
 108 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
 109 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 110 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 111 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
 112                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 113 #undef  CONFIG_DDR_2T_TIMING
 114
 115 /*
 116  * DDRCDR - DDR Control Driver Register
 117  */
 118 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
 119
 120 #if defined(CONFIG_SPD_EEPROM)
 121 /*
 122  * Determine DDR configuration from I2C interface.
 123  */
 124 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
 125 #else
 126 /*
 127  * Manually set up DDR parameters
 128  */
 129 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 130 #if defined(CONFIG_DDR_II)
 131 #define CONFIG_SYS_DDRCDR               0x80080001
 132 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
 133 #define CONFIG_SYS_DDR_CS2_CONFIG       0x80330102
 134 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
 135 #define CONFIG_SYS_DDR_TIMING_1 0x38357322
 136 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
 137 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 138 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
 139 #define CONFIG_SYS_DDR_MODE             0x47d00432
 140 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 141 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
 142 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 143 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 144 #else
 145 #define CONFIG_SYS_DDR_CONFIG           (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 146 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
 147 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 148 #define CONFIG_SYS_DDR_CONTROL          0xc2000000      /* unbuffered,no DYN_PWR */
 149 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
 150
 151 #if defined(CONFIG_DDR_32BIT)
 152 /* set burst length to 8 for 32-bit data path */
 153 #define CONFIG_SYS_DDR_MODE             0x00000023      /* DLL,normal,seq,4/2.5, 8 burst len */
 154 #else
 155 /* the default burst length is 4 - for 64-bit data path */
 156 #define CONFIG_SYS_DDR_MODE             0x00000022      /* DLL,normal,seq,4/2.5, 4 burst len */
 157 #endif
 158 #endif
 159 #endif
 160
 161 /*
 162  * SDRAM on the Local Bus
 163  */
 164 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
 165 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 166
 167 /*
 168  * FLASH on the Local Bus
 169  */
 170 #define CONFIG_SYS_FLASH_CFI                            /* use the Common Flash Interface */
 171 #define CONFIG_FLASH_CFI_DRIVER                 /* use the CFI driver */
 172 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 173 #define CONFIG_SYS_FLASH_SIZE           32              /* max flash size in MB */
 174 #define CONFIG_SYS_FLASH_PROTECTION     1               /* Use h/w Flash protection. */
 175 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 176
 177 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE |        /* flash Base address */ \
 178                                 (2 << BR_PS_SHIFT) |    /* 16 bit port size */   \
 179                                 BR_V)                   /* valid */
 180 #define CONFIG_SYS_OR0_PRELIM           ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 181                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 182                                 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 183 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE   /* window base at flash base */
 184 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000018      /* 32 MB window size */
 185
 186 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 187 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* max sectors per device */
 188
 189 #undef CONFIG_SYS_FLASH_CHECKSUM
 190 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 191 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 192
 193 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 194
 195 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 196 #define CONFIG_SYS_RAMBOOT
 197 #else
 198 #undef  CONFIG_SYS_RAMBOOT
 199 #endif
 200
 201 /*
 202  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
 203  */
 204 #define CONFIG_SYS_BCSR         0xE2400000
 205 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR         /* Access window base at BCSR base */
 206 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000E              /* Access window size 32K */
 207 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR|0x00000801)    /* Port-size=8bit, MSEL=GPCM */
 208 #define CONFIG_SYS_OR1_PRELIM           0xFFFFE8F0              /* length 32K */
 209
 210 #define CONFIG_SYS_INIT_RAM_LOCK        1
 211 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000              /* Initial RAM address */
 212 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000                  /* Size of used area in RAM*/
 213
 214 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 215 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 216
 217 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)            /* Reserve 384 kB for Mon */
 218 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)            /* Reserved for malloc */
 219
 220 /*
 221  * Local Bus LCRR and LBCR regs
 222  *    LCRR:  DLL bypass, Clock divider is 4
 223  * External Local Bus rate is
 224  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 225  */
 226 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 227 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_4
 228 #define CONFIG_SYS_LBC_LBCR     0x00000000
 229
 230 /*
 231  * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
 232  * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
 233  */
 234 #undef CONFIG_SYS_LB_SDRAM
 235
 236 #ifdef CONFIG_SYS_LB_SDRAM
 237 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
 238 /*
 239  * Base Register 2 and Option Register 2 configure SDRAM.
 240  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 241  *
 242  * For BR2, need:
 243  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 244  *    port-size = 32-bits = BR2[19:20] = 11
 245  *    no parity checking = BR2[21:22] = 00
 246  *    SDRAM for MSEL = BR2[24:26] = 011
 247  *    Valid = BR[31] = 1
 248  *
 249  * 0    4    8    12   16   20   24   28
 250  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 251  *
 252  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 253  * FIXME: the top 17 bits of BR2.
 254  */
 255
 256 #define CONFIG_SYS_BR2_PRELIM           0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
 257 #define CONFIG_SYS_LBLAWBAR2_PRELIM     0xF0000000
 258 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000019 /* 64M */
 259
 260 /*
 261  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 262  *
 263  * For OR2, need:
 264  *    64MB mask for AM, OR2[0:7] = 1111 1100
 265  *                 XAM, OR2[17:18] = 11
 266  *    9 columns OR2[19-21] = 010
 267  *    13 rows   OR2[23-25] = 100
 268  *    EAD set for extra time OR[31] = 1
 269  *
 270  * 0    4    8    12   16   20   24   28
 271  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 272  */
 273
 274 #define CONFIG_SYS_OR2_PRELIM   0xFC006901
 275
 276 #define CONFIG_SYS_LBC_LSRT     0x32000000    /* LB sdram refresh timer, about 6us */
 277 #define CONFIG_SYS_LBC_MRTPR    0x20000000    /* LB refresh timer prescal, 266MHz/32 */
 278
 279 #define CONFIG_SYS_LBC_LSDMR_COMMON    ( LSDMR_RFEN            \
 280                                 | LSDMR_BSMA1516        \
 281                                 | LSDMR_RFCR8           \
 282                                 | LSDMR_PRETOACT6       \
 283                                 | LSDMR_ACTTORW3        \
 284                                 | LSDMR_BL8             \
 285                                 | LSDMR_WRC3            \
 286                                 | LSDMR_CL3             \
 287                                 )
 288
 289 /*
 290  * SDRAM Controller configuration sequence.
 291  */
 292 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 293 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 294 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 295 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 296 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 297 #endif
 298
 299 /*
 300  * Serial Port
 301  */
 302 #define CONFIG_CONS_INDEX     1
 303 #define CONFIG_SYS_NS16550
 304 #define CONFIG_SYS_NS16550_SERIAL
 305 #define CONFIG_SYS_NS16550_REG_SIZE    1
 306 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 307
 308 #define CONFIG_SYS_BAUDRATE_TABLE  \
 309         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 310
 311 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 312 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 313
 314 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 315 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 316 /* Use the HUSH parser */
 317 #define CONFIG_SYS_HUSH_PARSER
 318 #ifdef  CONFIG_SYS_HUSH_PARSER
 319 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 320 #endif
 321
 322 /* pass open firmware flat tree */
 323 #define CONFIG_OF_LIBFDT        1
 324 #define CONFIG_OF_BOARD_SETUP   1
 325 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 326
 327 /* I2C */
 328 #define CONFIG_HARD_I2C                 /* I2C with hardware support*/
 329 #undef CONFIG_SOFT_I2C                  /* I2C bit-banged */
 330 #define CONFIG_FSL_I2C
 331 #define CONFIG_I2C_MULTI_BUS
 332 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 333 #define CONFIG_SYS_I2C_SLAVE            0x7F
 334 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}      /* Don't probe these addrs */
 335 #define CONFIG_SYS_I2C_OFFSET           0x3000
 336 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 337
 338 /* SPI */
 339 #define CONFIG_MPC8XXX_SPI
 340 #undef CONFIG_SOFT_SPI                  /* SPI bit-banged */
 341
 342 /* GPIOs.  Used as SPI chip selects */
 343 #define CONFIG_SYS_GPIO1_PRELIM
 344 #define CONFIG_SYS_GPIO1_DIR            0xC0000000  /* SPI CS on 0, LED on 1 */
 345 #define CONFIG_SYS_GPIO1_DAT            0xC0000000  /* Both are active LOW */
 346
 347 /* TSEC */
 348 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 349 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 350 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 351 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 352
 353 /* USB */
 354 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY       1 /* Use SYS board PHY */
 355
 356 /*
 357  * General PCI
 358  * Addresses are mapped 1-1.
 359  */
 360 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 361 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 362 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 363 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 364 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 365 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 366 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 367 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 368 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 369
 370 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 371 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 372 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 373 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 374 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 375 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 376 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
 377 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
 378 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 379
 380 #if defined(CONFIG_PCI)
 381
 382 #define PCI_ONE_PCI1
 383 #if defined(PCI_64BIT)
 384 #undef PCI_ALL_PCI1
 385 #undef PCI_TWO_PCI1
 386 #undef PCI_ONE_PCI1
 387 #endif
 388
 389 #define CONFIG_NET_MULTI
 390 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 391 #define CONFIG_83XX_PCI_STREAMING
 392
 393 #undef CONFIG_EEPRO100
 394 #undef CONFIG_TULIP
 395
 396 #if !defined(CONFIG_PCI_PNP)
 397         #define PCI_ENET0_IOADDR        0xFIXME
 398         #define PCI_ENET0_MEMADDR       0xFIXME
 399         #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 400 #endif
 401
 402 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 403 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 404
 405 #endif  /* CONFIG_PCI */
 406
 407 /*
 408  * TSEC configuration
 409  */
 410 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 411
 412 #if defined(CONFIG_TSEC_ENET)
 413 #ifndef CONFIG_NET_MULTI
 414 #define CONFIG_NET_MULTI        1
 415 #endif
 416
 417 #define CONFIG_GMII             1       /* MII PHY management */
 418 #define CONFIG_TSEC1    1
 419 #define CONFIG_TSEC1_NAME       "TSEC0"
 420 #define CONFIG_TSEC2    1
 421 #define CONFIG_TSEC2_NAME       "TSEC1"
 422 #define TSEC1_PHY_ADDR          0
 423 #define TSEC2_PHY_ADDR          1
 424 #define TSEC1_PHYIDX            0
 425 #define TSEC2_PHYIDX            0
 426 #define TSEC1_FLAGS             TSEC_GIGABIT
 427 #define TSEC2_FLAGS             TSEC_GIGABIT
 428
 429 /* Options are: TSEC[0-1] */
 430 #define CONFIG_ETHPRIME         "TSEC0"
 431
 432 #endif  /* CONFIG_TSEC_ENET */
 433
 434 /*
 435  * Configure on-board RTC
 436  */
 437 #define CONFIG_RTC_DS1374                       /* use ds1374 rtc via i2c       */
 438 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68              */
 439
 440 /*
 441  * Environment
 442  */
 443 #ifndef CONFIG_SYS_RAMBOOT
 444         #define CONFIG_ENV_IS_IN_FLASH  1
 445         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 446         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 447         #define CONFIG_ENV_SIZE         0x2000
 448
 449 /* Address and size of Redundant Environment Sector     */
 450 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 451 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 452
 453 #else
 454         #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 455         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 456         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 457         #define CONFIG_ENV_SIZE         0x2000
 458 #endif
 459
 460 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 461 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 462
 463
 464 /*
 465  * BOOTP options
 466  */
 467 #define CONFIG_BOOTP_BOOTFILESIZE
 468 #define CONFIG_BOOTP_BOOTPATH
 469 #define CONFIG_BOOTP_GATEWAY
 470 #define CONFIG_BOOTP_HOSTNAME
 471
 472
 473 /*
 474  * Command line configuration.
 475  */
 476 #include <config_cmd_default.h>
 477
 478 #define CONFIG_CMD_PING
 479 #define CONFIG_CMD_I2C
 480 #define CONFIG_CMD_DATE
 481 #define CONFIG_CMD_MII
 482
 483 #if defined(CONFIG_PCI)
 484     #define CONFIG_CMD_PCI
 485 #endif
 486
 487 #if defined(CONFIG_SYS_RAMBOOT)
 488     #undef CONFIG_CMD_SAVEENV
 489     #undef CONFIG_CMD_LOADS
 490 #endif
 491
 492
 493 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 494
 495 /*
 496  * Miscellaneous configurable options
 497  */
 498 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 499 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 500 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 501
 502 #if defined(CONFIG_CMD_KGDB)
 503         #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 504 #else
 505         #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 506 #endif
 507
 508 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 509 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 510 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 511 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 512
 513 /*
 514  * For booting Linux, the board info and command line data
 515  * have to be in the first 256 MB of memory, since this is
 516  * the maximum mapped by the Linux kernel during initialization.
 517  */
 518 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
 519
 520 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 521
 522 #if 1 /*528/264*/
 523 #define CONFIG_SYS_HRCW_LOW (\
 524         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 525         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 526         HRCWL_CSB_TO_CLKIN |\
 527         HRCWL_VCO_1X2 |\
 528         HRCWL_CORE_TO_CSB_2X1)
 529 #elif 0 /*396/132*/
 530 #define CONFIG_SYS_HRCW_LOW (\
 531         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 532         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 533         HRCWL_CSB_TO_CLKIN |\
 534         HRCWL_VCO_1X4 |\
 535         HRCWL_CORE_TO_CSB_3X1)
 536 #elif 0 /*264/132*/
 537 #define CONFIG_SYS_HRCW_LOW (\
 538         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 539         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 540         HRCWL_CSB_TO_CLKIN |\
 541         HRCWL_VCO_1X4 |\
 542         HRCWL_CORE_TO_CSB_2X1)
 543 #elif 0 /*132/132*/
 544 #define CONFIG_SYS_HRCW_LOW (\
 545         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 546         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 547         HRCWL_CSB_TO_CLKIN |\
 548         HRCWL_VCO_1X4 |\
 549         HRCWL_CORE_TO_CSB_1X1)
 550 #elif 0 /*264/264 */
 551 #define CONFIG_SYS_HRCW_LOW (\
 552         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 553         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 554         HRCWL_CSB_TO_CLKIN |\
 555         HRCWL_VCO_1X4 |\
 556         HRCWL_CORE_TO_CSB_1X1)
 557 #endif
 558
 559 #ifdef CONFIG_PCISLAVE
 560 #define CONFIG_SYS_HRCW_HIGH (\
 561         HRCWH_PCI_AGENT |\
 562         HRCWH_64_BIT_PCI |\
 563         HRCWH_PCI1_ARBITER_DISABLE |\
 564         HRCWH_PCI2_ARBITER_DISABLE |\
 565         HRCWH_CORE_ENABLE |\
 566         HRCWH_FROM_0X00000100 |\
 567         HRCWH_BOOTSEQ_DISABLE |\
 568         HRCWH_SW_WATCHDOG_DISABLE |\
 569         HRCWH_ROM_LOC_LOCAL_16BIT |\
 570         HRCWH_TSEC1M_IN_GMII |\
 571         HRCWH_TSEC2M_IN_GMII )
 572 #else
 573 #if defined(PCI_64BIT)
 574 #define CONFIG_SYS_HRCW_HIGH (\
 575         HRCWH_PCI_HOST |\
 576         HRCWH_64_BIT_PCI |\
 577         HRCWH_PCI1_ARBITER_ENABLE |\
 578         HRCWH_PCI2_ARBITER_DISABLE |\
 579         HRCWH_CORE_ENABLE |\
 580         HRCWH_FROM_0X00000100 |\
 581         HRCWH_BOOTSEQ_DISABLE |\
 582         HRCWH_SW_WATCHDOG_DISABLE |\
 583         HRCWH_ROM_LOC_LOCAL_16BIT |\
 584         HRCWH_TSEC1M_IN_GMII |\
 585         HRCWH_TSEC2M_IN_GMII )
 586 #else
 587 #define CONFIG_SYS_HRCW_HIGH (\
 588         HRCWH_PCI_HOST |\
 589         HRCWH_32_BIT_PCI |\
 590         HRCWH_PCI1_ARBITER_ENABLE |\
 591         HRCWH_PCI2_ARBITER_ENABLE |\
 592         HRCWH_CORE_ENABLE |\
 593         HRCWH_FROM_0X00000100 |\
 594         HRCWH_BOOTSEQ_DISABLE |\
 595         HRCWH_SW_WATCHDOG_DISABLE |\
 596         HRCWH_ROM_LOC_LOCAL_16BIT |\
 597         HRCWH_TSEC1M_IN_GMII |\
 598         HRCWH_TSEC2M_IN_GMII )
 599 #endif /* PCI_64BIT */
 600 #endif /* CONFIG_PCISLAVE */
 601
 602 /*
 603  * System performance
 604  */
 605 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 606 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
 607 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 608 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 609 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 610 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 611
 612 /* System IO Config */
 613 #define CONFIG_SYS_SICRH 0
 614 #define CONFIG_SYS_SICRL SICRL_LDP_A
 615
 616 #define CONFIG_SYS_HID0_INIT    0x000000000
 617 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 618                                  HID0_ENABLE_INSTRUCTION_CACHE)
 619
 620 /* #define CONFIG_SYS_HID0_FINAL                (\
 621         HID0_ENABLE_INSTRUCTION_CACHE |\
 622         HID0_ENABLE_M_BIT |\
 623         HID0_ENABLE_ADDRESS_BROADCAST ) */
 624
 625
 626 #define CONFIG_SYS_HID2 HID2_HBE
 627 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 628
 629 /* DDR @ 0x00000000 */
 630 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 631 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 632
 633 /* PCI @ 0x80000000 */
 634 #ifdef CONFIG_PCI
 635 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 636 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 637 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 638 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 639 #else
 640 #define CONFIG_SYS_IBAT1L       (0)
 641 #define CONFIG_SYS_IBAT1U       (0)
 642 #define CONFIG_SYS_IBAT2L       (0)
 643 #define CONFIG_SYS_IBAT2U       (0)
 644 #endif
 645
 646 #ifdef CONFIG_MPC83XX_PCI2
 647 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 648 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 649 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 650 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 651 #else
 652 #define CONFIG_SYS_IBAT3L       (0)
 653 #define CONFIG_SYS_IBAT3U       (0)
 654 #define CONFIG_SYS_IBAT4L       (0)
 655 #define CONFIG_SYS_IBAT4U       (0)
 656 #endif
 657
 658 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 659 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 660 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 661
 662 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 663 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
 664                                  BATL_GUARDEDSTORAGE)
 665 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 666
 667 #define CONFIG_SYS_IBAT7L       (0)
 668 #define CONFIG_SYS_IBAT7U       (0)
 669
 670 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 671 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 672 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 673 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 674 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 675 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 676 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 677 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 678 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 679 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 680 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 681 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 682 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 683 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 684 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 685 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 686
 687 #if defined(CONFIG_CMD_KGDB)
 688 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 689 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 690 #endif
 691
 692 /*
 693  * Environment Configuration
 694  */
 695 #define CONFIG_ENV_OVERWRITE
 696
 697 #if defined(CONFIG_TSEC_ENET)
 698 #define CONFIG_HAS_ETH1
 699 #define CONFIG_HAS_ETH0
 700 #endif
 701
 702 #define CONFIG_HOSTNAME         mpc8349emds
 703 #define CONFIG_ROOTPATH         /nfsroot/rootfs
 704 #define CONFIG_BOOTFILE         uImage
 705
 706 #define CONFIG_LOADADDR         800000  /* default location for tftp and bootm */
 707
 708 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 709 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 710
 711 #define CONFIG_BAUDRATE  115200
 712
 713 #define CONFIG_PREBOOT  "echo;" \
 714         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 715         "echo"
 716
 717 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 718         "netdev=eth0\0"                                                 \
 719         "hostname=mpc8349emds\0"                                        \
 720         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 721                 "nfsroot=${serverip}:${rootpath}\0"                     \
 722         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 723         "addip=setenv bootargs ${bootargs} "                            \
 724                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 725                 ":${hostname}:${netdev}:off panic=1\0"                  \
 726         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 727         "flash_nfs=run nfsargs addip addtty;"                           \
 728                 "bootm ${kernel_addr}\0"                                \
 729         "flash_self=run ramargs addip addtty;"                          \
 730                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 731         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 732                 "bootm\0"                                               \
 733         "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"           \
 734         "update=protect off fe000000 fe03ffff; "                        \
 735                 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"     \
 736         "upd=run load update\0"                                         \
 737         "fdtaddr=780000\0"                                              \
 738         "fdtfile=mpc834x_mds.dtb\0"                                     \
 739         ""
 740
 741 #define CONFIG_NFSBOOTCOMMAND                                           \
 742    "setenv bootargs root=/dev/nfs rw "                                  \
 743       "nfsroot=$serverip:$rootpath "                                    \
 744       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 745       "console=$consoledev,$baudrate $othbootargs;"                     \
 746    "tftp $loadaddr $bootfile;"                                          \
 747    "tftp $fdtaddr $fdtfile;"                                            \
 748    "bootm $loadaddr - $fdtaddr"
 749
 750 #define CONFIG_RAMBOOTCOMMAND                                           \
 751    "setenv bootargs root=/dev/ram rw "                                  \
 752       "console=$consoledev,$baudrate $othbootargs;"                     \
 753    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 754    "tftp $loadaddr $bootfile;"                                          \
 755    "tftp $fdtaddr $fdtfile;"                                            \
 756    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 757
 758 #define CONFIG_BOOTCOMMAND      "run flash_self"
 759
 760 #endif  /* __CONFIG_H */