include/configs/MPC8349ITX.h

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
   9
  10  Memory map:
  11
  12  0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
  13  0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
  14  0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
  15  0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
  16  0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
  17  0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
  18  0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
  19  0xF001_0000-0xF001_FFFF Local bus expansion slot
  20  0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
  21  0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
  22  0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
  23
  24  I2C address list:
  25                                                 Align.  Board
  26  Bus    Addr    Part No.        Description     Length  Location
  27  ----------------------------------------------------------------
  28  I2C0   0x50    M24256-BWMN6P   Board EEPROM    2       U64
  29
  30  I2C1   0x20    PCF8574         I2C Expander    0       U8
  31  I2C1   0x21    PCF8574         I2C Expander    0       U10
  32  I2C1   0x38    PCF8574A        I2C Expander    0       U8
  33  I2C1   0x39    PCF8574A        I2C Expander    0       U10
  34  I2C1   0x51    (DDR)           DDR EEPROM      1       U1
  35  I2C1   0x68    DS1339          RTC             1       U68
  36
  37  Note that a given board has *either* a pair of 8574s or a pair of 8574As.
  38 */
  39
  40 #ifndef __CONFIG_H
  41 #define __CONFIG_H
  42
  43 #define CONFIG_DISPLAY_BOARDINFO
  44
  45 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
  46 #define CONFIG_SYS_LOWBOOT
  47 #endif
  48
  49 /*
  50  * High Level Configuration Options
  51  */
  52 #define CONFIG_MPC834x          /* MPC834x family (8343, 8347, 8349) */
  53 #define CONFIG_MPC8349          /* MPC8349 specific */
  54
  55 #ifndef CONFIG_SYS_TEXT_BASE
  56 #define CONFIG_SYS_TEXT_BASE    0xFEF00000
  57 #endif
  58
  59 #define CONFIG_SYS_IMMR 0xE0000000      /* The IMMR is relocated to here */
  60
  61 #define CONFIG_MISC_INIT_F
  62 #define CONFIG_MISC_INIT_R
  63
  64 /*
  65  * On-board devices
  66  */
  67
  68 #ifdef CONFIG_MPC8349ITX
  69 /* The CF card interface on the back of the board */
  70 #define CONFIG_COMPACT_FLASH
  71 #define CONFIG_VSC7385_ENET     /* VSC7385 ethernet support */
  72 #define CONFIG_SATA_SIL3114     /* SIL3114 SATA controller */
  73 #define CONFIG_SYS_USB_HOST     /* use the EHCI USB controller */
  74 #endif
  75
  76 #define CONFIG_PCI
  77 #define CONFIG_RTC_DS1337
  78 #define CONFIG_SYS_I2C
  79 #define CONFIG_TSEC_ENET                /* TSEC Ethernet support */
  80
  81 /*
  82  * Device configurations
  83  */
  84
  85 /* I2C */
  86 #ifdef CONFIG_SYS_I2C
  87 #define CONFIG_SYS_I2C_FSL
  88 #define CONFIG_SYS_FSL_I2C_SPEED        400000
  89 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  90 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
  91 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
  92 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
  93 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
  94
  95 #define CONFIG_SYS_SPD_BUS_NUM          1       /* The I2C bus for SPD */
  96 #define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC */
  97
  98 #define CONFIG_SYS_I2C_8574_ADDR1       0x20    /* I2C1, PCF8574 */
  99 #define CONFIG_SYS_I2C_8574_ADDR2       0x21    /* I2C1, PCF8574 */
 100 #define CONFIG_SYS_I2C_8574A_ADDR1      0x38    /* I2C1, PCF8574A */
 101 #define CONFIG_SYS_I2C_8574A_ADDR2      0x39    /* I2C1, PCF8574A */
 102 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* I2C0, Board EEPROM */
 103 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* I2C1, DS1339 RTC*/
 104 #define SPD_EEPROM_ADDRESS              0x51    /* I2C1, DDR */
 105
 106 /* Don't probe these addresses: */
 107 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
 108                                  {1, CONFIG_SYS_I2C_8574_ADDR2}, \
 109                                  {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
 110                                  {1, CONFIG_SYS_I2C_8574A_ADDR2} }
 111 /* Bit definitions for the 8574[A] I2C expander */
 112                                 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
 113 #define I2C_8574_REVISION       0x03
 114 #define I2C_8574_CF             0x08    /* 1=Compact flash absent, 0=present */
 115 #define I2C_8574_MPCICLKRN      0x10    /* MiniPCI Clk Run */
 116 #define I2C_8574_PCI66          0x20    /* 0=33MHz PCI, 1=66MHz PCI */
 117 #define I2C_8574_FLASHSIDE      0x40    /* 0=Reset vector from U4, 1=from U7*/
 118
 119 #endif
 120
 121 /* Compact Flash */
 122 #ifdef CONFIG_COMPACT_FLASH
 123
 124 #define CONFIG_SYS_IDE_MAXBUS           1
 125 #define CONFIG_SYS_IDE_MAXDEVICE        1
 126
 127 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 128 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_CF_BASE
 129 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000
 130 #define CONFIG_SYS_ATA_REG_OFFSET       0
 131 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0200
 132 #define CONFIG_SYS_ATA_STRIDE           2
 133
 134 /* If a CF card is not inserted, time out quickly */
 135 #define ATA_RESET_TIME  1
 136
 137 #endif
 138
 139 /*
 140  * SATA
 141  */
 142 #ifdef CONFIG_SATA_SIL3114
 143
 144 #define CONFIG_SYS_SATA_MAX_DEVICE      4
 145 #define CONFIG_LIBATA
 146 #define CONFIG_LBA48
 147
 148 #endif
 149
 150 #ifdef CONFIG_SYS_USB_HOST
 151 /*
 152  * Support USB
 153  */
 154 #define CONFIG_USB_EHCI
 155 #define CONFIG_USB_EHCI_FSL
 156
 157 /* Current USB implementation supports the only USB controller,
 158  * so we have to choose between the MPH or the DR ones */
 159 #if 1
 160 #define CONFIG_HAS_FSL_MPH_USB
 161 #else
 162 #define CONFIG_HAS_FSL_DR_USB
 163 #endif
 164
 165 #endif
 166
 167 /*
 168  * DDR Setup
 169  */
 170 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
 171 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 172 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 173 #define CONFIG_SYS_83XX_DDR_USES_CS0
 174 #define CONFIG_SYS_MEMTEST_START        0x1000  /* memtest region */
 175 #define CONFIG_SYS_MEMTEST_END          0x2000
 176
 177 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
 178                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 179
 180 #define CONFIG_VERY_BIG_RAM
 181 #define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)
 182
 183 #ifdef CONFIG_SYS_I2C
 184 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
 185 #endif
 186
 187 /* No SPD? Then manually set up DDR parameters */
 188 #ifndef CONFIG_SPD_EEPROM
 189     #define CONFIG_SYS_DDR_SIZE         256     /* Mb */
 190     #define CONFIG_SYS_DDR_CS0_CONFIG   (CSCONFIG_EN \
 191                                         | CSCONFIG_ROW_BIT_13 \
 192                                         | CSCONFIG_COL_BIT_10)
 193
 194     #define CONFIG_SYS_DDR_TIMING_1     0x26242321
 195     #define CONFIG_SYS_DDR_TIMING_2     0x00000800  /* P9-45, may need tuning */
 196 #endif
 197
 198 /*
 199  *Flash on the Local Bus
 200  */
 201
 202 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 203 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 204 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 205 #define CONFIG_SYS_FLASH_EMPTY_INFO
 206 /* 127 64KB sectors + 8 8KB sectors per device */
 207 #define CONFIG_SYS_MAX_FLASH_SECT       135
 208 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 209 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 210 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 211
 212 /* The ITX has two flash chips, but the ITX-GP has only one.  To support both
 213 boards, we say we have two, but don't display a message if we find only one. */
 214 #define CONFIG_SYS_FLASH_QUIET_TEST
 215 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 216 #define CONFIG_SYS_FLASH_BANKS_LIST     \
 217                 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
 218 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size in MB */
 219 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 220
 221 /* Vitesse 7385 */
 222
 223 #ifdef CONFIG_VSC7385_ENET
 224
 225 #define CONFIG_TSEC2
 226
 227 /* The flash address and size of the VSC7385 firmware image */
 228 #define CONFIG_VSC7385_IMAGE            0xFEFFE000
 229 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 230
 231 #endif
 232
 233 /*
 234  * BRx, ORx, LBLAWBARx, and LBLAWARx
 235  */
 236
 237 /* Flash */
 238
 239 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 240                                 | BR_PS_16 \
 241                                 | BR_MS_GPCM \
 242                                 | BR_V)
 243 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 244                                 | OR_UPM_XAM \
 245                                 | OR_GPCM_CSNT \
 246                                 | OR_GPCM_ACS_DIV2 \
 247                                 | OR_GPCM_XACS \
 248                                 | OR_GPCM_SCY_15 \
 249                                 | OR_GPCM_TRLX_SET \
 250                                 | OR_GPCM_EHTR_SET \
 251                                 | OR_GPCM_EAD)
 252 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 253 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
 254
 255 /* Vitesse 7385 */
 256
 257 #define CONFIG_SYS_VSC7385_BASE 0xF8000000
 258
 259 #ifdef CONFIG_VSC7385_ENET
 260
 261 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_VSC7385_BASE \
 262                                 | BR_PS_8 \
 263                                 | BR_MS_GPCM \
 264                                 | BR_V)
 265 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_128KB \
 266                                 | OR_GPCM_CSNT \
 267                                 | OR_GPCM_XACS \
 268                                 | OR_GPCM_SCY_15 \
 269                                 | OR_GPCM_SETA \
 270                                 | OR_GPCM_TRLX_SET \
 271                                 | OR_GPCM_EHTR_SET \
 272                                 | OR_GPCM_EAD)
 273
 274 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_VSC7385_BASE
 275 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 276
 277 #endif
 278
 279 /* LED */
 280
 281 #define CONFIG_SYS_LED_BASE     0xF9000000
 282 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_LED_BASE \
 283                                 | BR_PS_8 \
 284                                 | BR_MS_GPCM \
 285                                 | BR_V)
 286 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_2MB \
 287                                 | OR_GPCM_CSNT \
 288                                 | OR_GPCM_ACS_DIV2 \
 289                                 | OR_GPCM_XACS \
 290                                 | OR_GPCM_SCY_9 \
 291                                 | OR_GPCM_TRLX_SET \
 292                                 | OR_GPCM_EHTR_SET \
 293                                 | OR_GPCM_EAD)
 294
 295 /* Compact Flash */
 296
 297 #ifdef CONFIG_COMPACT_FLASH
 298
 299 #define CONFIG_SYS_CF_BASE      0xF0000000
 300
 301 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_CF_BASE \
 302                                 | BR_PS_16 \
 303                                 | BR_MS_UPMA \
 304                                 | BR_V)
 305 #define CONFIG_SYS_OR3_PRELIM   (OR_UPM_AM | OR_UPM_BI)
 306
 307 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_CF_BASE
 308 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
 309
 310 #endif
 311
 312 /*
 313  * U-Boot memory configuration
 314  */
 315 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 316
 317 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 318 #define CONFIG_SYS_RAMBOOT
 319 #else
 320 #undef  CONFIG_SYS_RAMBOOT
 321 #endif
 322
 323 #define CONFIG_SYS_INIT_RAM_LOCK
 324 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 325 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 326
 327 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 328                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 329 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 330
 331 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 332 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 333 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024) /* Reserved for malloc */
 334
 335 /*
 336  * Local Bus LCRR and LBCR regs
 337  *    LCRR:  DLL bypass, Clock divider is 4
 338  * External Local Bus rate is
 339  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 340  */
 341 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 342 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 343 #define CONFIG_SYS_LBC_LBCR     0x00000000
 344
 345                                 /* LB sdram refresh timer, about 6us */
 346 #define CONFIG_SYS_LBC_LSRT     0x32000000
 347                                 /* LB refresh timer prescal, 266MHz/32*/
 348 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 349
 350 /*
 351  * Serial Port
 352  */
 353 #define CONFIG_CONS_INDEX       1
 354 #define CONFIG_SYS_NS16550_SERIAL
 355 #define CONFIG_SYS_NS16550_REG_SIZE     1
 356 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 357
 358 #define CONFIG_SYS_BAUDRATE_TABLE  \
 359                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 360
 361 #define CONFIG_CONSOLE          ttyS0
 362 #define CONFIG_BAUDRATE         115200
 363
 364 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 365 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 366
 367 /*
 368  * PCI
 369  */
 370 #ifdef CONFIG_PCI
 371 #define CONFIG_PCI_INDIRECT_BRIDGE
 372
 373 #define CONFIG_MPC83XX_PCI2
 374
 375 /*
 376  * General PCI
 377  * Addresses are mapped 1-1.
 378  */
 379 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 380 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 381 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 382 #define CONFIG_SYS_PCI1_MMIO_BASE       \
 383                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
 384 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 385 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 386 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 387 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 388 #define CONFIG_SYS_PCI1_IO_SIZE         0x01000000      /* 16M */
 389
 390 #ifdef CONFIG_MPC83XX_PCI2
 391 #define CONFIG_SYS_PCI2_MEM_BASE        \
 392                         (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
 393 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 394 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 395 #define CONFIG_SYS_PCI2_MMIO_BASE       \
 396                         (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
 397 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 398 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 399 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 400 #define CONFIG_SYS_PCI2_IO_PHYS         \
 401                         (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
 402 #define CONFIG_SYS_PCI2_IO_SIZE         0x01000000      /* 16M */
 403 #endif
 404
 405 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 406
 407 #ifndef CONFIG_PCI_PNP
 408     #define PCI_ENET0_IOADDR    0x00000000
 409     #define PCI_ENET0_MEMADDR   CONFIG_SYS_PCI2_MEM_BASE
 410     #define PCI_IDSEL_NUMBER    0x0f    /* IDSEL = AD15 */
 411 #endif
 412
 413 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 414
 415 #endif
 416
 417 #define CONFIG_PCI_66M
 418 #ifdef CONFIG_PCI_66M
 419 #define CONFIG_83XX_CLKIN       66666666        /* in Hz */
 420 #else
 421 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
 422 #endif
 423
 424 /* TSEC */
 425
 426 #ifdef CONFIG_TSEC_ENET
 427
 428 #define CONFIG_MII
 429 #define CONFIG_PHY_GIGE         /* In case CONFIG_CMD_MII is specified */
 430
 431 #define CONFIG_TSEC1
 432
 433 #ifdef CONFIG_TSEC1
 434 #define CONFIG_HAS_ETH0
 435 #define CONFIG_TSEC1_NAME  "TSEC0"
 436 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 437 #define TSEC1_PHY_ADDR          0x1c    /* VSC8201 uses address 0x1c */
 438 #define TSEC1_PHYIDX            0
 439 #define TSEC1_FLAGS             TSEC_GIGABIT
 440 #endif
 441
 442 #ifdef CONFIG_TSEC2
 443 #define CONFIG_HAS_ETH1
 444 #define CONFIG_TSEC2_NAME  "TSEC1"
 445 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 446
 447 #define TSEC2_PHY_ADDR          4
 448 #define TSEC2_PHYIDX            0
 449 #define TSEC2_FLAGS             TSEC_GIGABIT
 450 #endif
 451
 452 #define CONFIG_ETHPRIME         "Freescale TSEC"
 453
 454 #endif
 455
 456 /*
 457  * Environment
 458  */
 459 #define CONFIG_ENV_OVERWRITE
 460
 461 #ifndef CONFIG_SYS_RAMBOOT
 462   #define CONFIG_ENV_IS_IN_FLASH
 463   #define CONFIG_ENV_ADDR       \
 464                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 465   #define CONFIG_ENV_SECT_SIZE  0x10000 /* 64K (one sector) for environment */
 466   #define CONFIG_ENV_SIZE       0x2000
 467 #else
 468   #define CONFIG_SYS_NO_FLASH   /* Flash is not usable now */
 469   #undef  CONFIG_FLASH_CFI_DRIVER
 470   #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
 471   #define CONFIG_ENV_ADDR       (CONFIG_SYS_MONITOR_BASE - 0x1000)
 472   #define CONFIG_ENV_SIZE       0x2000
 473 #endif
 474
 475 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 476 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 477
 478 /*
 479  * BOOTP options
 480  */
 481 #define CONFIG_BOOTP_BOOTFILESIZE
 482 #define CONFIG_BOOTP_BOOTPATH
 483 #define CONFIG_BOOTP_GATEWAY
 484 #define CONFIG_BOOTP_HOSTNAME
 485
 486 /*
 487  * Command line configuration.
 488  */
 489 #define CONFIG_CMD_DATE
 490 #define CONFIG_CMD_IRQ
 491 #define CONFIG_CMD_SDRAM
 492
 493 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
 494                                 || defined(CONFIG_USB_STORAGE)
 495         #define CONFIG_DOS_PARTITION
 496         #define CONFIG_SUPPORT_VFAT
 497 #endif
 498
 499 #ifdef CONFIG_COMPACT_FLASH
 500         #define CONFIG_CMD_IDE
 501 #endif
 502
 503 #ifdef CONFIG_SATA_SIL3114
 504         #define CONFIG_CMD_SATA
 505 #endif
 506
 507 #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
 508 #endif
 509
 510 #ifdef CONFIG_PCI
 511         #define CONFIG_CMD_PCI
 512 #endif
 513
 514 /* Watchdog */
 515 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 516
 517 /*
 518  * Miscellaneous configurable options
 519  */
 520 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 521 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 522 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 523
 524 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 525 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 526
 527 #if defined(CONFIG_CMD_KGDB)
 528         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 529 #else
 530         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 531 #endif
 532
 533                                 /* Print Buffer Size */
 534 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 535 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 536                                 /* Boot Argument Buffer Size */
 537 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 538
 539 /*
 540  * For booting Linux, the board info and command line data
 541  * have to be in the first 256 MB of memory, since this is
 542  * the maximum mapped by the Linux kernel during initialization.
 543  */
 544                                 /* Initial Memory map for Linux*/
 545 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 546 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 547
 548 #define CONFIG_SYS_HRCW_LOW (\
 549         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 550         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 551         HRCWL_CSB_TO_CLKIN_4X1 |\
 552         HRCWL_VCO_1X2 |\
 553         HRCWL_CORE_TO_CSB_2X1)
 554
 555 #ifdef CONFIG_SYS_LOWBOOT
 556 #define CONFIG_SYS_HRCW_HIGH (\
 557         HRCWH_PCI_HOST |\
 558         HRCWH_32_BIT_PCI |\
 559         HRCWH_PCI1_ARBITER_ENABLE |\
 560         HRCWH_PCI2_ARBITER_ENABLE |\
 561         HRCWH_CORE_ENABLE |\
 562         HRCWH_FROM_0X00000100 |\
 563         HRCWH_BOOTSEQ_DISABLE |\
 564         HRCWH_SW_WATCHDOG_DISABLE |\
 565         HRCWH_ROM_LOC_LOCAL_16BIT |\
 566         HRCWH_TSEC1M_IN_GMII |\
 567         HRCWH_TSEC2M_IN_GMII)
 568 #else
 569 #define CONFIG_SYS_HRCW_HIGH (\
 570         HRCWH_PCI_HOST |\
 571         HRCWH_32_BIT_PCI |\
 572         HRCWH_PCI1_ARBITER_ENABLE |\
 573         HRCWH_PCI2_ARBITER_ENABLE |\
 574         HRCWH_CORE_ENABLE |\
 575         HRCWH_FROM_0XFFF00100 |\
 576         HRCWH_BOOTSEQ_DISABLE |\
 577         HRCWH_SW_WATCHDOG_DISABLE |\
 578         HRCWH_ROM_LOC_LOCAL_16BIT |\
 579         HRCWH_TSEC1M_IN_GMII |\
 580         HRCWH_TSEC2M_IN_GMII)
 581 #endif
 582
 583 /*
 584  * System performance
 585  */
 586 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 587 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
 588 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 589 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 590 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 591 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 592 #define CONFIG_SYS_SCCR_USBMPHCM 3      /* USB MPH controller's clock */
 593 #define CONFIG_SYS_SCCR_USBDRCM 0       /* USB DR controller's clock */
 594
 595 /*
 596  * System IO Config
 597  */
 598 /* Needed for gigabit to work on TSEC 1 */
 599 #define CONFIG_SYS_SICRH SICRH_TSOBI1
 600                                 /* USB DR as device + USB MPH as host */
 601 #define CONFIG_SYS_SICRL        (SICRL_LDP_A | SICRL_USB1)
 602
 603 #define CONFIG_SYS_HID0_INIT    0x00000000
 604 #define CONFIG_SYS_HID0_FINAL   HID0_ENABLE_INSTRUCTION_CACHE
 605
 606 #define CONFIG_SYS_HID2 HID2_HBE
 607 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 608
 609 /* DDR  */
 610 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 611                                 | BATL_PP_RW \
 612                                 | BATL_MEMCOHERENCE)
 613 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 614                                 | BATU_BL_256M \
 615                                 | BATU_VS \
 616                                 | BATU_VP)
 617
 618 /* PCI  */
 619 #ifdef CONFIG_PCI
 620 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 621                                 | BATL_PP_RW \
 622                                 | BATL_MEMCOHERENCE)
 623 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 624                                 | BATU_BL_256M \
 625                                 | BATU_VS \
 626                                 | BATU_VP)
 627 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 628                                 | BATL_PP_RW \
 629                                 | BATL_CACHEINHIBIT \
 630                                 | BATL_GUARDEDSTORAGE)
 631 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 632                                 | BATU_BL_256M \
 633                                 | BATU_VS \
 634                                 | BATU_VP)
 635 #else
 636 #define CONFIG_SYS_IBAT1L       0
 637 #define CONFIG_SYS_IBAT1U       0
 638 #define CONFIG_SYS_IBAT2L       0
 639 #define CONFIG_SYS_IBAT2U       0
 640 #endif
 641
 642 #ifdef CONFIG_MPC83XX_PCI2
 643 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 644                                 | BATL_PP_RW \
 645                                 | BATL_MEMCOHERENCE)
 646 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 647                                 | BATU_BL_256M \
 648                                 | BATU_VS \
 649                                 | BATU_VP)
 650 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 651                                 | BATL_PP_RW \
 652                                 | BATL_CACHEINHIBIT \
 653                                 | BATL_GUARDEDSTORAGE)
 654 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 655                                 | BATU_BL_256M \
 656                                 | BATU_VS \
 657                                 | BATU_VP)
 658 #else
 659 #define CONFIG_SYS_IBAT3L       0
 660 #define CONFIG_SYS_IBAT3U       0
 661 #define CONFIG_SYS_IBAT4L       0
 662 #define CONFIG_SYS_IBAT4U       0
 663 #endif
 664
 665 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 666 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 667                                 | BATL_PP_RW \
 668                                 | BATL_CACHEINHIBIT \
 669                                 | BATL_GUARDEDSTORAGE)
 670 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 671                                 | BATU_BL_256M \
 672                                 | BATU_VS \
 673                                 | BATU_VP)
 674
 675 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 676 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
 677                                 | BATL_PP_RW \
 678                                 | BATL_MEMCOHERENCE \
 679                                 | BATL_GUARDEDSTORAGE)
 680 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
 681                                 | BATU_BL_256M \
 682                                 | BATU_VS \
 683                                 | BATU_VP)
 684
 685 #define CONFIG_SYS_IBAT7L       0
 686 #define CONFIG_SYS_IBAT7U       0
 687
 688 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 689 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 690 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 691 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 692 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 693 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 694 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 695 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 696 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 697 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 698 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 699 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 700 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 701 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 702 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 703 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 704
 705 #if defined(CONFIG_CMD_KGDB)
 706 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 707 #endif
 708
 709 /*
 710  * Environment Configuration
 711  */
 712 #define CONFIG_ENV_OVERWRITE
 713
 714 #define CONFIG_NETDEV           "eth0"
 715
 716 #ifdef CONFIG_MPC8349ITX
 717 #define CONFIG_HOSTNAME         "mpc8349emitx"
 718 #else
 719 #define CONFIG_HOSTNAME         "mpc8349emitxgp"
 720 #endif
 721
 722 /* Default path and filenames */
 723 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 724 #define CONFIG_BOOTFILE         "uImage"
 725                                 /* U-Boot image on TFTP server */
 726 #define CONFIG_UBOOTPATH        "u-boot.bin"
 727
 728 #ifdef CONFIG_MPC8349ITX
 729 #define CONFIG_FDTFILE          "mpc8349emitx.dtb"
 730 #else
 731 #define CONFIG_FDTFILE          "mpc8349emitxgp.dtb"
 732 #endif
 733
 734
 735 #define CONFIG_BOOTARGS \
 736         "root=/dev/nfs rw" \
 737         " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH    \
 738         " ip=" __stringify(CONFIG_IPADDR) ":"           \
 739                 __stringify(CONFIG_SERVERIP) ":"        \
 740                 __stringify(CONFIG_GATEWAYIP) ":"       \
 741                 __stringify(CONFIG_NETMASK) ":"         \
 742                 CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off"                \
 743         " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE)
 744
 745 #define CONFIG_EXTRA_ENV_SETTINGS \
 746         "console=" __stringify(CONFIG_CONSOLE) "\0"                     \
 747         "netdev=" CONFIG_NETDEV "\0"                                    \
 748         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 749         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 750                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 751                         " +$filesize; " \
 752                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 753                         " +$filesize; " \
 754                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 755                         " $filesize; "  \
 756                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 757                         " +$filesize; " \
 758                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 759                         " $filesize\0"  \
 760         "fdtaddr=780000\0"                                              \
 761         "fdtfile=" CONFIG_FDTFILE "\0"
 762
 763 #define CONFIG_NFSBOOTCOMMAND                                           \
 764         "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"  \
 765         " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
 766         " console=$console,$baudrate $othbootargs; "                    \
 767         "tftp $loadaddr $bootfile;"                                     \
 768         "tftp $fdtaddr $fdtfile;"                                       \
 769         "bootm $loadaddr - $fdtaddr"
 770
 771 #define CONFIG_RAMBOOTCOMMAND                                           \
 772         "setenv bootargs root=/dev/ram rw"                              \
 773         " console=$console,$baudrate $othbootargs; "                    \
 774         "tftp $ramdiskaddr $ramdiskfile;"                               \
 775         "tftp $loadaddr $bootfile;"                                     \
 776         "tftp $fdtaddr $fdtfile;"                                       \
 777         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 778
 779 #endif