include/configs/MPC8360EMDS.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #ifndef __CONFIG_H
  23 #define __CONFIG_H
  24
  25 #undef DEBUG
  26
  27 /*
  28  * High Level Configuration Options
  29  */
  30 #define CONFIG_E300             1 /* E300 family */
  31 #define CONFIG_QE               1 /* Has QE */
  32 #define CONFIG_MPC83XX          1 /* MPC83XX family */
  33 #define CONFIG_MPC8360          1 /* MPC8360 CPU specific */
  34 #define CONFIG_MPC8360EMDS      1 /* MPC8360EMDS board specific */
  35
  36 /*
  37  * System Clock Setup
  38  */
  39 #ifdef CONFIG_PCISLAVE
  40 #define CONFIG_83XX_PCICLK      66000000 /* in HZ */
  41 #else
  42 #define CONFIG_83XX_CLKIN       66000000 /* in Hz */
  43 #endif
  44
  45 #ifndef CONFIG_SYS_CLK_FREQ
  46 #define CONFIG_SYS_CLK_FREQ     66000000
  47 #endif
  48
  49 /*
  50  * Hardware Reset Configuration Word
  51  */
  52 #define CFG_HRCW_LOW (\
  53         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  54         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  55         HRCWL_CSB_TO_CLKIN_4X1 |\
  56         HRCWL_VCO_1X2 |\
  57         HRCWL_CE_PLL_VCO_DIV_4 |\
  58         HRCWL_CE_PLL_DIV_1X1 |\
  59         HRCWL_CE_TO_PLL_1X6 |\
  60         HRCWL_CORE_TO_CSB_2X1)
  61
  62 #ifdef CONFIG_PCISLAVE
  63 #define CFG_HRCW_HIGH (\
  64         HRCWH_PCI_AGENT |\
  65         HRCWH_PCI1_ARBITER_DISABLE |\
  66         HRCWH_PCICKDRV_DISABLE |\
  67         HRCWH_CORE_ENABLE |\
  68         HRCWH_FROM_0XFFF00100 |\
  69         HRCWH_BOOTSEQ_DISABLE |\
  70         HRCWH_SW_WATCHDOG_DISABLE |\
  71         HRCWH_ROM_LOC_LOCAL_16BIT)
  72 #else
  73 #define CFG_HRCW_HIGH (\
  74         HRCWH_PCI_HOST |\
  75         HRCWH_PCI1_ARBITER_ENABLE |\
  76         HRCWH_PCICKDRV_ENABLE |\
  77         HRCWH_CORE_ENABLE |\
  78         HRCWH_FROM_0X00000100 |\
  79         HRCWH_BOOTSEQ_DISABLE |\
  80         HRCWH_SW_WATCHDOG_DISABLE |\
  81         HRCWH_ROM_LOC_LOCAL_16BIT)
  82 #endif
  83
  84 /*
  85  * System IO Config
  86  */
  87 #define CFG_SICRH               0x00000000
  88 #define CFG_SICRL               0x40000000
  89
  90 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
  91
  92 /*
  93  * IMMR new address
  94  */
  95 #define CFG_IMMR                0xE0000000
  96
  97 /*
  98  * DDR Setup
  99  */
 100 #define CFG_DDR_BASE            0x00000000 /* DDR is system memory */
 101 #define CFG_SDRAM_BASE          CFG_DDR_BASE
 102 #define CFG_DDR_SDRAM_BASE      CFG_DDR_BASE
 103 #define CFG_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
 104                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 105
 106 #define CFG_83XX_DDR_USES_CS0
 107
 108 #define CONFIG_DDR_ECC          /* support DDR ECC function */
 109 #define CONFIG_DDR_ECC_CMD      /* Use DDR ECC user commands */
 110
 111 /*
 112  * DDRCDR - DDR Control Driver Register
 113  */
 114 #define CFG_DDRCDR_VALUE        0x80080001
 115
 116 #define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
 117 #if defined(CONFIG_SPD_EEPROM)
 118 /*
 119  * Determine DDR configuration from I2C interface.
 120  */
 121 #define SPD_EEPROM_ADDRESS      0x52 /* DDR SODIMM */
 122 #else
 123 /*
 124  * Manually set up DDR parameters
 125  */
 126 #define CFG_DDR_SIZE            256 /* MB */
 127 #if defined(CONFIG_DDR_II)
 128 #define CFG_DDRCDR              0x80080001
 129 #define CFG_DDR_CS0_BNDS        0x0000000f
 130 #define CFG_DDR_CS0_CONFIG      0x80330102
 131 #define CFG_DDR_TIMING_0        0x00220802
 132 #define CFG_DDR_TIMING_1        0x38357322
 133 #define CFG_DDR_TIMING_2        0x2f9048c8
 134 #define CFG_DDR_TIMING_3        0x00000000
 135 #define CFG_DDR_CLK_CNTL        0x02000000
 136 #define CFG_DDR_MODE            0x47d00432
 137 #define CFG_DDR_MODE2           0x8000c000
 138 #define CFG_DDR_INTERVAL        0x03cf0080
 139 #define CFG_DDR_SDRAM_CFG       0x43000000
 140 #define CFG_DDR_SDRAM_CFG2      0x00401000
 141 #else
 142 #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
 143 #define CFG_DDR_TIMING_1        0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
 144 #define CFG_DDR_TIMING_2        0x00000800 /* may need tuning */
 145 #define CFG_DDR_CONTROL         0x42008000 /* Self refresh,2T timing */
 146 #define CFG_DDR_MODE            0x20000162 /* DLL,normal,seq,4/2.5 */
 147 #define CFG_DDR_INTERVAL        0x045b0100 /* page mode */
 148 #endif
 149 #endif
 150
 151 /*
 152  * Memory test
 153  */
 154 #undef CFG_DRAM_TEST            /* memory test, takes time */
 155 #define CFG_MEMTEST_START       0x00000000 /* memtest region */
 156 #define CFG_MEMTEST_END         0x00100000
 157
 158 /*
 159  * The reserved memory
 160  */
 161
 162 #define CFG_MONITOR_BASE        TEXT_BASE /* start of monitor */
 163
 164 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 165 #define CFG_RAMBOOT
 166 #else
 167 #undef  CFG_RAMBOOT
 168 #endif
 169
 170 #define CFG_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
 171 #define CFG_MALLOC_LEN          (128 * 1024) /* Reserved for malloc */
 172
 173 /*
 174  * Initial RAM Base Address Setup
 175  */
 176 #define CFG_INIT_RAM_LOCK       1
 177 #define CFG_INIT_RAM_ADDR       0xE6000000 /* Initial RAM address */
 178 #define CFG_INIT_RAM_END        0x1000 /* End of used area in RAM */
 179 #define CFG_GBL_DATA_SIZE       0x100 /* num bytes initial data */
 180 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 181
 182 /*
 183  * Local Bus Configuration & Clock Setup
 184  */
 185 #define CFG_LCRR                (LCRR_DBYP | LCRR_CLKDIV_4)
 186 #define CFG_LBC_LBCR            0x00000000
 187
 188 /*
 189  * FLASH on the Local Bus
 190  */
 191 #define CFG_FLASH_CFI           /* use the Common Flash Interface */
 192 #define CFG_FLASH_CFI_DRIVER    /* use the CFI driver */
 193 #define CFG_FLASH_BASE          0xFE000000 /* FLASH base address */
 194 #define CFG_FLASH_SIZE          32 /* max FLASH size is 32M */
 195
 196 #define CFG_LBLAWBAR0_PRELIM    CFG_FLASH_BASE /* Window base at flash base */
 197 #define CFG_LBLAWAR0_PRELIM     0x80000018 /* 32MB window size */
 198
 199 #define CFG_BR0_PRELIM  (CFG_FLASH_BASE | /* Flash Base address */ \
 200                         (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 201                         BR_V)   /* valid */
 202 #define CFG_OR0_PRELIM          ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 203                                 OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 204                                 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 205
 206 #define CFG_MAX_FLASH_BANKS     1 /* number of banks */
 207 #define CFG_MAX_FLASH_SECT      256 /* max sectors per device */
 208
 209 #undef  CFG_FLASH_CHECKSUM
 210
 211 /*
 212  * BCSR on the Local Bus
 213  */
 214 #define CFG_BCSR                0xF8000000
 215 #define CFG_LBLAWBAR1_PRELIM    CFG_BCSR /* Access window base at BCSR base */
 216 #define CFG_LBLAWAR1_PRELIM     0x8000000F /* Access window size 64K */
 217
 218 #define CFG_BR1_PRELIM          (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
 219 #define CFG_OR1_PRELIM          0xFFFFE9f7 /* length 32K */
 220
 221 /*
 222  * SDRAM on the Local Bus
 223  */
 224 #define CFG_LBC_SDRAM_BASE      0xF0000000      /* SDRAM base address */
 225 #define CFG_LBC_SDRAM_SIZE      64              /* LBC SDRAM is 64MB */
 226
 227 #define CFG_LB_SDRAM            /* if board has SRDAM on local bus */
 228
 229 #ifdef CFG_LB_SDRAM
 230 #define CFG_LBLAWBAR2_PRELIM    CFG_LBC_SDRAM_BASE
 231 #define CFG_LBLAWAR2_PRELIM     0x80000019 /* 64MB */
 232
 233 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
 234 /*
 235  * Base Register 2 and Option Register 2 configure SDRAM.
 236  * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
 237  *
 238  * For BR2, need:
 239  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 240  *    port size = 32-bits = BR2[19:20] = 11
 241  *    no parity checking = BR2[21:22] = 00
 242  *    SDRAM for MSEL = BR2[24:26] = 011
 243  *    Valid = BR[31] = 1
 244  *
 245  * 0    4    8    12   16   20   24   28
 246  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 247  *
 248  * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
 249  * the top 17 bits of BR2.
 250  */
 251
 252 #define CFG_BR2_PRELIM  0xf0001861 /*Port size=32bit, MSEL=SDRAM */
 253
 254 /*
 255  * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
 256  *
 257  * For OR2, need:
 258  *    64MB mask for AM, OR2[0:7] = 1111 1100
 259  *                 XAM, OR2[17:18] = 11
 260  *    9 columns OR2[19-21] = 010
 261  *    13 rows   OR2[23-25] = 100
 262  *    EAD set for extra time OR[31] = 1
 263  *
 264  * 0    4    8    12   16   20   24   28
 265  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 266  */
 267
 268 #define CFG_OR2_PRELIM  0xfc006901
 269
 270 #define CFG_LBC_LSRT    0x32000000 /* LB sdram refresh timer, about 6us */
 271 #define CFG_LBC_MRTPR   0x20000000 /* LB refresh timer prescal, 266MHz/32 */
 272
 273 /*
 274  * LSDMR masks
 275  */
 276 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
 277 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
 278 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
 279 #define CFG_LBC_LSDMR_OP_MRW    (3 << (31 - 4))
 280 #define CFG_LBC_LSDMR_OP_PRECH  (4 << (31 - 4))
 281 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
 282 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
 283 #define CFG_LBC_LSDMR_OP_RWINV  (7 << (31 - 4))
 284
 285 #define CFG_LBC_LSDMR_COMMON    0x0063b723
 286
 287 /*
 288  * SDRAM Controller configuration sequence.
 289  */
 290 #define CFG_LBC_LSDMR_1         ( CFG_LBC_LSDMR_COMMON \
 291                                 | CFG_LBC_LSDMR_OP_PCHALL)
 292 #define CFG_LBC_LSDMR_2         ( CFG_LBC_LSDMR_COMMON \
 293                                 | CFG_LBC_LSDMR_OP_ARFRSH)
 294 #define CFG_LBC_LSDMR_3         ( CFG_LBC_LSDMR_COMMON \
 295                                 | CFG_LBC_LSDMR_OP_ARFRSH)
 296 #define CFG_LBC_LSDMR_4         ( CFG_LBC_LSDMR_COMMON \
 297                                 | CFG_LBC_LSDMR_OP_MRW)
 298 #define CFG_LBC_LSDMR_5         ( CFG_LBC_LSDMR_COMMON \
 299                                 | CFG_LBC_LSDMR_OP_NORMAL)
 300
 301 #endif
 302
 303 /*
 304  * Windows to access PIB via local bus
 305  */
 306 #define CFG_LBLAWBAR3_PRELIM    0xf8010000 /* windows base 0xf8010000 */
 307 #define CFG_LBLAWAR3_PRELIM     0x8000000e /* windows size 32KB */
 308
 309 /*
 310  * CS4 on Local Bus, to PIB
 311  */
 312 #define CFG_BR4_PRELIM  0xf8008801 /* CS4 base address at 0xf8008000 */
 313 #define CFG_OR4_PRELIM  0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
 314
 315 /*
 316  * CS5 on Local Bus, to PIB
 317  */
 318 #define CFG_BR5_PRELIM  0xf8010801 /* CS5 base address at 0xf8010000 */
 319 #define CFG_OR5_PRELIM  0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
 320
 321 /*
 322  * Serial Port
 323  */
 324 #define CONFIG_CONS_INDEX       1
 325 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 326 #define CFG_NS16550
 327 #define CFG_NS16550_SERIAL
 328 #define CFG_NS16550_REG_SIZE    1
 329 #define CFG_NS16550_CLK         get_bus_freq(0)
 330
 331 #define CFG_BAUDRATE_TABLE  \
 332         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 333
 334 #define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
 335 #define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
 336
 337 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 338 /* Use the HUSH parser */
 339 #define CFG_HUSH_PARSER
 340 #ifdef  CFG_HUSH_PARSER
 341 #define CFG_PROMPT_HUSH_PS2 "> "
 342 #endif
 343
 344 /* pass open firmware flat tree */
 345 #define CONFIG_OF_LIBFDT        1
 346 #undef  CONFIG_OF_FLAT_TREE
 347 #define CONFIG_OF_BOARD_SETUP   1
 348 #define CONFIG_OF_HAS_BD_T      1
 349 #define CONFIG_OF_HAS_UBOOT_ENV 1
 350
 351
 352 /* maximum size of the flat tree (8K) */
 353 #define OF_FLAT_TREE_MAX_SIZE   8192
 354
 355 #define OF_CPU                  "PowerPC,8360@0"
 356 #define OF_SOC                  "soc8360@e0000000"
 357 #define OF_QE                   "qe@e0100000"
 358 #define OF_TBCLK                (bd->bi_busfreq / 4)
 359 #define OF_STDOUT_PATH          "/soc8360@e0000000/serial@4500"
 360
 361 /* I2C */
 362 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 363 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 364 #define CONFIG_FSL_I2C
 365 #define CFG_I2C_SPEED   400000  /* I2C speed and slave address */
 366 #define CFG_I2C_SLAVE   0x7F
 367 #define CFG_I2C_NOPROBES        {0x52} /* Don't probe these addrs */
 368 #define CFG_I2C_OFFSET  0x3000
 369 #define CFG_I2C2_OFFSET 0x3100
 370
 371 /*
 372  * Config on-board RTC
 373  */
 374 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 375 #define CFG_I2C_RTC_ADDR        0x68    /* at address 0x68 */
 376
 377 /*
 378  * General PCI
 379  * Addresses are mapped 1-1.
 380  */
 381 #define CFG_PCI_MEM_BASE        0x80000000
 382 #define CFG_PCI_MEM_PHYS        CFG_PCI_MEM_BASE
 383 #define CFG_PCI_MEM_SIZE        0x10000000 /* 256M */
 384 #define CFG_PCI_MMIO_BASE       0x90000000
 385 #define CFG_PCI_MMIO_PHYS       CFG_PCI_MMIO_BASE
 386 #define CFG_PCI_MMIO_SIZE       0x10000000 /* 256M */
 387 #define CFG_PCI_IO_BASE         0xE0300000
 388 #define CFG_PCI_IO_PHYS         0xE0300000
 389 #define CFG_PCI_IO_SIZE         0x100000 /* 1M */
 390
 391 #define CFG_PCI_SLV_MEM_LOCAL   CFG_SDRAM_BASE
 392 #define CFG_PCI_SLV_MEM_BUS     0x00000000
 393 #define CFG_PCI_SLV_MEM_SIZE    0x80000000
 394
 395
 396 #ifdef CONFIG_PCI
 397
 398 #define CONFIG_NET_MULTI
 399 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 400
 401 #undef CONFIG_EEPRO100
 402 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 403 #define CFG_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 404
 405 #endif  /* CONFIG_PCI */
 406
 407
 408 #ifndef CONFIG_NET_MULTI
 409 #define CONFIG_NET_MULTI        1
 410 #endif
 411
 412 /*
 413  * QE UEC ethernet configuration
 414  */
 415 #define CONFIG_UEC_ETH
 416 #define CONFIG_ETHPRIME         "Freescale GETH"
 417 #define CONFIG_PHY_MODE_NEED_CHANGE
 418
 419 #define CONFIG_UEC_ETH1         /* GETH1 */
 420
 421 #ifdef CONFIG_UEC_ETH1
 422 #define CFG_UEC1_UCC_NUM        0       /* UCC1 */
 423 #define CFG_UEC1_RX_CLK         QE_CLK_NONE
 424 #define CFG_UEC1_TX_CLK         QE_CLK9
 425 #define CFG_UEC1_ETH_TYPE       GIGA_ETH
 426 #define CFG_UEC1_PHY_ADDR       0
 427 #define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
 428 #endif
 429
 430 #define CONFIG_UEC_ETH2         /* GETH2 */
 431
 432 #ifdef CONFIG_UEC_ETH2
 433 #define CFG_UEC2_UCC_NUM        1       /* UCC2 */
 434 #define CFG_UEC2_RX_CLK         QE_CLK_NONE
 435 #define CFG_UEC2_TX_CLK         QE_CLK4
 436 #define CFG_UEC2_ETH_TYPE       GIGA_ETH
 437 #define CFG_UEC2_PHY_ADDR       1
 438 #define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
 439 #endif
 440
 441 /*
 442  * Environment
 443  */
 444
 445 #ifndef CFG_RAMBOOT
 446         #define CFG_ENV_IS_IN_FLASH     1
 447         #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + 0x40000)
 448         #define CFG_ENV_SECT_SIZE       0x40000 /* 256K(one sector) for env */
 449         #define CFG_ENV_SIZE            0x2000
 450 #else
 451         #define CFG_NO_FLASH            1       /* Flash is not usable now */
 452         #define CFG_ENV_IS_NOWHERE      1       /* Store ENV in memory only */
 453         #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - 0x1000)
 454         #define CFG_ENV_SIZE            0x2000
 455 #endif
 456
 457 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 458 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 459
 460 #if defined(CFG_RAMBOOT)
 461 #if defined(CONFIG_PCI)
 462 #define  CONFIG_COMMANDS        ((CONFIG_CMD_DFL \
 463                                 | CFG_CMD_PING \
 464                                 | CFG_CMD_ASKENV \
 465                                 | CFG_CMD_PCI \
 466                                 | CFG_CMD_I2C) \
 467                                 & \
 468                                 ~(CFG_CMD_ENV \
 469                                 | CFG_CMD_LOADS))
 470 #else
 471 #define  CONFIG_COMMANDS        ((CONFIG_CMD_DFL \
 472                                 | CFG_CMD_PING \
 473                                 | CFG_CMD_ASKENV \
 474                                 | CFG_CMD_I2C) \
 475                                 & \
 476                                 ~(CFG_CMD_ENV \
 477                                 | CFG_CMD_LOADS))
 478 #endif
 479 #else
 480 #if defined(CONFIG_PCI)
 481 #define  CONFIG_COMMANDS        (CONFIG_CMD_DFL \
 482                                 | CFG_CMD_PCI \
 483                                 | CFG_CMD_PING \
 484                                 | CFG_CMD_ASKENV \
 485                                 | CFG_CMD_I2C)
 486 #else
 487 #define  CONFIG_COMMANDS        (CONFIG_CMD_DFL \
 488                                 | CFG_CMD_PING \
 489                                 | CFG_CMD_ASKENV \
 490                                 | CFG_CMD_I2C  )
 491 #endif
 492 #endif
 493
 494 #include <cmd_confdefs.h>
 495
 496 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 497
 498 /*
 499  * Miscellaneous configurable options
 500  */
 501 #define CFG_LONGHELP            /* undef to save memory */
 502 #define CFG_LOAD_ADDR           0x2000000 /* default load address */
 503 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt */
 504
 505 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 506         #define CFG_CBSIZE      1024 /* Console I/O Buffer Size */
 507 #else
 508         #define CFG_CBSIZE      256 /* Console I/O Buffer Size */
 509 #endif
 510
 511 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 512 #define CFG_MAXARGS     16              /* max number of command args */
 513 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 514 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 515
 516 /*
 517  * For booting Linux, the board info and command line data
 518  * have to be in the first 8 MB of memory, since this is
 519  * the maximum mapped by the Linux kernel during initialization.
 520  */
 521 #define CFG_BOOTMAPSZ           (8 << 20) /* Initial Memory map for Linux */
 522
 523 /*
 524  * Core HID Setup
 525  */
 526 #define CFG_HID0_INIT           0x000000000
 527 #define CFG_HID0_FINAL          HID0_ENABLE_MACHINE_CHECK
 528 #define CFG_HID2                HID2_HBE
 529
 530 /*
 531  * Cache Config
 532  */
 533 #define CFG_DCACHE_SIZE         32768
 534 #define CFG_CACHELINE_SIZE      32
 535 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 536 #define CFG_CACHELINE_SHIFT     5 /*log base 2 of the above value */
 537 #endif
 538
 539 /*
 540  * MMU Setup
 541  */
 542
 543 /* DDR: cache cacheable */
 544 #define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 545 #define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 546 #define CFG_DBAT0L      CFG_IBAT0L
 547 #define CFG_DBAT0U      CFG_IBAT0U
 548
 549 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 550 #define CFG_IBAT1L      (CFG_IMMR | BATL_PP_10 | \
 551                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 552 #define CFG_IBAT1U      (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
 553 #define CFG_DBAT1L      CFG_IBAT1L
 554 #define CFG_DBAT1U      CFG_IBAT1U
 555
 556 /* BCSR: cache-inhibit and guarded */
 557 #define CFG_IBAT2L      (CFG_BCSR | BATL_PP_10 | \
 558                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 559 #define CFG_IBAT2U      (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
 560 #define CFG_DBAT2L      CFG_IBAT2L
 561 #define CFG_DBAT2U      CFG_IBAT2U
 562
 563 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 564 #define CFG_IBAT3L      (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 565 #define CFG_IBAT3U      (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
 566 #define CFG_DBAT3L      (CFG_FLASH_BASE | BATL_PP_10 | \
 567                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 568 #define CFG_DBAT3U      CFG_IBAT3U
 569
 570 /* Local bus SDRAM: cacheable */
 571 #define CFG_IBAT4L      (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 572 #define CFG_IBAT4U      (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
 573 #define CFG_DBAT4L      CFG_IBAT4L
 574 #define CFG_DBAT4U      CFG_IBAT4U
 575
 576 /* Stack in dcache: cacheable, no memory coherence */
 577 #define CFG_IBAT5L      (CFG_INIT_RAM_ADDR | BATL_PP_10)
 578 #define CFG_IBAT5U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 579 #define CFG_DBAT5L      CFG_IBAT5L
 580 #define CFG_DBAT5U      CFG_IBAT5U
 581
 582 #ifdef CONFIG_PCI
 583 /* PCI MEM space: cacheable */
 584 #define CFG_IBAT6L      (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 585 #define CFG_IBAT6U      (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 586 #define CFG_DBAT6L      CFG_IBAT6L
 587 #define CFG_DBAT6U      CFG_IBAT6U
 588 /* PCI MMIO space: cache-inhibit and guarded */
 589 #define CFG_IBAT7L      (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
 590                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 591 #define CFG_IBAT7U      (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 592 #define CFG_DBAT7L      CFG_IBAT7L
 593 #define CFG_DBAT7U      CFG_IBAT7U
 594 #else
 595 #define CFG_IBAT6L      (0)
 596 #define CFG_IBAT6U      (0)
 597 #define CFG_IBAT7L      (0)
 598 #define CFG_IBAT7U      (0)
 599 #define CFG_DBAT6L      CFG_IBAT6L
 600 #define CFG_DBAT6U      CFG_IBAT6U
 601 #define CFG_DBAT7L      CFG_IBAT7L
 602 #define CFG_DBAT7U      CFG_IBAT7U
 603 #endif
 604
 605 /*
 606  * Internal Definitions
 607  *
 608  * Boot Flags
 609  */
 610 #define BOOTFLAG_COLD   0x01 /* Normal Power-On: Boot from FLASH */
 611 #define BOOTFLAG_WARM   0x02 /* Software reboot */
 612
 613 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 614 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 615 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 616 #endif
 617
 618 /*
 619  * Environment Configuration
 620  */
 621
 622 #define CONFIG_ENV_OVERWRITE
 623
 624 #if defined(CONFIG_UEC_ETH)
 625 #define CONFIG_ETHADDR  00:04:9f:ef:01:01
 626 #define CONFIG_HAS_ETH1
 627 #define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
 628 #endif
 629
 630 #define CONFIG_BAUDRATE 115200
 631
 632 #define CONFIG_LOADADDR 200000  /* default location for tftp and bootm */
 633
 634 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
 635 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 636
 637 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 638    "netdev=eth0\0"                                                      \
 639    "consoledev=ttyS0\0"                                                 \
 640    "ramdiskaddr=1000000\0"                                              \
 641    "ramdiskfile=ramfs.83xx\0"                                           \
 642    "fdtaddr=400000\0"                                                   \
 643    "fdtfile=mpc8360emds.dtb\0"                                          \
 644    ""
 645
 646 #define CONFIG_NFSBOOTCOMMAND                                           \
 647    "setenv bootargs root=/dev/nfs rw "                                  \
 648       "nfsroot=$serverip:$rootpath "                                    \
 649       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 650       "console=$consoledev,$baudrate $othbootargs;"                     \
 651    "tftp $loadaddr $bootfile;"                                          \
 652    "tftp $fdtaddr $fdtfile;"                                            \
 653    "bootm $loadaddr - $fdtaddr"
 654
 655 #define CONFIG_RAMBOOTCOMMAND                                           \
 656    "setenv bootargs root=/dev/ram rw "                                  \
 657       "console=$consoledev,$baudrate $othbootargs;"                     \
 658    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 659    "tftp $loadaddr $bootfile;"                                          \
 660    "tftp $fdtaddr $fdtfile;"                                            \
 661    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 662
 663
 664 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 665
 666 #endif  /* __CONFIG_H */