include/configs/MPC8536DS.h

   1 /*
   2  * Copyright 2007-2009,2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8536ds board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #include "../board/freescale/common/ics307_clk.h"
  31
  32 #ifdef CONFIG_36BIT
  33 #define CONFIG_PHYS_64BIT       1
  34 #endif
  35
  36 #ifdef CONFIG_NAND
  37 #define CONFIG_NAND_U_BOOT              1
  38 #define CONFIG_RAMBOOT_NAND             1
  39 #ifdef CONFIG_NAND_SPL
  40 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  41 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  42 #else
  43 #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
  44 #define CONFIG_SYS_TEXT_BASE    0xf8f82000
  45 #endif /* CONFIG_NAND_SPL */
  46 #endif
  47
  48 #ifdef CONFIG_SDCARD
  49 #define CONFIG_RAMBOOT_SDCARD           1
  50 #define CONFIG_SYS_TEXT_BASE    0xf8f80000
  51 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  52 #endif
  53
  54 #ifdef CONFIG_SPIFLASH
  55 #define CONFIG_RAMBOOT_SPIFLASH         1
  56 #define CONFIG_SYS_TEXT_BASE    0xf8f80000
  57 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  58 #endif
  59
  60 #ifndef CONFIG_SYS_TEXT_BASE
  61 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  62 #endif
  63
  64 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  65 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  66 #endif
  67
  68 #ifndef CONFIG_SYS_MONITOR_BASE
  69 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  70 #endif
  71
  72 /* High Level Configuration Options */
  73 #define CONFIG_BOOKE            1       /* BOOKE */
  74 #define CONFIG_E500             1       /* BOOKE e500 family */
  75 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  76 #define CONFIG_MPC8536          1
  77 #define CONFIG_MPC8536DS        1
  78
  79 #define CONFIG_FSL_ELBC         1       /* Has Enhanced localbus controller */
  80 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  81 #define CONFIG_PCI1             1       /* Enable PCI controller 1 */
  82 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  83 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  84 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  85 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  86 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  87 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  88
  89 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  90 #define CONFIG_E1000            1       /* Defind e1000 pci Ethernet card*/
  91
  92 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  93 #define CONFIG_ENV_OVERWRITE
  94
  95 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  96 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
  97 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
  98
  99 /*
 100  * These can be toggled for performance analysis, otherwise use default.
 101  */
 102 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 103 #define CONFIG_BTB                      /* toggle branch predition */
 104
 105 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
 106
 107 #define CONFIG_ENABLE_36BIT_PHYS        1
 108
 109 #ifdef CONFIG_PHYS_64BIT
 110 #define CONFIG_ADDR_MAP                 1
 111 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 112 #endif
 113
 114 #define CONFIG_SYS_MEMTEST_START 0x00010000     /* skip exception vectors */
 115 #define CONFIG_SYS_MEMTEST_END   0x1f000000     /* skip u-boot at top of RAM */
 116 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 117
 118 /*
 119  * Config the L2 Cache as L2 SRAM
 120  */
 121 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 122 #ifdef CONFIG_PHYS_64BIT
 123 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8f80000ull
 124 #else
 125 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 126 #endif
 127 #define CONFIG_SYS_L2_SIZE              (512 << 10)
 128 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 129
 130 /*
 131  * Base addresses -- Note these are effective addresses where the
 132  * actual resources get mapped (not physical addresses)
 133  */
 134 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
 135 #ifdef CONFIG_PHYS_64BIT
 136 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
 137 #else
 138 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
 139 #endif
 140 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
 141
 142 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
 143 #define CONFIG_SYS_CCSRBAR_DEFAULT      CONFIG_SYS_CCSRBAR
 144 #else
 145 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
 146 #endif
 147
 148 /* DDR Setup */
 149 #define CONFIG_VERY_BIG_RAM
 150 #define CONFIG_FSL_DDR2
 151 #undef CONFIG_FSL_DDR_INTERACTIVE
 152 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 153 #define CONFIG_DDR_SPD
 154
 155 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 156 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 157
 158 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 159 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 160
 161 #define CONFIG_NUM_DDR_CONTROLLERS      1
 162 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 163 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 164
 165 /* I2C addresses of SPD EEPROMs */
 166 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 167 #define CONFIG_SYS_SPD_BUS_NUM          1
 168
 169 /* These are used when DDR doesn't use SPD. */
 170 #define CONFIG_SYS_SDRAM_SIZE           256     /* DDR is 256MB */
 171 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
 172 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102 /* Enable, no interleaving */
 173 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 174 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 175 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
 176 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 177 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 178 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 179 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
 180 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 181 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 182 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 183 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 184 #define CONFIG_SYS_DDR_CONTROL  0xC3008000      /* Type = DDR2 */
 185 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
 186
 187 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 188 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 189 #define CONFIG_SYS_DDR_SBE              0x00010000
 190
 191 /* Make sure required options are set */
 192 #ifndef CONFIG_SPD_EEPROM
 193 #error ("CONFIG_SPD_EEPROM is required")
 194 #endif
 195
 196 #undef CONFIG_CLOCKS_IN_MHZ
 197
 198
 199 /*
 200  * Memory map -- xxx -this is wrong, needs updating
 201  *
 202  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 203  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 204  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 205  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 206  *
 207  * Localbus cacheable (TBD)
 208  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 209  *
 210  * Localbus non-cacheable
 211  * 0xe000_0000  0xe7ff_ffff     Promjet/free            128M non-cacheable
 212  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 213  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 214  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 215  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 216  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 217  */
 218
 219 /*
 220  * Local Bus Definitions
 221  */
 222 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* start of FLASH 128M */
 223 #ifdef CONFIG_PHYS_64BIT
 224 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 225 #else
 226 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 227 #endif
 228
 229 #define CONFIG_FLASH_BR_PRELIM \
 230                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
 231                  | BR_PS_16 | BR_V)
 232 #define CONFIG_FLASH_OR_PRELIM  0xf8000ff7
 233
 234 #define CONFIG_SYS_BR1_PRELIM \
 235                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 236                  | BR_PS_16 | BR_V)
 237 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 238
 239 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
 240                                       CONFIG_SYS_FLASH_BASE_PHYS }
 241 #define CONFIG_SYS_FLASH_QUIET_TEST
 242 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 243
 244 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 245 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 246 #undef  CONFIG_SYS_FLASH_CHECKSUM
 247 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 248 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 249
 250 #if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
 251     defined(CONFIG_RAMBOOT_SPIFLASH)
 252 #define CONFIG_SYS_RAMBOOT
 253 #define CONFIG_SYS_EXTRA_ENV_RELOC
 254 #else
 255 #undef CONFIG_SYS_RAMBOOT
 256 #endif
 257
 258 #define CONFIG_FLASH_CFI_DRIVER
 259 #define CONFIG_SYS_FLASH_CFI
 260 #define CONFIG_SYS_FLASH_EMPTY_INFO
 261 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 262
 263 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 264
 265 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 266 #define PIXIS_BASE      0xffdf0000      /* PIXIS registers */
 267 #ifdef CONFIG_PHYS_64BIT
 268 #define PIXIS_BASE_PHYS 0xfffdf0000ull
 269 #else
 270 #define PIXIS_BASE_PHYS PIXIS_BASE
 271 #endif
 272
 273 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 274 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 275
 276 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 277 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 278 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 279 #define PIXIS_CSR               0x3     /* PIXIS General control/status register */
 280 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 281 #define PIXIS_PWR               0x5     /* PIXIS Power status register */
 282 #define PIXIS_AUX               0x6     /* Auxiliary 1 register */
 283 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 284 #define PIXIS_AUX2              0x8     /* Auxiliary 2 register */
 285 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 286 #define PIXIS_VSTAT             0x11    /* VELA Status Register */
 287 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 288 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 289 #define PIXIS_VCORE0            0x14    /* VELA VCORE0 Register */
 290 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 291 #define PIXIS_VBOOT_LBMAP       0xe0    /* VBOOT - CFG_LBMAP */
 292 #define PIXIS_VBOOT_LBMAP_NOR0  0x00    /* cfg_lbmap - boot from NOR 0 */
 293 #define PIXIS_VBOOT_LBMAP_NOR1  0x01    /* cfg_lbmap - boot from NOR 1 */
 294 #define PIXIS_VBOOT_LBMAP_NOR2  0x02    /* cfg_lbmap - boot from NOR 2 */
 295 #define PIXIS_VBOOT_LBMAP_NOR3  0x03    /* cfg_lbmap - boot from NOR 3 */
 296 #define PIXIS_VBOOT_LBMAP_PJET  0x04    /* cfg_lbmap - boot from projet */
 297 #define PIXIS_VBOOT_LBMAP_NAND  0x05    /* cfg_lbmap - boot from NAND */
 298 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 299 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 300 #define PIXIS_VSPEED2           0x19    /* VELA VSpeed 2 */
 301 #define PIXIS_VSYSCLK0          0x1A    /* VELA SYSCLK0 Register */
 302 #define PIXIS_VSYSCLK1          0x1B    /* VELA SYSCLK1 Register */
 303 #define PIXIS_VSYSCLK2          0x1C    /* VELA SYSCLK2 Register */
 304 #define PIXIS_VDDRCLK0          0x1D    /* VELA DDRCLK0 Register */
 305 #define PIXIS_VDDRCLK1          0x1E    /* VELA DDRCLK1 Register */
 306 #define PIXIS_VDDRCLK2          0x1F    /* VELA DDRCLK2 Register */
 307 #define PIXIS_VWATCH            0x24    /* Watchdog Register */
 308 #define PIXIS_LED               0x25    /* LED Register */
 309
 310 #define PIXIS_SPD_SYSCLK        0x7     /* SYSCLK option */
 311
 312 /* old pixis referenced names */
 313 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 314 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 315 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x4e
 316
 317 #define CONFIG_SYS_INIT_RAM_LOCK        1
 318 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 319 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000      /* Size of used area in RAM */
 320
 321 #define CONFIG_SYS_GBL_DATA_OFFSET \
 322                 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 323 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 324
 325 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024) /* Reserve 256 kB for Mon */
 326 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)   /* Reserved for malloc */
 327
 328 #ifndef CONFIG_NAND_SPL
 329 #define CONFIG_SYS_NAND_BASE            0xffa00000
 330 #ifdef CONFIG_PHYS_64BIT
 331 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 332 #else
 333 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 334 #endif
 335 #else
 336 #define CONFIG_SYS_NAND_BASE            0xfff00000
 337 #ifdef CONFIG_PHYS_64BIT
 338 #define CONFIG_SYS_NAND_BASE_PHYS       0xffff00000ull
 339 #else
 340 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 341 #endif
 342 #endif
 343 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
 344                                 CONFIG_SYS_NAND_BASE + 0x40000, \
 345                                 CONFIG_SYS_NAND_BASE + 0x80000, \
 346                                 CONFIG_SYS_NAND_BASE + 0xC0000}
 347 #define CONFIG_SYS_MAX_NAND_DEVICE      4
 348 #define CONFIG_MTD_NAND_VERIFY_WRITE
 349 #define CONFIG_CMD_NAND         1
 350 #define CONFIG_NAND_FSL_ELBC    1
 351 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 352
 353 /* NAND boot: 4K NAND loader config */
 354 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 355 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) - 0x2000)
 356 #define CONFIG_SYS_NAND_U_BOOT_DST      (CONFIG_SYS_INIT_L2_ADDR)
 357 #define CONFIG_SYS_NAND_U_BOOT_START \
 358                 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 359 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 360 #define CONFIG_SYS_NAND_U_BOOT_RELOC    (CONFIG_SYS_INIT_L2_END - 0x2000)
 361 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 362
 363 /* NAND flash config */
 364 #define CONFIG_SYS_NAND_BR_PRELIM \
 365                 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 366                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 367                 | BR_PS_8               /* Port Size = 8 bit */ \
 368                 | BR_MS_FCM             /* MSEL = FCM */ \
 369                 | BR_V)                 /* valid */
 370 #define CONFIG_SYS_NAND_OR_PRELIM       (0xFFFC0000     /* length 256K */ \
 371                 | OR_FCM_PGS            /* Large Page*/ \
 372                 | OR_FCM_CSCT \
 373                 | OR_FCM_CST \
 374                 | OR_FCM_CHT \
 375                 | OR_FCM_SCY_1 \
 376                 | OR_FCM_TRLX \
 377                 | OR_FCM_EHTR)
 378
 379 #ifdef CONFIG_RAMBOOT_NAND
 380 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 381 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 382 #define CONFIG_SYS_BR2_PRELIM  CONFIG_FLASH_BR_PRELIM   /* NOR Base Address */
 383 #define CONFIG_SYS_OR2_PRELIM  CONFIG_FLASH_OR_PRELIM   /* NOR Options */
 384 #else
 385 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM   /* NOR Base Address */
 386 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM   /* NOR Options */
 387 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 388 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 389 #endif
 390
 391 #define CONFIG_SYS_BR4_PRELIM \
 392                 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
 393                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 394                 | BR_PS_8               /* Port Size = 8 bit */ \
 395                 | BR_MS_FCM             /* MSEL = FCM */ \
 396                 | BR_V)                 /* valid */
 397 #define CONFIG_SYS_OR4_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 398 #define CONFIG_SYS_BR5_PRELIM \
 399                 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \
 400                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 401                 | BR_PS_8               /* Port Size = 8 bit */ \
 402                 | BR_MS_FCM             /* MSEL = FCM */ \
 403                 | BR_V)                 /* valid */
 404 #define CONFIG_SYS_OR5_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 405
 406 #define CONFIG_SYS_BR6_PRELIM \
 407                 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \
 408                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 409                 | BR_PS_8               /* Port Size = 8 bit */ \
 410                 | BR_MS_FCM             /* MSEL = FCM */ \
 411                 | BR_V)                 /* valid */
 412 #define CONFIG_SYS_OR6_PRELIM   CONFIG_SYS_NAND_OR_PRELIM       /* NAND Options */
 413
 414 /* Serial Port - controlled on board with jumper J8
 415  * open - index 2
 416  * shorted - index 1
 417  */
 418 #define CONFIG_CONS_INDEX       1
 419 #define CONFIG_SYS_NS16550
 420 #define CONFIG_SYS_NS16550_SERIAL
 421 #define CONFIG_SYS_NS16550_REG_SIZE     1
 422 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 423 #ifdef CONFIG_NAND_SPL
 424 #define CONFIG_NS16550_MIN_FUNCTIONS
 425 #endif
 426
 427 #define CONFIG_SYS_BAUDRATE_TABLE       \
 428         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 429
 430 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
 431 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
 432
 433 /* Use the HUSH parser */
 434 #define CONFIG_SYS_HUSH_PARSER
 435 #ifdef  CONFIG_SYS_HUSH_PARSER
 436 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 437 #endif
 438
 439 /*
 440  * Pass open firmware flat tree
 441  */
 442 #define CONFIG_OF_LIBFDT                1
 443 #define CONFIG_OF_BOARD_SETUP           1
 444 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 445
 446 /*
 447  * I2C
 448  */
 449 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 450 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 451 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 452 #define CONFIG_I2C_MULTI_BUS
 453 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 454 #define CONFIG_SYS_I2C_SLAVE            0x7F
 455 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}     /* Don't probe these addrs */
 456 #define CONFIG_SYS_I2C_OFFSET           0x3000
 457 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 458
 459 /*
 460  * I2C2 EEPROM
 461  */
 462 #define CONFIG_ID_EEPROM
 463 #ifdef CONFIG_ID_EEPROM
 464 #define CONFIG_SYS_I2C_EEPROM_NXID
 465 #endif
 466 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 467 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 468 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 469
 470 /*
 471  * General PCI
 472  * Memory space is mapped 1-1, but I/O space must start from 0.
 473  */
 474
 475 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 476 #ifdef CONFIG_PHYS_64BIT
 477 #define CONFIG_SYS_PCI1_MEM_BUS         0xf0000000
 478 #define CONFIG_SYS_PCI1_MEM_PHYS        0xc00000000ull
 479 #else
 480 #define CONFIG_SYS_PCI1_MEM_BUS         0x80000000
 481 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 482 #endif
 483 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 484 #define CONFIG_SYS_PCI1_IO_VIRT         0xffc00000
 485 #define CONFIG_SYS_PCI1_IO_BUS          0x00000000
 486 #ifdef CONFIG_PHYS_64BIT
 487 #define CONFIG_SYS_PCI1_IO_PHYS         0xfffc00000ull
 488 #else
 489 #define CONFIG_SYS_PCI1_IO_PHYS         0xffc00000
 490 #endif
 491 #define CONFIG_SYS_PCI1_IO_SIZE         0x00010000      /* 64k */
 492
 493 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 494 #define CONFIG_SYS_PCIE1_NAME           "Slot 1"
 495 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x90000000
 496 #ifdef CONFIG_PHYS_64BIT
 497 #define CONFIG_SYS_PCIE1_MEM_BUS        0xf8000000
 498 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc10000000ull
 499 #else
 500 #define CONFIG_SYS_PCIE1_MEM_BUS        0x90000000
 501 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x90000000
 502 #endif
 503 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x08000000      /* 128M */
 504 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc10000
 505 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 506 #ifdef CONFIG_PHYS_64BIT
 507 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc10000ull
 508 #else
 509 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc10000
 510 #endif
 511 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 512
 513 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 514 #define CONFIG_SYS_PCIE2_NAME           "Slot 2"
 515 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x98000000
 516 #ifdef CONFIG_PHYS_64BIT
 517 #define CONFIG_SYS_PCIE2_MEM_BUS        0xf8000000
 518 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc18000000ull
 519 #else
 520 #define CONFIG_SYS_PCIE2_MEM_BUS        0x98000000
 521 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x98000000
 522 #endif
 523 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x08000000      /* 128M */
 524 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc20000
 525 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 526 #ifdef CONFIG_PHYS_64BIT
 527 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc20000ull
 528 #else
 529 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc20000
 530 #endif
 531 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 532
 533 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
 534 #define CONFIG_SYS_PCIE3_NAME           "Slot 3"
 535 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 536 #ifdef CONFIG_PHYS_64BIT
 537 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 538 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 539 #else
 540 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 541 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 542 #endif
 543 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 544 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc30000
 545 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 546 #ifdef CONFIG_PHYS_64BIT
 547 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc30000ull
 548 #else
 549 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc30000
 550 #endif
 551 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 552
 553 #if defined(CONFIG_PCI)
 554
 555 #define CONFIG_NET_MULTI
 556 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 557
 558 /*PCIE video card used*/
 559 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE3_IO_VIRT
 560
 561 /*PCI video card used*/
 562 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCI1_IO_VIRT*/
 563
 564 /* video */
 565 #define CONFIG_VIDEO
 566
 567 #if defined(CONFIG_VIDEO)
 568 #define CONFIG_BIOSEMU
 569 #define CONFIG_CFB_CONSOLE
 570 #define CONFIG_VIDEO_SW_CURSOR
 571 #define CONFIG_VGA_AS_SINGLE_DEVICE
 572 #define CONFIG_ATI_RADEON_FB
 573 #define CONFIG_VIDEO_LOGO
 574 /*#define CONFIG_CONSOLE_CURSOR*/
 575 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
 576 #endif
 577
 578 #undef CONFIG_EEPRO100
 579 #undef CONFIG_TULIP
 580 #undef CONFIG_RTL8139
 581
 582 #ifndef CONFIG_PCI_PNP
 583         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BUS
 584         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BUS
 585         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 586 #endif
 587
 588 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 589
 590 #endif  /* CONFIG_PCI */
 591
 592 /* SATA */
 593 #define CONFIG_LIBATA
 594 #define CONFIG_FSL_SATA
 595
 596 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 597 #define CONFIG_SATA1
 598 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 599 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 600 #define CONFIG_SATA2
 601 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 602 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 603
 604 #ifdef CONFIG_FSL_SATA
 605 #define CONFIG_LBA48
 606 #define CONFIG_CMD_SATA
 607 #define CONFIG_DOS_PARTITION
 608 #define CONFIG_CMD_EXT2
 609 #endif
 610
 611 #if defined(CONFIG_TSEC_ENET)
 612
 613 #ifndef CONFIG_NET_MULTI
 614 #define CONFIG_NET_MULTI        1
 615 #endif
 616
 617 #define CONFIG_MII              1       /* MII PHY management */
 618 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 619 #define CONFIG_TSEC1    1
 620 #define CONFIG_TSEC1_NAME       "eTSEC1"
 621 #define CONFIG_TSEC3    1
 622 #define CONFIG_TSEC3_NAME       "eTSEC3"
 623
 624 #define CONFIG_FSL_SGMII_RISER  1
 625 #define SGMII_RISER_PHY_OFFSET  0x1c
 626
 627 #define TSEC1_PHY_ADDR          1       /* TSEC1 -> PHY1 */
 628 #define TSEC3_PHY_ADDR          0       /* TSEC3 -> PHY0 */
 629
 630 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 631 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 632
 633 #define TSEC1_PHYIDX            0
 634 #define TSEC3_PHYIDX            0
 635
 636 #define CONFIG_ETHPRIME         "eTSEC1"
 637
 638 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 639
 640 #endif  /* CONFIG_TSEC_ENET */
 641
 642 /*
 643  * Environment
 644  */
 645
 646 #if defined(CONFIG_SYS_RAMBOOT)
 647 #if defined(CONFIG_RAMBOOT_NAND)
 648         #define CONFIG_ENV_IS_IN_NAND   1
 649         #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 650         #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 651 #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
 652         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 653         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 654         #define CONFIG_ENV_SIZE         0x2000
 655 #endif
 656 #else
 657         #define CONFIG_ENV_IS_IN_FLASH  1
 658         #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 659         #define CONFIG_ENV_ADDR         0xfff80000
 660         #else
 661         #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 662         #endif
 663         #define CONFIG_ENV_SIZE         0x2000
 664         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 665 #endif
 666
 667 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 668 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 669
 670 /*
 671  * Command line configuration.
 672  */
 673 #include <config_cmd_default.h>
 674
 675 #define CONFIG_CMD_IRQ
 676 #define CONFIG_CMD_PING
 677 #define CONFIG_CMD_I2C
 678 #define CONFIG_CMD_MII
 679 #define CONFIG_CMD_ELF
 680 #define CONFIG_CMD_IRQ
 681 #define CONFIG_CMD_SETEXPR
 682 #define CONFIG_CMD_REGINFO
 683
 684 #if defined(CONFIG_PCI)
 685 #define CONFIG_CMD_PCI
 686 #define CONFIG_CMD_NET
 687 #endif
 688
 689 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 690
 691 #define CONFIG_MMC     1
 692
 693 #ifdef CONFIG_MMC
 694 #define CONFIG_FSL_ESDHC
 695 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 696 #define CONFIG_CMD_MMC
 697 #define CONFIG_GENERIC_MMC
 698 #define CONFIG_CMD_EXT2
 699 #define CONFIG_CMD_FAT
 700 #define CONFIG_DOS_PARTITION
 701 #endif
 702
 703 /*
 704  * Miscellaneous configurable options
 705  */
 706 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 707 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 708 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 709 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 710 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 711 #if defined(CONFIG_CMD_KGDB)
 712 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 713 #else
 714 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 715 #endif
 716 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE \
 717                 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
 718 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 719 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
 720 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 721
 722 /*
 723  * For booting Linux, the board info and command line data
 724  * have to be in the first 64 MB of memory, since this is
 725  * the maximum mapped by the Linux kernel during initialization.
 726  */
 727 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 728 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 729
 730 #if defined(CONFIG_CMD_KGDB)
 731 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 732 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 733 #endif
 734
 735 /*
 736  * Environment Configuration
 737  */
 738
 739 /* The mac addresses for all ethernet interface */
 740 #if defined(CONFIG_TSEC_ENET)
 741 #define CONFIG_HAS_ETH0
 742 #define CONFIG_ETHADDR  00:E0:0C:02:00:FD
 743 #define CONFIG_HAS_ETH1
 744 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
 745 #define CONFIG_HAS_ETH2
 746 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
 747 #define CONFIG_HAS_ETH3
 748 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
 749 #endif
 750
 751 #define CONFIG_IPADDR           192.168.1.254
 752
 753 #define CONFIG_HOSTNAME         unknown
 754 #define CONFIG_ROOTPATH         /opt/nfsroot
 755 #define CONFIG_BOOTFILE         uImage
 756 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 757
 758 #define CONFIG_SERVERIP         192.168.1.1
 759 #define CONFIG_GATEWAYIP        192.168.1.1
 760 #define CONFIG_NETMASK          255.255.255.0
 761
 762 /* default location for tftp and bootm */
 763 #define CONFIG_LOADADDR         1000000
 764
 765 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 766 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 767
 768 #define CONFIG_BAUDRATE 115200
 769
 770 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 771  "netdev=eth0\0"                                                \
 772  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 773  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 774         "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "     \
 775         "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "           \
 776         "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "   \
 777         "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "              \
 778         "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"  \
 779  "consoledev=ttyS0\0"                           \
 780  "ramdiskaddr=2000000\0"                        \
 781  "ramdiskfile=8536ds/ramdisk.uboot\0"           \
 782  "fdtaddr=c00000\0"                             \
 783  "fdtfile=8536ds/mpc8536ds.dtb\0"               \
 784  "bdev=sda3\0"                                  \
 785  "usb_phy_type=ulpi\0"
 786
 787 #define CONFIG_HDBOOT                           \
 788  "setenv bootargs root=/dev/$bdev rw "          \
 789  "console=$consoledev,$baudrate $othbootargs;"  \
 790  "tftp $loadaddr $bootfile;"                    \
 791  "tftp $fdtaddr $fdtfile;"                      \
 792  "bootm $loadaddr - $fdtaddr"
 793
 794 #define CONFIG_NFSBOOTCOMMAND           \
 795  "setenv bootargs root=/dev/nfs rw "    \
 796  "nfsroot=$serverip:$rootpath "         \
 797  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 798  "console=$consoledev,$baudrate $othbootargs;"  \
 799  "tftp $loadaddr $bootfile;"            \
 800  "tftp $fdtaddr $fdtfile;"              \
 801  "bootm $loadaddr - $fdtaddr"
 802
 803 #define CONFIG_RAMBOOTCOMMAND           \
 804  "setenv bootargs root=/dev/ram rw "    \
 805  "console=$consoledev,$baudrate $othbootargs;"  \
 806  "tftp $ramdiskaddr $ramdiskfile;"      \
 807  "tftp $loadaddr $bootfile;"            \
 808  "tftp $fdtaddr $fdtfile;"              \
 809  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 810
 811 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 812
 813 #endif  /* __CONFIG_H */