include/configs/MPC8536DS.h

   1 /*
   2  * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8536ds board configuration file
   9  *
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include "../board/freescale/common/ics307_clk.h"
  15
  16 #ifdef CONFIG_SDCARD
  17 #define CONFIG_RAMBOOT_SDCARD           1
  18 #define CONFIG_SYS_TEXT_BASE    0xf8f40000
  19 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  20 #endif
  21
  22 #ifdef CONFIG_SPIFLASH
  23 #define CONFIG_RAMBOOT_SPIFLASH         1
  24 #define CONFIG_SYS_TEXT_BASE    0xf8f40000
  25 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  26 #endif
  27
  28 #ifndef CONFIG_SYS_TEXT_BASE
  29 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  30 #endif
  31
  32 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  33 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  34 #endif
  35
  36 #ifndef CONFIG_SYS_MONITOR_BASE
  37 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  38 #endif
  39
  40 #define CONFIG_PCI1             1       /* Enable PCI controller 1 */
  41 #define CONFIG_PCIE1            1       /* PCIE controller 1 (slot 1) */
  42 #define CONFIG_PCIE2            1       /* PCIE controller 2 (slot 2) */
  43 #define CONFIG_PCIE3            1       /* PCIE controller 3 (ULI bridge) */
  44 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  45 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  46 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  47 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  48
  49
  50 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  51 #define CONFIG_ENV_OVERWRITE
  52
  53 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  54 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
  55 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
  56
  57 /*
  58  * These can be toggled for performance analysis, otherwise use default.
  59  */
  60 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  61 #define CONFIG_BTB                      /* toggle branch predition */
  62
  63 #define CONFIG_ENABLE_36BIT_PHYS        1
  64
  65 #ifdef CONFIG_PHYS_64BIT
  66 #define CONFIG_ADDR_MAP                 1
  67 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  68 #endif
  69
  70 #define CONFIG_SYS_MEMTEST_START 0x00010000     /* skip exception vectors */
  71 #define CONFIG_SYS_MEMTEST_END   0x1f000000     /* skip u-boot at top of RAM */
  72 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  73
  74 /*
  75  * Config the L2 Cache as L2 SRAM
  76  */
  77 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
  78 #ifdef CONFIG_PHYS_64BIT
  79 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8f80000ull
  80 #else
  81 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
  82 #endif
  83 #define CONFIG_SYS_L2_SIZE              (512 << 10)
  84 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  85
  86 #define CONFIG_SYS_CCSRBAR              0xffe00000
  87 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  88
  89 #if defined(CONFIG_NAND_SPL)
  90 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  91 #endif
  92
  93 /* DDR Setup */
  94 #define CONFIG_VERY_BIG_RAM
  95 #undef CONFIG_FSL_DDR_INTERACTIVE
  96 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  97 #define CONFIG_DDR_SPD
  98
  99 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 100 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 101
 102 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 103 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 104
 105 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 106 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 107
 108 /* I2C addresses of SPD EEPROMs */
 109 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 110 #define CONFIG_SYS_SPD_BUS_NUM          1
 111
 112 /* These are used when DDR doesn't use SPD. */
 113 #define CONFIG_SYS_SDRAM_SIZE           256     /* DDR is 256MB */
 114 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
 115 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102 /* Enable, no interleaving */
 116 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 117 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 118 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
 119 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 120 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 121 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 122 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
 123 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 124 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 125 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 126 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 127 #define CONFIG_SYS_DDR_CONTROL  0xC3008000      /* Type = DDR2 */
 128 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
 129
 130 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 131 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 132 #define CONFIG_SYS_DDR_SBE              0x00010000
 133
 134 /* Make sure required options are set */
 135 #ifndef CONFIG_SPD_EEPROM
 136 #error ("CONFIG_SPD_EEPROM is required")
 137 #endif
 138
 139 #undef CONFIG_CLOCKS_IN_MHZ
 140
 141 /*
 142  * Memory map -- xxx -this is wrong, needs updating
 143  *
 144  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 145  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 146  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 147  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 148  *
 149  * Localbus cacheable (TBD)
 150  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 151  *
 152  * Localbus non-cacheable
 153  * 0xe000_0000  0xe7ff_ffff     Promjet/free            128M non-cacheable
 154  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 155  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 156  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 157  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 158  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 159  */
 160
 161 /*
 162  * Local Bus Definitions
 163  */
 164 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* start of FLASH 128M */
 165 #ifdef CONFIG_PHYS_64BIT
 166 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 167 #else
 168 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 169 #endif
 170
 171 #define CONFIG_FLASH_BR_PRELIM \
 172         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
 173 #define CONFIG_FLASH_OR_PRELIM  0xf8000ff7
 174
 175 #define CONFIG_SYS_BR1_PRELIM \
 176                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 177                  | BR_PS_16 | BR_V)
 178 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 179
 180 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
 181                                       CONFIG_SYS_FLASH_BASE_PHYS }
 182 #define CONFIG_SYS_FLASH_QUIET_TEST
 183 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 184
 185 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 186 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 187 #undef  CONFIG_SYS_FLASH_CHECKSUM
 188 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 189 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 190
 191 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
 192 #define CONFIG_SYS_RAMBOOT
 193 #define CONFIG_SYS_EXTRA_ENV_RELOC
 194 #else
 195 #undef CONFIG_SYS_RAMBOOT
 196 #endif
 197
 198 #define CONFIG_FLASH_CFI_DRIVER
 199 #define CONFIG_SYS_FLASH_CFI
 200 #define CONFIG_SYS_FLASH_EMPTY_INFO
 201 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 202
 203 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 204
 205 #define CONFIG_HWCONFIG                 /* enable hwconfig */
 206 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 207 #define PIXIS_BASE      0xffdf0000      /* PIXIS registers */
 208 #ifdef CONFIG_PHYS_64BIT
 209 #define PIXIS_BASE_PHYS 0xfffdf0000ull
 210 #else
 211 #define PIXIS_BASE_PHYS PIXIS_BASE
 212 #endif
 213
 214 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 215 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 216
 217 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 218 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 219 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 220 #define PIXIS_CSR               0x3     /* PIXIS General control/status register */
 221 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 222 #define PIXIS_PWR               0x5     /* PIXIS Power status register */
 223 #define PIXIS_AUX               0x6     /* Auxiliary 1 register */
 224 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 225 #define PIXIS_AUX2              0x8     /* Auxiliary 2 register */
 226 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 227 #define PIXIS_VSTAT             0x11    /* VELA Status Register */
 228 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 229 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 230 #define PIXIS_VCORE0            0x14    /* VELA VCORE0 Register */
 231 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 232 #define PIXIS_VBOOT_LBMAP       0xe0    /* VBOOT - CFG_LBMAP */
 233 #define PIXIS_VBOOT_LBMAP_NOR0  0x00    /* cfg_lbmap - boot from NOR 0 */
 234 #define PIXIS_VBOOT_LBMAP_NOR1  0x01    /* cfg_lbmap - boot from NOR 1 */
 235 #define PIXIS_VBOOT_LBMAP_NOR2  0x02    /* cfg_lbmap - boot from NOR 2 */
 236 #define PIXIS_VBOOT_LBMAP_NOR3  0x03    /* cfg_lbmap - boot from NOR 3 */
 237 #define PIXIS_VBOOT_LBMAP_PJET  0x04    /* cfg_lbmap - boot from projet */
 238 #define PIXIS_VBOOT_LBMAP_NAND  0x05    /* cfg_lbmap - boot from NAND */
 239 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 240 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 241 #define PIXIS_VSPEED2           0x19    /* VELA VSpeed 2 */
 242 #define PIXIS_VSYSCLK0          0x1A    /* VELA SYSCLK0 Register */
 243 #define PIXIS_VSYSCLK1          0x1B    /* VELA SYSCLK1 Register */
 244 #define PIXIS_VSYSCLK2          0x1C    /* VELA SYSCLK2 Register */
 245 #define PIXIS_VDDRCLK0          0x1D    /* VELA DDRCLK0 Register */
 246 #define PIXIS_VDDRCLK1          0x1E    /* VELA DDRCLK1 Register */
 247 #define PIXIS_VDDRCLK2          0x1F    /* VELA DDRCLK2 Register */
 248 #define PIXIS_VWATCH            0x24    /* Watchdog Register */
 249 #define PIXIS_LED               0x25    /* LED Register */
 250
 251 #define PIXIS_SPD_SYSCLK        0x7     /* SYSCLK option */
 252
 253 /* old pixis referenced names */
 254 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 255 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 256 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x4e
 257
 258 #define CONFIG_SYS_INIT_RAM_LOCK        1
 259 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 260 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000      /* Size of used area in RAM */
 261
 262 #define CONFIG_SYS_GBL_DATA_OFFSET \
 263                 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 264 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 265
 266 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024) /* Reserve 256 kB for Mon */
 267 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)   /* Reserved for malloc */
 268
 269 #ifndef CONFIG_NAND_SPL
 270 #define CONFIG_SYS_NAND_BASE            0xffa00000
 271 #ifdef CONFIG_PHYS_64BIT
 272 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 273 #else
 274 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 275 #endif
 276 #else
 277 #define CONFIG_SYS_NAND_BASE            0xfff00000
 278 #ifdef CONFIG_PHYS_64BIT
 279 #define CONFIG_SYS_NAND_BASE_PHYS       0xffff00000ull
 280 #else
 281 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 282 #endif
 283 #endif
 284 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
 285                                 CONFIG_SYS_NAND_BASE + 0x40000, \
 286                                 CONFIG_SYS_NAND_BASE + 0x80000, \
 287                                 CONFIG_SYS_NAND_BASE + 0xC0000}
 288 #define CONFIG_SYS_MAX_NAND_DEVICE      4
 289 #define CONFIG_NAND_FSL_ELBC    1
 290 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 291
 292 /* NAND boot: 4K NAND loader config */
 293 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 294 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
 295 #define CONFIG_SYS_NAND_U_BOOT_DST      (CONFIG_SYS_INIT_L2_ADDR)
 296 #define CONFIG_SYS_NAND_U_BOOT_START \
 297                 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 298 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 299 #define CONFIG_SYS_NAND_U_BOOT_RELOC    (CONFIG_SYS_INIT_L2_END - 0x2000)
 300 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 301
 302 /* NAND flash config */
 303 #define CONFIG_SYS_NAND_BR_PRELIM \
 304                 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 305                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 306                 | BR_PS_8               /* Port Size = 8 bit */ \
 307                 | BR_MS_FCM             /* MSEL = FCM */ \
 308                 | BR_V)                 /* valid */
 309 #define CONFIG_SYS_NAND_OR_PRELIM       (0xFFFC0000     /* length 256K */ \
 310                 | OR_FCM_PGS            /* Large Page*/ \
 311                 | OR_FCM_CSCT \
 312                 | OR_FCM_CST \
 313                 | OR_FCM_CHT \
 314                 | OR_FCM_SCY_1 \
 315                 | OR_FCM_TRLX \
 316                 | OR_FCM_EHTR)
 317
 318 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM   /* NOR Base Address */
 319 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM   /* NOR Options */
 320 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 321 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 322
 323 #define CONFIG_SYS_BR4_PRELIM \
 324                 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
 325                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 326                 | BR_PS_8               /* Port Size = 8 bit */ \
 327                 | BR_MS_FCM             /* MSEL = FCM */ \
 328                 | BR_V)                 /* valid */
 329 #define CONFIG_SYS_OR4_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 330 #define CONFIG_SYS_BR5_PRELIM \
 331                 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
 332                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 333                 | BR_PS_8               /* Port Size = 8 bit */ \
 334                 | BR_MS_FCM             /* MSEL = FCM */ \
 335                 | BR_V)                 /* valid */
 336 #define CONFIG_SYS_OR5_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 337
 338 #define CONFIG_SYS_BR6_PRELIM \
 339                 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
 340                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 341                 | BR_PS_8               /* Port Size = 8 bit */ \
 342                 | BR_MS_FCM             /* MSEL = FCM */ \
 343                 | BR_V)                 /* valid */
 344 #define CONFIG_SYS_OR6_PRELIM   CONFIG_SYS_NAND_OR_PRELIM       /* NAND Options */
 345
 346 /* Serial Port - controlled on board with jumper J8
 347  * open - index 2
 348  * shorted - index 1
 349  */
 350 #define CONFIG_CONS_INDEX       1
 351 #define CONFIG_SYS_NS16550_SERIAL
 352 #define CONFIG_SYS_NS16550_REG_SIZE     1
 353 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 354 #ifdef CONFIG_NAND_SPL
 355 #define CONFIG_NS16550_MIN_FUNCTIONS
 356 #endif
 357
 358 #define CONFIG_SYS_BAUDRATE_TABLE       \
 359         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 360
 361 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
 362 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
 363
 364 /*
 365  * I2C
 366  */
 367 #define CONFIG_SYS_I2C
 368 #define CONFIG_SYS_I2C_FSL
 369 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 370 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 371 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 372 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 373 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 374 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 375 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x29} }
 376
 377 /*
 378  * I2C2 EEPROM
 379  */
 380 #define CONFIG_ID_EEPROM
 381 #ifdef CONFIG_ID_EEPROM
 382 #define CONFIG_SYS_I2C_EEPROM_NXID
 383 #endif
 384 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 385 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 386 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 387
 388 /*
 389  * eSPI - Enhanced SPI
 390  */
 391 #define CONFIG_HARD_SPI
 392
 393 #if defined(CONFIG_SPI_FLASH)
 394 #define CONFIG_SF_DEFAULT_SPEED 10000000
 395 #define CONFIG_SF_DEFAULT_MODE  0
 396 #endif
 397
 398 /*
 399  * General PCI
 400  * Memory space is mapped 1-1, but I/O space must start from 0.
 401  */
 402
 403 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 404 #ifdef CONFIG_PHYS_64BIT
 405 #define CONFIG_SYS_PCI1_MEM_BUS         0xf0000000
 406 #define CONFIG_SYS_PCI1_MEM_PHYS        0xc00000000ull
 407 #else
 408 #define CONFIG_SYS_PCI1_MEM_BUS         0x80000000
 409 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 410 #endif
 411 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 412 #define CONFIG_SYS_PCI1_IO_VIRT         0xffc00000
 413 #define CONFIG_SYS_PCI1_IO_BUS          0x00000000
 414 #ifdef CONFIG_PHYS_64BIT
 415 #define CONFIG_SYS_PCI1_IO_PHYS         0xfffc00000ull
 416 #else
 417 #define CONFIG_SYS_PCI1_IO_PHYS         0xffc00000
 418 #endif
 419 #define CONFIG_SYS_PCI1_IO_SIZE         0x00010000      /* 64k */
 420
 421 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 422 #define CONFIG_SYS_PCIE1_NAME           "Slot 1"
 423 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x90000000
 424 #ifdef CONFIG_PHYS_64BIT
 425 #define CONFIG_SYS_PCIE1_MEM_BUS        0xf8000000
 426 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc10000000ull
 427 #else
 428 #define CONFIG_SYS_PCIE1_MEM_BUS        0x90000000
 429 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x90000000
 430 #endif
 431 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x08000000      /* 128M */
 432 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc10000
 433 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 434 #ifdef CONFIG_PHYS_64BIT
 435 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc10000ull
 436 #else
 437 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc10000
 438 #endif
 439 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 440
 441 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 442 #define CONFIG_SYS_PCIE2_NAME           "Slot 2"
 443 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x98000000
 444 #ifdef CONFIG_PHYS_64BIT
 445 #define CONFIG_SYS_PCIE2_MEM_BUS        0xf8000000
 446 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc18000000ull
 447 #else
 448 #define CONFIG_SYS_PCIE2_MEM_BUS        0x98000000
 449 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x98000000
 450 #endif
 451 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x08000000      /* 128M */
 452 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc20000
 453 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 454 #ifdef CONFIG_PHYS_64BIT
 455 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc20000ull
 456 #else
 457 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc20000
 458 #endif
 459 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 460
 461 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
 462 #define CONFIG_SYS_PCIE3_NAME           "Slot 3"
 463 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 464 #ifdef CONFIG_PHYS_64BIT
 465 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 466 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 467 #else
 468 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 469 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 470 #endif
 471 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 472 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc30000
 473 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 474 #ifdef CONFIG_PHYS_64BIT
 475 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc30000ull
 476 #else
 477 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc30000
 478 #endif
 479 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 480
 481 #if defined(CONFIG_PCI)
 482 /*PCIE video card used*/
 483 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE3_IO_VIRT
 484
 485 /*PCI video card used*/
 486 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCI1_IO_VIRT*/
 487
 488 /* video */
 489
 490 #if defined(CONFIG_VIDEO)
 491 #define CONFIG_BIOSEMU
 492 #define CONFIG_ATI_RADEON_FB
 493 #define CONFIG_VIDEO_LOGO
 494 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
 495 #endif
 496
 497 #undef CONFIG_EEPRO100
 498 #undef CONFIG_TULIP
 499
 500 #ifndef CONFIG_PCI_PNP
 501         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BUS
 502         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BUS
 503         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 504 #endif
 505
 506 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 507
 508 #endif  /* CONFIG_PCI */
 509
 510 /* SATA */
 511 #define CONFIG_LIBATA
 512 #define CONFIG_FSL_SATA
 513
 514 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 515 #define CONFIG_SATA1
 516 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 517 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 518 #define CONFIG_SATA2
 519 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 520 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 521
 522 #ifdef CONFIG_FSL_SATA
 523 #define CONFIG_LBA48
 524 #endif
 525
 526 #if defined(CONFIG_TSEC_ENET)
 527
 528 #define CONFIG_MII              1       /* MII PHY management */
 529 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 530 #define CONFIG_TSEC1    1
 531 #define CONFIG_TSEC1_NAME       "eTSEC1"
 532 #define CONFIG_TSEC3    1
 533 #define CONFIG_TSEC3_NAME       "eTSEC3"
 534
 535 #define CONFIG_FSL_SGMII_RISER  1
 536 #define SGMII_RISER_PHY_OFFSET  0x1c
 537
 538 #define TSEC1_PHY_ADDR          1       /* TSEC1 -> PHY1 */
 539 #define TSEC3_PHY_ADDR          0       /* TSEC3 -> PHY0 */
 540
 541 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 542 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 543
 544 #define TSEC1_PHYIDX            0
 545 #define TSEC3_PHYIDX            0
 546
 547 #define CONFIG_ETHPRIME         "eTSEC1"
 548
 549 #endif  /* CONFIG_TSEC_ENET */
 550
 551 /*
 552  * Environment
 553  */
 554
 555 #if defined(CONFIG_SYS_RAMBOOT)
 556 #if defined(CONFIG_RAMBOOT_SPIFLASH)
 557 #define CONFIG_ENV_SPI_BUS      0
 558 #define CONFIG_ENV_SPI_CS       0
 559 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 560 #define CONFIG_ENV_SPI_MODE     0
 561 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
 562 #define CONFIG_ENV_OFFSET       0xF0000
 563 #define CONFIG_ENV_SECT_SIZE    0x10000
 564 #elif defined(CONFIG_RAMBOOT_SDCARD)
 565 #define CONFIG_FSL_FIXED_MMC_LOCATION
 566 #define CONFIG_ENV_SIZE         0x2000
 567 #define CONFIG_SYS_MMC_ENV_DEV  0
 568 #else
 569         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 570         #define CONFIG_ENV_SIZE         0x2000
 571 #endif
 572 #else
 573         #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 574         #define CONFIG_ENV_SIZE         0x2000
 575         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 576 #endif
 577
 578 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 579 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 580
 581 /*
 582  * Command line configuration.
 583  */
 584 #define CONFIG_CMD_REGINFO
 585
 586 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 587
 588 #ifdef CONFIG_MMC
 589 #define CONFIG_FSL_ESDHC
 590 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 591 #endif
 592
 593 /*
 594  * USB
 595  */
 596 #define CONFIG_HAS_FSL_MPH_USB
 597 #ifdef CONFIG_HAS_FSL_MPH_USB
 598 #ifdef CONFIG_USB_EHCI_HCD
 599 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 600 #define CONFIG_USB_EHCI_FSL
 601 #endif
 602 #endif
 603
 604 /*
 605  * Miscellaneous configurable options
 606  */
 607 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 608 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 609 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 610 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 611 #if defined(CONFIG_CMD_KGDB)
 612 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 613 #else
 614 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 615 #endif
 616 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE \
 617                 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
 618 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 619 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
 620
 621 /*
 622  * For booting Linux, the board info and command line data
 623  * have to be in the first 64 MB of memory, since this is
 624  * the maximum mapped by the Linux kernel during initialization.
 625  */
 626 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 627 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 628
 629 #if defined(CONFIG_CMD_KGDB)
 630 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 631 #endif
 632
 633 /*
 634  * Environment Configuration
 635  */
 636
 637 /* The mac addresses for all ethernet interface */
 638 #if defined(CONFIG_TSEC_ENET)
 639 #define CONFIG_HAS_ETH0
 640 #define CONFIG_HAS_ETH1
 641 #define CONFIG_HAS_ETH2
 642 #define CONFIG_HAS_ETH3
 643 #endif
 644
 645 #define CONFIG_IPADDR           192.168.1.254
 646
 647 #define CONFIG_HOSTNAME         unknown
 648 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 649 #define CONFIG_BOOTFILE         "uImage"
 650 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 651
 652 #define CONFIG_SERVERIP         192.168.1.1
 653 #define CONFIG_GATEWAYIP        192.168.1.1
 654 #define CONFIG_NETMASK          255.255.255.0
 655
 656 /* default location for tftp and bootm */
 657 #define CONFIG_LOADADDR         1000000
 658
 659 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 660
 661 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 662 "netdev=eth0\0"                                         \
 663 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 664 "tftpflash=tftpboot $loadaddr $uboot; "                 \
 665         "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 666                 " +$filesize; " \
 667         "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 668                 " +$filesize; " \
 669         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 670                 " $filesize; "  \
 671         "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 672                 " +$filesize; " \
 673         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 674                 " $filesize\0"  \
 675 "consoledev=ttyS0\0"                            \
 676 "ramdiskaddr=2000000\0"                 \
 677 "ramdiskfile=8536ds/ramdisk.uboot\0"            \
 678 "fdtaddr=1e00000\0"                             \
 679 "fdtfile=8536ds/mpc8536ds.dtb\0"                \
 680 "bdev=sda3\0"                                   \
 681 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
 682
 683 #define CONFIG_HDBOOT                           \
 684  "setenv bootargs root=/dev/$bdev rw "          \
 685  "console=$consoledev,$baudrate $othbootargs;"  \
 686  "tftp $loadaddr $bootfile;"                    \
 687  "tftp $fdtaddr $fdtfile;"                      \
 688  "bootm $loadaddr - $fdtaddr"
 689
 690 #define CONFIG_NFSBOOTCOMMAND           \
 691  "setenv bootargs root=/dev/nfs rw "    \
 692  "nfsroot=$serverip:$rootpath "         \
 693  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 694  "console=$consoledev,$baudrate $othbootargs;"  \
 695  "tftp $loadaddr $bootfile;"            \
 696  "tftp $fdtaddr $fdtfile;"              \
 697  "bootm $loadaddr - $fdtaddr"
 698
 699 #define CONFIG_RAMBOOTCOMMAND           \
 700  "setenv bootargs root=/dev/ram rw "    \
 701  "console=$consoledev,$baudrate $othbootargs;"  \
 702  "tftp $ramdiskaddr $ramdiskfile;"      \
 703  "tftp $loadaddr $bootfile;"            \
 704  "tftp $fdtaddr $fdtfile;"              \
 705  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 706
 707 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 708
 709 #endif  /* __CONFIG_H */