include/configs/MPC8536DS.h

   1 /*
   2  * Copyright 2007-2009,2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8536ds board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #include "../board/freescale/common/ics307_clk.h"
  31
  32 #ifdef CONFIG_36BIT
  33 #define CONFIG_PHYS_64BIT       1
  34 #endif
  35
  36 #ifdef CONFIG_NAND
  37 #define CONFIG_NAND_U_BOOT              1
  38 #define CONFIG_RAMBOOT_NAND             1
  39 #ifdef CONFIG_NAND_SPL
  40 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  41 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  42 #else
  43 #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
  44 #define CONFIG_SYS_TEXT_BASE    0xf8f82000
  45 #endif /* CONFIG_NAND_SPL */
  46 #endif
  47
  48 #ifdef CONFIG_SDCARD
  49 #define CONFIG_RAMBOOT_SDCARD           1
  50 #define CONFIG_SYS_TEXT_BASE    0xf8f80000
  51 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  52 #endif
  53
  54 #ifdef CONFIG_SPIFLASH
  55 #define CONFIG_RAMBOOT_SPIFLASH         1
  56 #define CONFIG_SYS_TEXT_BASE    0xf8f80000
  57 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  58 #endif
  59
  60 #ifndef CONFIG_SYS_TEXT_BASE
  61 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  62 #endif
  63
  64 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  65 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  66 #endif
  67
  68 #ifndef CONFIG_SYS_MONITOR_BASE
  69 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  70 #endif
  71
  72 /* High Level Configuration Options */
  73 #define CONFIG_BOOKE            1       /* BOOKE */
  74 #define CONFIG_E500             1       /* BOOKE e500 family */
  75 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  76 #define CONFIG_MPC8536          1
  77 #define CONFIG_MPC8536DS        1
  78
  79 #define CONFIG_FSL_ELBC         1       /* Has Enhanced localbus controller */
  80 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  81 #define CONFIG_PCI1             1       /* Enable PCI controller 1 */
  82 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  83 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  84 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  85 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  86 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  87 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  88
  89 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  90 #define CONFIG_E1000            1       /* Defind e1000 pci Ethernet card*/
  91
  92 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  93 #define CONFIG_ENV_OVERWRITE
  94
  95 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  96 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
  97 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
  98
  99 /*
 100  * These can be toggled for performance analysis, otherwise use default.
 101  */
 102 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 103 #define CONFIG_BTB                      /* toggle branch predition */
 104
 105 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
 106
 107 #define CONFIG_ENABLE_36BIT_PHYS        1
 108
 109 #ifdef CONFIG_PHYS_64BIT
 110 #define CONFIG_ADDR_MAP                 1
 111 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 112 #endif
 113
 114 #define CONFIG_SYS_MEMTEST_START 0x00010000     /* skip exception vectors */
 115 #define CONFIG_SYS_MEMTEST_END   0x1f000000     /* skip u-boot at top of RAM */
 116 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 117
 118 /*
 119  * Config the L2 Cache as L2 SRAM
 120  */
 121 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 122 #ifdef CONFIG_PHYS_64BIT
 123 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8f80000ull
 124 #else
 125 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 126 #endif
 127 #define CONFIG_SYS_L2_SIZE              (512 << 10)
 128 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 129
 130 #define CONFIG_SYS_CCSRBAR              0xffe00000
 131 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 132
 133 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
 134 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 135 #endif
 136
 137 /* DDR Setup */
 138 #define CONFIG_VERY_BIG_RAM
 139 #define CONFIG_FSL_DDR2
 140 #undef CONFIG_FSL_DDR_INTERACTIVE
 141 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 142 #define CONFIG_DDR_SPD
 143
 144 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 145 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 146
 147 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 148 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 149
 150 #define CONFIG_NUM_DDR_CONTROLLERS      1
 151 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 152 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 153
 154 /* I2C addresses of SPD EEPROMs */
 155 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 156 #define CONFIG_SYS_SPD_BUS_NUM          1
 157
 158 /* These are used when DDR doesn't use SPD. */
 159 #define CONFIG_SYS_SDRAM_SIZE           256     /* DDR is 256MB */
 160 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
 161 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102 /* Enable, no interleaving */
 162 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 163 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 164 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
 165 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 166 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 167 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 168 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
 169 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 170 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 171 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 172 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 173 #define CONFIG_SYS_DDR_CONTROL  0xC3008000      /* Type = DDR2 */
 174 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
 175
 176 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 177 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 178 #define CONFIG_SYS_DDR_SBE              0x00010000
 179
 180 /* Make sure required options are set */
 181 #ifndef CONFIG_SPD_EEPROM
 182 #error ("CONFIG_SPD_EEPROM is required")
 183 #endif
 184
 185 #undef CONFIG_CLOCKS_IN_MHZ
 186
 187
 188 /*
 189  * Memory map -- xxx -this is wrong, needs updating
 190  *
 191  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 192  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 193  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 194  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 195  *
 196  * Localbus cacheable (TBD)
 197  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 198  *
 199  * Localbus non-cacheable
 200  * 0xe000_0000  0xe7ff_ffff     Promjet/free            128M non-cacheable
 201  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 202  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 203  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 204  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 205  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 206  */
 207
 208 /*
 209  * Local Bus Definitions
 210  */
 211 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* start of FLASH 128M */
 212 #ifdef CONFIG_PHYS_64BIT
 213 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 214 #else
 215 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 216 #endif
 217
 218 #define CONFIG_FLASH_BR_PRELIM \
 219                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
 220                  | BR_PS_16 | BR_V)
 221 #define CONFIG_FLASH_OR_PRELIM  0xf8000ff7
 222
 223 #define CONFIG_SYS_BR1_PRELIM \
 224                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 225                  | BR_PS_16 | BR_V)
 226 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 227
 228 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
 229                                       CONFIG_SYS_FLASH_BASE_PHYS }
 230 #define CONFIG_SYS_FLASH_QUIET_TEST
 231 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 232
 233 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 234 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 235 #undef  CONFIG_SYS_FLASH_CHECKSUM
 236 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 237 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 238
 239 #if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
 240     defined(CONFIG_RAMBOOT_SPIFLASH)
 241 #define CONFIG_SYS_RAMBOOT
 242 #define CONFIG_SYS_EXTRA_ENV_RELOC
 243 #else
 244 #undef CONFIG_SYS_RAMBOOT
 245 #endif
 246
 247 #define CONFIG_FLASH_CFI_DRIVER
 248 #define CONFIG_SYS_FLASH_CFI
 249 #define CONFIG_SYS_FLASH_EMPTY_INFO
 250 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 251
 252 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 253
 254 #define CONFIG_HWCONFIG                 /* enable hwconfig */
 255 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 256 #define PIXIS_BASE      0xffdf0000      /* PIXIS registers */
 257 #ifdef CONFIG_PHYS_64BIT
 258 #define PIXIS_BASE_PHYS 0xfffdf0000ull
 259 #else
 260 #define PIXIS_BASE_PHYS PIXIS_BASE
 261 #endif
 262
 263 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 264 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 265
 266 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 267 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 268 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 269 #define PIXIS_CSR               0x3     /* PIXIS General control/status register */
 270 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 271 #define PIXIS_PWR               0x5     /* PIXIS Power status register */
 272 #define PIXIS_AUX               0x6     /* Auxiliary 1 register */
 273 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 274 #define PIXIS_AUX2              0x8     /* Auxiliary 2 register */
 275 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 276 #define PIXIS_VSTAT             0x11    /* VELA Status Register */
 277 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 278 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 279 #define PIXIS_VCORE0            0x14    /* VELA VCORE0 Register */
 280 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 281 #define PIXIS_VBOOT_LBMAP       0xe0    /* VBOOT - CFG_LBMAP */
 282 #define PIXIS_VBOOT_LBMAP_NOR0  0x00    /* cfg_lbmap - boot from NOR 0 */
 283 #define PIXIS_VBOOT_LBMAP_NOR1  0x01    /* cfg_lbmap - boot from NOR 1 */
 284 #define PIXIS_VBOOT_LBMAP_NOR2  0x02    /* cfg_lbmap - boot from NOR 2 */
 285 #define PIXIS_VBOOT_LBMAP_NOR3  0x03    /* cfg_lbmap - boot from NOR 3 */
 286 #define PIXIS_VBOOT_LBMAP_PJET  0x04    /* cfg_lbmap - boot from projet */
 287 #define PIXIS_VBOOT_LBMAP_NAND  0x05    /* cfg_lbmap - boot from NAND */
 288 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 289 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 290 #define PIXIS_VSPEED2           0x19    /* VELA VSpeed 2 */
 291 #define PIXIS_VSYSCLK0          0x1A    /* VELA SYSCLK0 Register */
 292 #define PIXIS_VSYSCLK1          0x1B    /* VELA SYSCLK1 Register */
 293 #define PIXIS_VSYSCLK2          0x1C    /* VELA SYSCLK2 Register */
 294 #define PIXIS_VDDRCLK0          0x1D    /* VELA DDRCLK0 Register */
 295 #define PIXIS_VDDRCLK1          0x1E    /* VELA DDRCLK1 Register */
 296 #define PIXIS_VDDRCLK2          0x1F    /* VELA DDRCLK2 Register */
 297 #define PIXIS_VWATCH            0x24    /* Watchdog Register */
 298 #define PIXIS_LED               0x25    /* LED Register */
 299
 300 #define PIXIS_SPD_SYSCLK        0x7     /* SYSCLK option */
 301
 302 /* old pixis referenced names */
 303 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 304 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 305 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x4e
 306
 307 #define CONFIG_SYS_INIT_RAM_LOCK        1
 308 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 309 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000      /* Size of used area in RAM */
 310
 311 #define CONFIG_SYS_GBL_DATA_OFFSET \
 312                 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 313 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 314
 315 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024) /* Reserve 256 kB for Mon */
 316 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)   /* Reserved for malloc */
 317
 318 #ifndef CONFIG_NAND_SPL
 319 #define CONFIG_SYS_NAND_BASE            0xffa00000
 320 #ifdef CONFIG_PHYS_64BIT
 321 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 322 #else
 323 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 324 #endif
 325 #else
 326 #define CONFIG_SYS_NAND_BASE            0xfff00000
 327 #ifdef CONFIG_PHYS_64BIT
 328 #define CONFIG_SYS_NAND_BASE_PHYS       0xffff00000ull
 329 #else
 330 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 331 #endif
 332 #endif
 333 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
 334                                 CONFIG_SYS_NAND_BASE + 0x40000, \
 335                                 CONFIG_SYS_NAND_BASE + 0x80000, \
 336                                 CONFIG_SYS_NAND_BASE + 0xC0000}
 337 #define CONFIG_SYS_MAX_NAND_DEVICE      4
 338 #define CONFIG_MTD_NAND_VERIFY_WRITE
 339 #define CONFIG_CMD_NAND         1
 340 #define CONFIG_NAND_FSL_ELBC    1
 341 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 342
 343 /* NAND boot: 4K NAND loader config */
 344 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 345 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) - 0x2000)
 346 #define CONFIG_SYS_NAND_U_BOOT_DST      (CONFIG_SYS_INIT_L2_ADDR)
 347 #define CONFIG_SYS_NAND_U_BOOT_START \
 348                 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 349 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 350 #define CONFIG_SYS_NAND_U_BOOT_RELOC    (CONFIG_SYS_INIT_L2_END - 0x2000)
 351 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 352
 353 /* NAND flash config */
 354 #define CONFIG_SYS_NAND_BR_PRELIM \
 355                 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 356                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 357                 | BR_PS_8               /* Port Size = 8 bit */ \
 358                 | BR_MS_FCM             /* MSEL = FCM */ \
 359                 | BR_V)                 /* valid */
 360 #define CONFIG_SYS_NAND_OR_PRELIM       (0xFFFC0000     /* length 256K */ \
 361                 | OR_FCM_PGS            /* Large Page*/ \
 362                 | OR_FCM_CSCT \
 363                 | OR_FCM_CST \
 364                 | OR_FCM_CHT \
 365                 | OR_FCM_SCY_1 \
 366                 | OR_FCM_TRLX \
 367                 | OR_FCM_EHTR)
 368
 369 #ifdef CONFIG_RAMBOOT_NAND
 370 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 371 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 372 #define CONFIG_SYS_BR2_PRELIM  CONFIG_FLASH_BR_PRELIM   /* NOR Base Address */
 373 #define CONFIG_SYS_OR2_PRELIM  CONFIG_FLASH_OR_PRELIM   /* NOR Options */
 374 #else
 375 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM   /* NOR Base Address */
 376 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM   /* NOR Options */
 377 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 378 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 379 #endif
 380
 381 #define CONFIG_SYS_BR4_PRELIM \
 382                 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
 383                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 384                 | BR_PS_8               /* Port Size = 8 bit */ \
 385                 | BR_MS_FCM             /* MSEL = FCM */ \
 386                 | BR_V)                 /* valid */
 387 #define CONFIG_SYS_OR4_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 388 #define CONFIG_SYS_BR5_PRELIM \
 389                 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \
 390                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 391                 | BR_PS_8               /* Port Size = 8 bit */ \
 392                 | BR_MS_FCM             /* MSEL = FCM */ \
 393                 | BR_V)                 /* valid */
 394 #define CONFIG_SYS_OR5_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 395
 396 #define CONFIG_SYS_BR6_PRELIM \
 397                 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \
 398                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 399                 | BR_PS_8               /* Port Size = 8 bit */ \
 400                 | BR_MS_FCM             /* MSEL = FCM */ \
 401                 | BR_V)                 /* valid */
 402 #define CONFIG_SYS_OR6_PRELIM   CONFIG_SYS_NAND_OR_PRELIM       /* NAND Options */
 403
 404 /* Serial Port - controlled on board with jumper J8
 405  * open - index 2
 406  * shorted - index 1
 407  */
 408 #define CONFIG_CONS_INDEX       1
 409 #define CONFIG_SYS_NS16550
 410 #define CONFIG_SYS_NS16550_SERIAL
 411 #define CONFIG_SYS_NS16550_REG_SIZE     1
 412 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 413 #ifdef CONFIG_NAND_SPL
 414 #define CONFIG_NS16550_MIN_FUNCTIONS
 415 #endif
 416
 417 #define CONFIG_SYS_BAUDRATE_TABLE       \
 418         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 419
 420 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
 421 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
 422
 423 /* Use the HUSH parser */
 424 #define CONFIG_SYS_HUSH_PARSER
 425 #ifdef  CONFIG_SYS_HUSH_PARSER
 426 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 427 #endif
 428
 429 /*
 430  * Pass open firmware flat tree
 431  */
 432 #define CONFIG_OF_LIBFDT                1
 433 #define CONFIG_OF_BOARD_SETUP           1
 434 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 435
 436 /*
 437  * I2C
 438  */
 439 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 440 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 441 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 442 #define CONFIG_I2C_MULTI_BUS
 443 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 444 #define CONFIG_SYS_I2C_SLAVE            0x7F
 445 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}     /* Don't probe these addrs */
 446 #define CONFIG_SYS_I2C_OFFSET           0x3000
 447 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 448
 449 /*
 450  * I2C2 EEPROM
 451  */
 452 #define CONFIG_ID_EEPROM
 453 #ifdef CONFIG_ID_EEPROM
 454 #define CONFIG_SYS_I2C_EEPROM_NXID
 455 #endif
 456 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 457 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 458 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 459
 460 /*
 461  * General PCI
 462  * Memory space is mapped 1-1, but I/O space must start from 0.
 463  */
 464
 465 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 466 #ifdef CONFIG_PHYS_64BIT
 467 #define CONFIG_SYS_PCI1_MEM_BUS         0xf0000000
 468 #define CONFIG_SYS_PCI1_MEM_PHYS        0xc00000000ull
 469 #else
 470 #define CONFIG_SYS_PCI1_MEM_BUS         0x80000000
 471 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 472 #endif
 473 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 474 #define CONFIG_SYS_PCI1_IO_VIRT         0xffc00000
 475 #define CONFIG_SYS_PCI1_IO_BUS          0x00000000
 476 #ifdef CONFIG_PHYS_64BIT
 477 #define CONFIG_SYS_PCI1_IO_PHYS         0xfffc00000ull
 478 #else
 479 #define CONFIG_SYS_PCI1_IO_PHYS         0xffc00000
 480 #endif
 481 #define CONFIG_SYS_PCI1_IO_SIZE         0x00010000      /* 64k */
 482
 483 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 484 #define CONFIG_SYS_PCIE1_NAME           "Slot 1"
 485 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x90000000
 486 #ifdef CONFIG_PHYS_64BIT
 487 #define CONFIG_SYS_PCIE1_MEM_BUS        0xf8000000
 488 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc10000000ull
 489 #else
 490 #define CONFIG_SYS_PCIE1_MEM_BUS        0x90000000
 491 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x90000000
 492 #endif
 493 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x08000000      /* 128M */
 494 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc10000
 495 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 496 #ifdef CONFIG_PHYS_64BIT
 497 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc10000ull
 498 #else
 499 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc10000
 500 #endif
 501 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 502
 503 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 504 #define CONFIG_SYS_PCIE2_NAME           "Slot 2"
 505 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x98000000
 506 #ifdef CONFIG_PHYS_64BIT
 507 #define CONFIG_SYS_PCIE2_MEM_BUS        0xf8000000
 508 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc18000000ull
 509 #else
 510 #define CONFIG_SYS_PCIE2_MEM_BUS        0x98000000
 511 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x98000000
 512 #endif
 513 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x08000000      /* 128M */
 514 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc20000
 515 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 516 #ifdef CONFIG_PHYS_64BIT
 517 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc20000ull
 518 #else
 519 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc20000
 520 #endif
 521 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 522
 523 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
 524 #define CONFIG_SYS_PCIE3_NAME           "Slot 3"
 525 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 526 #ifdef CONFIG_PHYS_64BIT
 527 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 528 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 529 #else
 530 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 531 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 532 #endif
 533 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 534 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc30000
 535 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 536 #ifdef CONFIG_PHYS_64BIT
 537 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc30000ull
 538 #else
 539 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc30000
 540 #endif
 541 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 542
 543 #if defined(CONFIG_PCI)
 544
 545 #define CONFIG_NET_MULTI
 546 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 547
 548 /*PCIE video card used*/
 549 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE3_IO_VIRT
 550
 551 /*PCI video card used*/
 552 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCI1_IO_VIRT*/
 553
 554 /* video */
 555 #define CONFIG_VIDEO
 556
 557 #if defined(CONFIG_VIDEO)
 558 #define CONFIG_BIOSEMU
 559 #define CONFIG_CFB_CONSOLE
 560 #define CONFIG_VIDEO_SW_CURSOR
 561 #define CONFIG_VGA_AS_SINGLE_DEVICE
 562 #define CONFIG_ATI_RADEON_FB
 563 #define CONFIG_VIDEO_LOGO
 564 /*#define CONFIG_CONSOLE_CURSOR*/
 565 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
 566 #endif
 567
 568 #undef CONFIG_EEPRO100
 569 #undef CONFIG_TULIP
 570 #undef CONFIG_RTL8139
 571
 572 #ifndef CONFIG_PCI_PNP
 573         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BUS
 574         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BUS
 575         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 576 #endif
 577
 578 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 579
 580 #endif  /* CONFIG_PCI */
 581
 582 /* SATA */
 583 #define CONFIG_LIBATA
 584 #define CONFIG_FSL_SATA
 585
 586 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 587 #define CONFIG_SATA1
 588 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 589 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 590 #define CONFIG_SATA2
 591 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 592 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 593
 594 #ifdef CONFIG_FSL_SATA
 595 #define CONFIG_LBA48
 596 #define CONFIG_CMD_SATA
 597 #define CONFIG_DOS_PARTITION
 598 #define CONFIG_CMD_EXT2
 599 #endif
 600
 601 #if defined(CONFIG_TSEC_ENET)
 602
 603 #ifndef CONFIG_NET_MULTI
 604 #define CONFIG_NET_MULTI        1
 605 #endif
 606
 607 #define CONFIG_MII              1       /* MII PHY management */
 608 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 609 #define CONFIG_TSEC1    1
 610 #define CONFIG_TSEC1_NAME       "eTSEC1"
 611 #define CONFIG_TSEC3    1
 612 #define CONFIG_TSEC3_NAME       "eTSEC3"
 613
 614 #define CONFIG_FSL_SGMII_RISER  1
 615 #define SGMII_RISER_PHY_OFFSET  0x1c
 616
 617 #define TSEC1_PHY_ADDR          1       /* TSEC1 -> PHY1 */
 618 #define TSEC3_PHY_ADDR          0       /* TSEC3 -> PHY0 */
 619
 620 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 621 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 622
 623 #define TSEC1_PHYIDX            0
 624 #define TSEC3_PHYIDX            0
 625
 626 #define CONFIG_ETHPRIME         "eTSEC1"
 627
 628 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 629
 630 #endif  /* CONFIG_TSEC_ENET */
 631
 632 /*
 633  * Environment
 634  */
 635
 636 #if defined(CONFIG_SYS_RAMBOOT)
 637 #if defined(CONFIG_RAMBOOT_NAND)
 638         #define CONFIG_ENV_IS_IN_NAND   1
 639         #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 640         #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 641 #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
 642         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 643         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 644         #define CONFIG_ENV_SIZE         0x2000
 645 #endif
 646 #else
 647         #define CONFIG_ENV_IS_IN_FLASH  1
 648         #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 649         #define CONFIG_ENV_ADDR         0xfff80000
 650         #else
 651         #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 652         #endif
 653         #define CONFIG_ENV_SIZE         0x2000
 654         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 655 #endif
 656
 657 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 658 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 659
 660 /*
 661  * Command line configuration.
 662  */
 663 #include <config_cmd_default.h>
 664
 665 #define CONFIG_CMD_IRQ
 666 #define CONFIG_CMD_PING
 667 #define CONFIG_CMD_I2C
 668 #define CONFIG_CMD_MII
 669 #define CONFIG_CMD_ELF
 670 #define CONFIG_CMD_IRQ
 671 #define CONFIG_CMD_SETEXPR
 672 #define CONFIG_CMD_REGINFO
 673
 674 #if defined(CONFIG_PCI)
 675 #define CONFIG_CMD_PCI
 676 #define CONFIG_CMD_NET
 677 #endif
 678
 679 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 680
 681 #define CONFIG_MMC     1
 682
 683 #ifdef CONFIG_MMC
 684 #define CONFIG_FSL_ESDHC
 685 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 686 #define CONFIG_CMD_MMC
 687 #define CONFIG_GENERIC_MMC
 688 #define CONFIG_CMD_EXT2
 689 #define CONFIG_CMD_FAT
 690 #define CONFIG_DOS_PARTITION
 691 #endif
 692
 693 /*
 694  * Miscellaneous configurable options
 695  */
 696 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 697 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 698 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 699 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 700 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 701 #if defined(CONFIG_CMD_KGDB)
 702 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 703 #else
 704 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 705 #endif
 706 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE \
 707                 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
 708 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 709 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
 710 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 711
 712 /*
 713  * For booting Linux, the board info and command line data
 714  * have to be in the first 64 MB of memory, since this is
 715  * the maximum mapped by the Linux kernel during initialization.
 716  */
 717 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 718 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 719
 720 #if defined(CONFIG_CMD_KGDB)
 721 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 722 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 723 #endif
 724
 725 /*
 726  * Environment Configuration
 727  */
 728
 729 /* The mac addresses for all ethernet interface */
 730 #if defined(CONFIG_TSEC_ENET)
 731 #define CONFIG_HAS_ETH0
 732 #define CONFIG_ETHADDR  00:E0:0C:02:00:FD
 733 #define CONFIG_HAS_ETH1
 734 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
 735 #define CONFIG_HAS_ETH2
 736 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
 737 #define CONFIG_HAS_ETH3
 738 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
 739 #endif
 740
 741 #define CONFIG_IPADDR           192.168.1.254
 742
 743 #define CONFIG_HOSTNAME         unknown
 744 #define CONFIG_ROOTPATH         /opt/nfsroot
 745 #define CONFIG_BOOTFILE         uImage
 746 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 747
 748 #define CONFIG_SERVERIP         192.168.1.1
 749 #define CONFIG_GATEWAYIP        192.168.1.1
 750 #define CONFIG_NETMASK          255.255.255.0
 751
 752 /* default location for tftp and bootm */
 753 #define CONFIG_LOADADDR         1000000
 754
 755 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 756 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 757
 758 #define CONFIG_BAUDRATE 115200
 759
 760 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 761  "netdev=eth0\0"                                                \
 762  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 763  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 764         "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "     \
 765         "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "           \
 766         "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "   \
 767         "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "              \
 768         "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"  \
 769  "consoledev=ttyS0\0"                           \
 770  "ramdiskaddr=2000000\0"                        \
 771  "ramdiskfile=8536ds/ramdisk.uboot\0"           \
 772  "fdtaddr=c00000\0"                             \
 773  "fdtfile=8536ds/mpc8536ds.dtb\0"               \
 774  "bdev=sda3\0"                                  \
 775  "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
 776
 777 #define CONFIG_HDBOOT                           \
 778  "setenv bootargs root=/dev/$bdev rw "          \
 779  "console=$consoledev,$baudrate $othbootargs;"  \
 780  "tftp $loadaddr $bootfile;"                    \
 781  "tftp $fdtaddr $fdtfile;"                      \
 782  "bootm $loadaddr - $fdtaddr"
 783
 784 #define CONFIG_NFSBOOTCOMMAND           \
 785  "setenv bootargs root=/dev/nfs rw "    \
 786  "nfsroot=$serverip:$rootpath "         \
 787  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 788  "console=$consoledev,$baudrate $othbootargs;"  \
 789  "tftp $loadaddr $bootfile;"            \
 790  "tftp $fdtaddr $fdtfile;"              \
 791  "bootm $loadaddr - $fdtaddr"
 792
 793 #define CONFIG_RAMBOOTCOMMAND           \
 794  "setenv bootargs root=/dev/ram rw "    \
 795  "console=$consoledev,$baudrate $othbootargs;"  \
 796  "tftp $ramdiskaddr $ramdiskfile;"      \
 797  "tftp $loadaddr $bootfile;"            \
 798  "tftp $fdtaddr $fdtfile;"              \
 799  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 800
 801 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 802
 803 #endif  /* __CONFIG_H */