include/configs/MPC8536DS.h

   1 /*
   2  * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8536ds board configuration file
   9  *
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #include "../board/freescale/common/ics307_clk.h"
  15
  16 #ifdef CONFIG_36BIT
  17 #define CONFIG_PHYS_64BIT       1
  18 #endif
  19
  20 #ifdef CONFIG_NAND
  21 #define CONFIG_NAND_U_BOOT              1
  22 #define CONFIG_RAMBOOT_NAND             1
  23 #ifdef CONFIG_NAND_SPL
  24 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  25 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  26 #else
  27 #define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
  28 #define CONFIG_SYS_TEXT_BASE    0xf8f82000
  29 #endif /* CONFIG_NAND_SPL */
  30 #endif
  31
  32 #ifdef CONFIG_SDCARD
  33 #define CONFIG_RAMBOOT_SDCARD           1
  34 #define CONFIG_SYS_TEXT_BASE    0xf8f40000
  35 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  36 #endif
  37
  38 #ifdef CONFIG_SPIFLASH
  39 #define CONFIG_RAMBOOT_SPIFLASH         1
  40 #define CONFIG_SYS_TEXT_BASE    0xf8f40000
  41 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  42 #endif
  43
  44 #ifndef CONFIG_SYS_TEXT_BASE
  45 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  46 #endif
  47
  48 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  49 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  50 #endif
  51
  52 #ifndef CONFIG_SYS_MONITOR_BASE
  53 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  54 #endif
  55
  56 /* High Level Configuration Options */
  57 #define CONFIG_BOOKE            1       /* BOOKE */
  58 #define CONFIG_E500             1       /* BOOKE e500 family */
  59 #define CONFIG_MPC8536          1
  60 #define CONFIG_MPC8536DS        1
  61
  62 #define CONFIG_FSL_ELBC         1       /* Has Enhanced localbus controller */
  63 #define CONFIG_SPI_FLASH        1       /* Has SPI Flash */
  64 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  65 #define CONFIG_PCI1             1       /* Enable PCI controller 1 */
  66 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  67 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  68 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  69 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  70 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  71 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  72 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  73
  74 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  75 #define CONFIG_E1000            1       /* Defind e1000 pci Ethernet card*/
  76
  77 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  78 #define CONFIG_ENV_OVERWRITE
  79
  80 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  81 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
  82 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
  83
  84 /*
  85  * These can be toggled for performance analysis, otherwise use default.
  86  */
  87 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  88 #define CONFIG_BTB                      /* toggle branch predition */
  89
  90 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  91
  92 #define CONFIG_ENABLE_36BIT_PHYS        1
  93
  94 #ifdef CONFIG_PHYS_64BIT
  95 #define CONFIG_ADDR_MAP                 1
  96 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  97 #endif
  98
  99 #define CONFIG_SYS_MEMTEST_START 0x00010000     /* skip exception vectors */
 100 #define CONFIG_SYS_MEMTEST_END   0x1f000000     /* skip u-boot at top of RAM */
 101 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 102
 103 /*
 104  * Config the L2 Cache as L2 SRAM
 105  */
 106 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 107 #ifdef CONFIG_PHYS_64BIT
 108 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8f80000ull
 109 #else
 110 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 111 #endif
 112 #define CONFIG_SYS_L2_SIZE              (512 << 10)
 113 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 114
 115 #define CONFIG_SYS_CCSRBAR              0xffe00000
 116 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 117
 118 #if defined(CONFIG_NAND_SPL)
 119 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 120 #endif
 121
 122 /* DDR Setup */
 123 #define CONFIG_VERY_BIG_RAM
 124 #define CONFIG_SYS_FSL_DDR2
 125 #undef CONFIG_FSL_DDR_INTERACTIVE
 126 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 127 #define CONFIG_DDR_SPD
 128
 129 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 130 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 131
 132 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 133 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 134
 135 #define CONFIG_NUM_DDR_CONTROLLERS      1
 136 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 137 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 138
 139 /* I2C addresses of SPD EEPROMs */
 140 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 141 #define CONFIG_SYS_SPD_BUS_NUM          1
 142
 143 /* These are used when DDR doesn't use SPD. */
 144 #define CONFIG_SYS_SDRAM_SIZE           256     /* DDR is 256MB */
 145 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
 146 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102 /* Enable, no interleaving */
 147 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 148 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 149 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
 150 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 151 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 152 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 153 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
 154 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 155 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 156 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 157 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 158 #define CONFIG_SYS_DDR_CONTROL  0xC3008000      /* Type = DDR2 */
 159 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
 160
 161 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 162 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 163 #define CONFIG_SYS_DDR_SBE              0x00010000
 164
 165 /* Make sure required options are set */
 166 #ifndef CONFIG_SPD_EEPROM
 167 #error ("CONFIG_SPD_EEPROM is required")
 168 #endif
 169
 170 #undef CONFIG_CLOCKS_IN_MHZ
 171
 172
 173 /*
 174  * Memory map -- xxx -this is wrong, needs updating
 175  *
 176  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 177  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 178  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 179  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 180  *
 181  * Localbus cacheable (TBD)
 182  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 183  *
 184  * Localbus non-cacheable
 185  * 0xe000_0000  0xe7ff_ffff     Promjet/free            128M non-cacheable
 186  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 187  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 188  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 189  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 190  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 191  */
 192
 193 /*
 194  * Local Bus Definitions
 195  */
 196 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* start of FLASH 128M */
 197 #ifdef CONFIG_PHYS_64BIT
 198 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 199 #else
 200 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 201 #endif
 202
 203 #define CONFIG_FLASH_BR_PRELIM \
 204         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
 205 #define CONFIG_FLASH_OR_PRELIM  0xf8000ff7
 206
 207 #define CONFIG_SYS_BR1_PRELIM \
 208                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 209                  | BR_PS_16 | BR_V)
 210 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 211
 212 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
 213                                       CONFIG_SYS_FLASH_BASE_PHYS }
 214 #define CONFIG_SYS_FLASH_QUIET_TEST
 215 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 216
 217 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 218 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 219 #undef  CONFIG_SYS_FLASH_CHECKSUM
 220 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 221 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 222
 223 #if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
 224     defined(CONFIG_RAMBOOT_SPIFLASH)
 225 #define CONFIG_SYS_RAMBOOT
 226 #define CONFIG_SYS_EXTRA_ENV_RELOC
 227 #else
 228 #undef CONFIG_SYS_RAMBOOT
 229 #endif
 230
 231 #define CONFIG_FLASH_CFI_DRIVER
 232 #define CONFIG_SYS_FLASH_CFI
 233 #define CONFIG_SYS_FLASH_EMPTY_INFO
 234 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 235
 236 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 237
 238 #define CONFIG_HWCONFIG                 /* enable hwconfig */
 239 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 240 #define PIXIS_BASE      0xffdf0000      /* PIXIS registers */
 241 #ifdef CONFIG_PHYS_64BIT
 242 #define PIXIS_BASE_PHYS 0xfffdf0000ull
 243 #else
 244 #define PIXIS_BASE_PHYS PIXIS_BASE
 245 #endif
 246
 247 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 248 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 249
 250 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 251 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 252 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 253 #define PIXIS_CSR               0x3     /* PIXIS General control/status register */
 254 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 255 #define PIXIS_PWR               0x5     /* PIXIS Power status register */
 256 #define PIXIS_AUX               0x6     /* Auxiliary 1 register */
 257 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 258 #define PIXIS_AUX2              0x8     /* Auxiliary 2 register */
 259 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 260 #define PIXIS_VSTAT             0x11    /* VELA Status Register */
 261 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 262 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 263 #define PIXIS_VCORE0            0x14    /* VELA VCORE0 Register */
 264 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 265 #define PIXIS_VBOOT_LBMAP       0xe0    /* VBOOT - CFG_LBMAP */
 266 #define PIXIS_VBOOT_LBMAP_NOR0  0x00    /* cfg_lbmap - boot from NOR 0 */
 267 #define PIXIS_VBOOT_LBMAP_NOR1  0x01    /* cfg_lbmap - boot from NOR 1 */
 268 #define PIXIS_VBOOT_LBMAP_NOR2  0x02    /* cfg_lbmap - boot from NOR 2 */
 269 #define PIXIS_VBOOT_LBMAP_NOR3  0x03    /* cfg_lbmap - boot from NOR 3 */
 270 #define PIXIS_VBOOT_LBMAP_PJET  0x04    /* cfg_lbmap - boot from projet */
 271 #define PIXIS_VBOOT_LBMAP_NAND  0x05    /* cfg_lbmap - boot from NAND */
 272 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 273 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 274 #define PIXIS_VSPEED2           0x19    /* VELA VSpeed 2 */
 275 #define PIXIS_VSYSCLK0          0x1A    /* VELA SYSCLK0 Register */
 276 #define PIXIS_VSYSCLK1          0x1B    /* VELA SYSCLK1 Register */
 277 #define PIXIS_VSYSCLK2          0x1C    /* VELA SYSCLK2 Register */
 278 #define PIXIS_VDDRCLK0          0x1D    /* VELA DDRCLK0 Register */
 279 #define PIXIS_VDDRCLK1          0x1E    /* VELA DDRCLK1 Register */
 280 #define PIXIS_VDDRCLK2          0x1F    /* VELA DDRCLK2 Register */
 281 #define PIXIS_VWATCH            0x24    /* Watchdog Register */
 282 #define PIXIS_LED               0x25    /* LED Register */
 283
 284 #define PIXIS_SPD_SYSCLK        0x7     /* SYSCLK option */
 285
 286 /* old pixis referenced names */
 287 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 288 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 289 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x4e
 290
 291 #define CONFIG_SYS_INIT_RAM_LOCK        1
 292 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 293 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000      /* Size of used area in RAM */
 294
 295 #define CONFIG_SYS_GBL_DATA_OFFSET \
 296                 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 297 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 298
 299 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024) /* Reserve 256 kB for Mon */
 300 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)   /* Reserved for malloc */
 301
 302 #ifndef CONFIG_NAND_SPL
 303 #define CONFIG_SYS_NAND_BASE            0xffa00000
 304 #ifdef CONFIG_PHYS_64BIT
 305 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 306 #else
 307 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 308 #endif
 309 #else
 310 #define CONFIG_SYS_NAND_BASE            0xfff00000
 311 #ifdef CONFIG_PHYS_64BIT
 312 #define CONFIG_SYS_NAND_BASE_PHYS       0xffff00000ull
 313 #else
 314 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 315 #endif
 316 #endif
 317 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
 318                                 CONFIG_SYS_NAND_BASE + 0x40000, \
 319                                 CONFIG_SYS_NAND_BASE + 0x80000, \
 320                                 CONFIG_SYS_NAND_BASE + 0xC0000}
 321 #define CONFIG_SYS_MAX_NAND_DEVICE      4
 322 #define CONFIG_MTD_NAND_VERIFY_WRITE
 323 #define CONFIG_CMD_NAND         1
 324 #define CONFIG_NAND_FSL_ELBC    1
 325 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 326
 327 /* NAND boot: 4K NAND loader config */
 328 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 329 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
 330 #define CONFIG_SYS_NAND_U_BOOT_DST      (CONFIG_SYS_INIT_L2_ADDR)
 331 #define CONFIG_SYS_NAND_U_BOOT_START \
 332                 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 333 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 334 #define CONFIG_SYS_NAND_U_BOOT_RELOC    (CONFIG_SYS_INIT_L2_END - 0x2000)
 335 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 336
 337 /* NAND flash config */
 338 #define CONFIG_SYS_NAND_BR_PRELIM \
 339                 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 340                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 341                 | BR_PS_8               /* Port Size = 8 bit */ \
 342                 | BR_MS_FCM             /* MSEL = FCM */ \
 343                 | BR_V)                 /* valid */
 344 #define CONFIG_SYS_NAND_OR_PRELIM       (0xFFFC0000     /* length 256K */ \
 345                 | OR_FCM_PGS            /* Large Page*/ \
 346                 | OR_FCM_CSCT \
 347                 | OR_FCM_CST \
 348                 | OR_FCM_CHT \
 349                 | OR_FCM_SCY_1 \
 350                 | OR_FCM_TRLX \
 351                 | OR_FCM_EHTR)
 352
 353 #ifdef CONFIG_RAMBOOT_NAND
 354 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 355 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 356 #define CONFIG_SYS_BR2_PRELIM  CONFIG_FLASH_BR_PRELIM   /* NOR Base Address */
 357 #define CONFIG_SYS_OR2_PRELIM  CONFIG_FLASH_OR_PRELIM   /* NOR Options */
 358 #else
 359 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM   /* NOR Base Address */
 360 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM   /* NOR Options */
 361 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 362 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 363 #endif
 364
 365 #define CONFIG_SYS_BR4_PRELIM \
 366                 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
 367                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 368                 | BR_PS_8               /* Port Size = 8 bit */ \
 369                 | BR_MS_FCM             /* MSEL = FCM */ \
 370                 | BR_V)                 /* valid */
 371 #define CONFIG_SYS_OR4_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 372 #define CONFIG_SYS_BR5_PRELIM \
 373                 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
 374                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 375                 | BR_PS_8               /* Port Size = 8 bit */ \
 376                 | BR_MS_FCM             /* MSEL = FCM */ \
 377                 | BR_V)                 /* valid */
 378 #define CONFIG_SYS_OR5_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 379
 380 #define CONFIG_SYS_BR6_PRELIM \
 381                 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
 382                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 383                 | BR_PS_8               /* Port Size = 8 bit */ \
 384                 | BR_MS_FCM             /* MSEL = FCM */ \
 385                 | BR_V)                 /* valid */
 386 #define CONFIG_SYS_OR6_PRELIM   CONFIG_SYS_NAND_OR_PRELIM       /* NAND Options */
 387
 388 /* Serial Port - controlled on board with jumper J8
 389  * open - index 2
 390  * shorted - index 1
 391  */
 392 #define CONFIG_CONS_INDEX       1
 393 #define CONFIG_SYS_NS16550
 394 #define CONFIG_SYS_NS16550_SERIAL
 395 #define CONFIG_SYS_NS16550_REG_SIZE     1
 396 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 397 #ifdef CONFIG_NAND_SPL
 398 #define CONFIG_NS16550_MIN_FUNCTIONS
 399 #endif
 400
 401 #define CONFIG_SYS_BAUDRATE_TABLE       \
 402         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 403
 404 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
 405 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
 406
 407 /* Use the HUSH parser */
 408 #define CONFIG_SYS_HUSH_PARSER
 409
 410 /*
 411  * Pass open firmware flat tree
 412  */
 413 #define CONFIG_OF_LIBFDT                1
 414 #define CONFIG_OF_BOARD_SETUP           1
 415 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 416
 417 /*
 418  * I2C
 419  */
 420 #define CONFIG_SYS_I2C
 421 #define CONFIG_SYS_I2C_FSL
 422 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 423 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 424 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 425 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 426 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 427 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 428 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x29} }
 429
 430 /*
 431  * I2C2 EEPROM
 432  */
 433 #define CONFIG_ID_EEPROM
 434 #ifdef CONFIG_ID_EEPROM
 435 #define CONFIG_SYS_I2C_EEPROM_NXID
 436 #endif
 437 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 438 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 439 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 440
 441 /*
 442  * eSPI - Enhanced SPI
 443  */
 444 #define CONFIG_HARD_SPI
 445 #define CONFIG_FSL_ESPI
 446
 447 #if defined(CONFIG_SPI_FLASH)
 448 #define CONFIG_SPI_FLASH_SPANSION
 449 #define CONFIG_CMD_SF
 450 #define CONFIG_SF_DEFAULT_SPEED 10000000
 451 #define CONFIG_SF_DEFAULT_MODE  0
 452 #endif
 453
 454 /*
 455  * General PCI
 456  * Memory space is mapped 1-1, but I/O space must start from 0.
 457  */
 458
 459 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 460 #ifdef CONFIG_PHYS_64BIT
 461 #define CONFIG_SYS_PCI1_MEM_BUS         0xf0000000
 462 #define CONFIG_SYS_PCI1_MEM_PHYS        0xc00000000ull
 463 #else
 464 #define CONFIG_SYS_PCI1_MEM_BUS         0x80000000
 465 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 466 #endif
 467 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 468 #define CONFIG_SYS_PCI1_IO_VIRT         0xffc00000
 469 #define CONFIG_SYS_PCI1_IO_BUS          0x00000000
 470 #ifdef CONFIG_PHYS_64BIT
 471 #define CONFIG_SYS_PCI1_IO_PHYS         0xfffc00000ull
 472 #else
 473 #define CONFIG_SYS_PCI1_IO_PHYS         0xffc00000
 474 #endif
 475 #define CONFIG_SYS_PCI1_IO_SIZE         0x00010000      /* 64k */
 476
 477 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 478 #define CONFIG_SYS_PCIE1_NAME           "Slot 1"
 479 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x90000000
 480 #ifdef CONFIG_PHYS_64BIT
 481 #define CONFIG_SYS_PCIE1_MEM_BUS        0xf8000000
 482 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc10000000ull
 483 #else
 484 #define CONFIG_SYS_PCIE1_MEM_BUS        0x90000000
 485 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x90000000
 486 #endif
 487 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x08000000      /* 128M */
 488 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc10000
 489 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 490 #ifdef CONFIG_PHYS_64BIT
 491 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc10000ull
 492 #else
 493 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc10000
 494 #endif
 495 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 496
 497 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 498 #define CONFIG_SYS_PCIE2_NAME           "Slot 2"
 499 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x98000000
 500 #ifdef CONFIG_PHYS_64BIT
 501 #define CONFIG_SYS_PCIE2_MEM_BUS        0xf8000000
 502 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc18000000ull
 503 #else
 504 #define CONFIG_SYS_PCIE2_MEM_BUS        0x98000000
 505 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x98000000
 506 #endif
 507 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x08000000      /* 128M */
 508 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc20000
 509 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 510 #ifdef CONFIG_PHYS_64BIT
 511 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc20000ull
 512 #else
 513 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc20000
 514 #endif
 515 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 516
 517 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
 518 #define CONFIG_SYS_PCIE3_NAME           "Slot 3"
 519 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 520 #ifdef CONFIG_PHYS_64BIT
 521 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 522 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 523 #else
 524 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 525 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 526 #endif
 527 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 528 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc30000
 529 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 530 #ifdef CONFIG_PHYS_64BIT
 531 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc30000ull
 532 #else
 533 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc30000
 534 #endif
 535 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 536
 537 #if defined(CONFIG_PCI)
 538
 539 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 540
 541 /*PCIE video card used*/
 542 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE3_IO_VIRT
 543
 544 /*PCI video card used*/
 545 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCI1_IO_VIRT*/
 546
 547 /* video */
 548 #define CONFIG_VIDEO
 549
 550 #if defined(CONFIG_VIDEO)
 551 #define CONFIG_BIOSEMU
 552 #define CONFIG_CFB_CONSOLE
 553 #define CONFIG_VIDEO_SW_CURSOR
 554 #define CONFIG_VGA_AS_SINGLE_DEVICE
 555 #define CONFIG_ATI_RADEON_FB
 556 #define CONFIG_VIDEO_LOGO
 557 /*#define CONFIG_CONSOLE_CURSOR*/
 558 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
 559 #endif
 560
 561 #undef CONFIG_EEPRO100
 562 #undef CONFIG_TULIP
 563 #undef CONFIG_RTL8139
 564
 565 #ifndef CONFIG_PCI_PNP
 566         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BUS
 567         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BUS
 568         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 569 #endif
 570
 571 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 572
 573 #endif  /* CONFIG_PCI */
 574
 575 /* SATA */
 576 #define CONFIG_LIBATA
 577 #define CONFIG_FSL_SATA
 578
 579 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 580 #define CONFIG_SATA1
 581 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 582 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 583 #define CONFIG_SATA2
 584 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 585 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 586
 587 #ifdef CONFIG_FSL_SATA
 588 #define CONFIG_LBA48
 589 #define CONFIG_CMD_SATA
 590 #define CONFIG_DOS_PARTITION
 591 #define CONFIG_CMD_EXT2
 592 #endif
 593
 594 #if defined(CONFIG_TSEC_ENET)
 595
 596 #define CONFIG_MII              1       /* MII PHY management */
 597 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 598 #define CONFIG_TSEC1    1
 599 #define CONFIG_TSEC1_NAME       "eTSEC1"
 600 #define CONFIG_TSEC3    1
 601 #define CONFIG_TSEC3_NAME       "eTSEC3"
 602
 603 #define CONFIG_FSL_SGMII_RISER  1
 604 #define SGMII_RISER_PHY_OFFSET  0x1c
 605
 606 #define TSEC1_PHY_ADDR          1       /* TSEC1 -> PHY1 */
 607 #define TSEC3_PHY_ADDR          0       /* TSEC3 -> PHY0 */
 608
 609 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 610 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 611
 612 #define TSEC1_PHYIDX            0
 613 #define TSEC3_PHYIDX            0
 614
 615 #define CONFIG_ETHPRIME         "eTSEC1"
 616
 617 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 618
 619 #endif  /* CONFIG_TSEC_ENET */
 620
 621 /*
 622  * Environment
 623  */
 624
 625 #if defined(CONFIG_SYS_RAMBOOT)
 626 #if defined(CONFIG_RAMBOOT_NAND)
 627 #define CONFIG_ENV_IS_IN_NAND   1
 628 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 629 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 630 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
 631 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
 632 #define CONFIG_ENV_IS_IN_SPI_FLASH
 633 #define CONFIG_ENV_SPI_BUS      0
 634 #define CONFIG_ENV_SPI_CS       0
 635 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 636 #define CONFIG_ENV_SPI_MODE     0
 637 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
 638 #define CONFIG_ENV_OFFSET       0xF0000
 639 #define CONFIG_ENV_SECT_SIZE    0x10000
 640 #elif defined(CONFIG_RAMBOOT_SDCARD)
 641 #define CONFIG_ENV_IS_IN_MMC
 642 #define CONFIG_FSL_FIXED_MMC_LOCATION
 643 #define CONFIG_ENV_SIZE         0x2000
 644 #define CONFIG_SYS_MMC_ENV_DEV  0
 645 #else
 646         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 647         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 648         #define CONFIG_ENV_SIZE         0x2000
 649 #endif
 650 #else
 651         #define CONFIG_ENV_IS_IN_FLASH  1
 652         #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 653         #define CONFIG_ENV_SIZE         0x2000
 654         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 655 #endif
 656
 657 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 658 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 659
 660 /*
 661  * Command line configuration.
 662  */
 663 #include <config_cmd_default.h>
 664
 665 #define CONFIG_CMD_IRQ
 666 #define CONFIG_CMD_PING
 667 #define CONFIG_CMD_I2C
 668 #define CONFIG_CMD_MII
 669 #define CONFIG_CMD_ELF
 670 #define CONFIG_CMD_IRQ
 671 #define CONFIG_CMD_SETEXPR
 672 #define CONFIG_CMD_REGINFO
 673
 674 #if defined(CONFIG_PCI)
 675 #define CONFIG_CMD_PCI
 676 #define CONFIG_CMD_NET
 677 #endif
 678
 679 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 680
 681 #define CONFIG_MMC     1
 682
 683 #ifdef CONFIG_MMC
 684 #define CONFIG_FSL_ESDHC
 685 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 686 #define CONFIG_CMD_MMC
 687 #define CONFIG_GENERIC_MMC
 688 #endif
 689
 690 /*
 691  * USB
 692  */
 693 #define CONFIG_HAS_FSL_MPH_USB
 694 #ifdef CONFIG_HAS_FSL_MPH_USB
 695 #define CONFIG_USB_EHCI
 696
 697 #ifdef CONFIG_USB_EHCI
 698 #define CONFIG_CMD_USB
 699 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 700 #define CONFIG_USB_EHCI_FSL
 701 #define CONFIG_USB_STORAGE
 702 #endif
 703 #endif
 704
 705 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 706 #define CONFIG_CMD_EXT2
 707 #define CONFIG_CMD_FAT
 708 #define CONFIG_DOS_PARTITION
 709 #endif
 710
 711 /*
 712  * Miscellaneous configurable options
 713  */
 714 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 715 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 716 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 717 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 718 #if defined(CONFIG_CMD_KGDB)
 719 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 720 #else
 721 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 722 #endif
 723 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE \
 724                 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
 725 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 726 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
 727
 728 /*
 729  * For booting Linux, the board info and command line data
 730  * have to be in the first 64 MB of memory, since this is
 731  * the maximum mapped by the Linux kernel during initialization.
 732  */
 733 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 734 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 735
 736 #if defined(CONFIG_CMD_KGDB)
 737 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 738 #endif
 739
 740 /*
 741  * Environment Configuration
 742  */
 743
 744 /* The mac addresses for all ethernet interface */
 745 #if defined(CONFIG_TSEC_ENET)
 746 #define CONFIG_HAS_ETH0
 747 #define CONFIG_ETHADDR  00:E0:0C:02:00:FD
 748 #define CONFIG_HAS_ETH1
 749 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
 750 #define CONFIG_HAS_ETH2
 751 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
 752 #define CONFIG_HAS_ETH3
 753 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
 754 #endif
 755
 756 #define CONFIG_IPADDR           192.168.1.254
 757
 758 #define CONFIG_HOSTNAME         unknown
 759 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 760 #define CONFIG_BOOTFILE         "uImage"
 761 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 762
 763 #define CONFIG_SERVERIP         192.168.1.1
 764 #define CONFIG_GATEWAYIP        192.168.1.1
 765 #define CONFIG_NETMASK          255.255.255.0
 766
 767 /* default location for tftp and bootm */
 768 #define CONFIG_LOADADDR         1000000
 769
 770 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 771 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 772
 773 #define CONFIG_BAUDRATE 115200
 774
 775 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 776 "netdev=eth0\0"                                         \
 777 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 778 "tftpflash=tftpboot $loadaddr $uboot; "                 \
 779         "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 780                 " +$filesize; " \
 781         "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 782                 " +$filesize; " \
 783         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 784                 " $filesize; "  \
 785         "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 786                 " +$filesize; " \
 787         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 788                 " $filesize\0"  \
 789 "consoledev=ttyS0\0"                            \
 790 "ramdiskaddr=2000000\0"                 \
 791 "ramdiskfile=8536ds/ramdisk.uboot\0"            \
 792 "fdtaddr=c00000\0"                              \
 793 "fdtfile=8536ds/mpc8536ds.dtb\0"                \
 794 "bdev=sda3\0"                                   \
 795 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
 796
 797 #define CONFIG_HDBOOT                           \
 798  "setenv bootargs root=/dev/$bdev rw "          \
 799  "console=$consoledev,$baudrate $othbootargs;"  \
 800  "tftp $loadaddr $bootfile;"                    \
 801  "tftp $fdtaddr $fdtfile;"                      \
 802  "bootm $loadaddr - $fdtaddr"
 803
 804 #define CONFIG_NFSBOOTCOMMAND           \
 805  "setenv bootargs root=/dev/nfs rw "    \
 806  "nfsroot=$serverip:$rootpath "         \
 807  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 808  "console=$consoledev,$baudrate $othbootargs;"  \
 809  "tftp $loadaddr $bootfile;"            \
 810  "tftp $fdtaddr $fdtfile;"              \
 811  "bootm $loadaddr - $fdtaddr"
 812
 813 #define CONFIG_RAMBOOTCOMMAND           \
 814  "setenv bootargs root=/dev/ram rw "    \
 815  "console=$consoledev,$baudrate $othbootargs;"  \
 816  "tftp $ramdiskaddr $ramdiskfile;"      \
 817  "tftp $loadaddr $bootfile;"            \
 818  "tftp $fdtaddr $fdtfile;"              \
 819  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 820
 821 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 822
 823 #endif  /* __CONFIG_H */