include/configs/MPC8540ADS.h

   1 /*
   2  * Copyright 2004, 2011 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003 Motorola,Inc.
   4  * Xianghua Xiao <X.Xiao@motorola.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * mpc8540ads board configuration file
  11  *
  12  * Please refer to doc/README.mpc85xx for more info.
  13  *
  14  * Make sure you change the MAC address and other network params first,
  15  * search for CONFIG_SERVERIP, etc in this file.
  16  */
  17
  18 #ifndef __CONFIG_H
  19 #define __CONFIG_H
  20
  21 /*
  22  * default CCARBAR is at 0xff700000
  23  * assume U-Boot is less than 0.5MB
  24  */
  25 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  26
  27 #ifndef CONFIG_HAS_FEC
  28 #define CONFIG_HAS_FEC          1       /* 8540 has FEC */
  29 #endif
  30
  31 #define CONFIG_PCI_INDIRECT_BRIDGE
  32 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  33 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  34 #define CONFIG_ENV_OVERWRITE
  35
  36 /*
  37  * sysclk for MPC85xx
  38  *
  39  * Two valid values are:
  40  *    33000000
  41  *    66000000
  42  *
  43  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  44  * is likely the desired value here, so that is now the default.
  45  * The board, however, can run at 66MHz.  In any event, this value
  46  * must match the settings of some switches.  Details can be found
  47  * in the README.mpc85xxads.
  48  *
  49  * XXX -- Can't we run at 66 MHz, anyway?  PCI should drop to
  50  * 33MHz to accommodate, based on a PCI pin.
  51  * Note that PCI-X won't work at 33MHz.
  52  */
  53
  54 #ifndef CONFIG_SYS_CLK_FREQ
  55 #define CONFIG_SYS_CLK_FREQ     33000000
  56 #endif
  57
  58 /*
  59  * These can be toggled for performance analysis, otherwise use default.
  60  */
  61 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  62 #define CONFIG_BTB                      /* toggle branch predition */
  63
  64 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  65 #define CONFIG_SYS_MEMTEST_END          0x00400000
  66
  67 #define CONFIG_SYS_CCSRBAR              0xe0000000
  68 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  69
  70 /* DDR Setup */
  71 #define CONFIG_SYS_FSL_DDR1
  72 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  73 #define CONFIG_DDR_SPD
  74 #undef CONFIG_FSL_DDR_INTERACTIVE
  75
  76 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  77
  78 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  79 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  80
  81 #define CONFIG_NUM_DDR_CONTROLLERS      1
  82 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  83 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  84
  85 /* I2C addresses of SPD EEPROMs */
  86 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  87
  88 /* These are used when DDR doesn't use SPD. */
  89 #define CONFIG_SYS_SDRAM_SIZE   128             /* DDR is 128MB */
  90 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007      /* 0-128MB */
  91 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80000002
  92 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
  93 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
  94 #define CONFIG_SYS_DDR_CONTROL          0xc2000000      /* unbuffered,no DYN_PWR */
  95 #define CONFIG_SYS_DDR_MODE             0x00000062      /* DLL,normal,seq,4/2.5 */
  96 #define CONFIG_SYS_DDR_INTERVAL 0x05200100      /* autocharge,no open page */
  97
  98 /*
  99  * SDRAM on the Local Bus
 100  */
 101 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 102 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 103
 104 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 16M */
 105 #define CONFIG_SYS_BR0_PRELIM           0xff001801      /* port size 32bit */
 106
 107 #define CONFIG_SYS_OR0_PRELIM           0xff006ff7      /* 16MB Flash */
 108 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 109 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* sectors per device */
 110 #undef  CONFIG_SYS_FLASH_CHECKSUM
 111 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 112 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 113
 114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 115
 116 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 117 #define CONFIG_SYS_RAMBOOT
 118 #else
 119 #undef  CONFIG_SYS_RAMBOOT
 120 #endif
 121
 122 #define CONFIG_FLASH_CFI_DRIVER
 123 #define CONFIG_SYS_FLASH_CFI
 124 #define CONFIG_SYS_FLASH_EMPTY_INFO
 125
 126 #undef CONFIG_CLOCKS_IN_MHZ
 127
 128 /*
 129  * Local Bus Definitions
 130  */
 131
 132 /*
 133  * Base Register 2 and Option Register 2 configure SDRAM.
 134  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 135  *
 136  * For BR2, need:
 137  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 138  *    port-size = 32-bits = BR2[19:20] = 11
 139  *    no parity checking = BR2[21:22] = 00
 140  *    SDRAM for MSEL = BR2[24:26] = 011
 141  *    Valid = BR[31] = 1
 142  *
 143  * 0    4    8    12   16   20   24   28
 144  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 145  *
 146  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 147  * FIXME: the top 17 bits of BR2.
 148  */
 149
 150 #define CONFIG_SYS_BR2_PRELIM           0xf0001861
 151
 152 /*
 153  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 154  *
 155  * For OR2, need:
 156  *    64MB mask for AM, OR2[0:7] = 1111 1100
 157  *                 XAM, OR2[17:18] = 11
 158  *    9 columns OR2[19-21] = 010
 159  *    13 rows   OR2[23-25] = 100
 160  *    EAD set for extra time OR[31] = 1
 161  *
 162  * 0    4    8    12   16   20   24   28
 163  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 164  */
 165
 166 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 167
 168 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 169 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 170 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
 171 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer prescal*/
 172
 173 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_BSMA1516        \
 174                                 | LSDMR_RFCR5           \
 175                                 | LSDMR_PRETOACT3       \
 176                                 | LSDMR_ACTTORW3        \
 177                                 | LSDMR_BL8             \
 178                                 | LSDMR_WRC2            \
 179                                 | LSDMR_CL3             \
 180                                 | LSDMR_RFEN            \
 181                                 )
 182
 183 /*
 184  * SDRAM Controller configuration sequence.
 185  */
 186 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 187 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 188 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 189 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 190 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 191
 192 /*
 193  * 32KB, 8-bit wide for ADS config reg
 194  */
 195 #define CONFIG_SYS_BR4_PRELIM          0xf8000801
 196 #define CONFIG_SYS_OR4_PRELIM           0xffffe1f1
 197 #define CONFIG_SYS_BCSR         (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 198
 199 #define CONFIG_SYS_INIT_RAM_LOCK        1
 200 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 201 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 202
 203 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 204 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 205
 206 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 207 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 208
 209 /* Serial Port */
 210 #define CONFIG_CONS_INDEX     1
 211 #define CONFIG_SYS_NS16550_SERIAL
 212 #define CONFIG_SYS_NS16550_REG_SIZE    1
 213 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 214
 215 #define CONFIG_SYS_BAUDRATE_TABLE  \
 216         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 217
 218 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 219 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 220
 221 /*
 222  * I2C
 223  */
 224 #define CONFIG_SYS_I2C
 225 #define CONFIG_SYS_I2C_FSL
 226 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 227 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 228 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 229 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 230
 231 /* RapidIO MMU */
 232 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000      /* base address */
 233 #define CONFIG_SYS_RIO_MEM_BUS  0xc0000000      /* base address */
 234 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
 235 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 236
 237 /*
 238  * General PCI
 239  * Memory space is mapped 1-1, but I/O space must start from 0.
 240  */
 241 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 242 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 243 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 244 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 245 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 246 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 247 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 248 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000        /* 1M */
 249
 250 #if defined(CONFIG_PCI)
 251 #undef CONFIG_EEPRO100
 252 #undef CONFIG_TULIP
 253
 254 #if !defined(CONFIG_PCI_PNP)
 255     #define PCI_ENET0_IOADDR    0xe0000000
 256     #define PCI_ENET0_MEMADDR   0xe0000000
 257     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 258 #endif
 259
 260 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 261 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 262
 263 #endif  /* CONFIG_PCI */
 264
 265 #if defined(CONFIG_TSEC_ENET)
 266
 267 #define CONFIG_MII              1       /* MII PHY management */
 268 #define CONFIG_TSEC1    1
 269 #define CONFIG_TSEC1_NAME       "TSEC0"
 270 #define CONFIG_TSEC2    1
 271 #define CONFIG_TSEC2_NAME       "TSEC1"
 272 #define TSEC1_PHY_ADDR          0
 273 #define TSEC2_PHY_ADDR          1
 274 #define TSEC1_PHYIDX            0
 275 #define TSEC2_PHYIDX            0
 276 #define TSEC1_FLAGS             TSEC_GIGABIT
 277 #define TSEC2_FLAGS             TSEC_GIGABIT
 278
 279 #if CONFIG_HAS_FEC
 280 #define CONFIG_MPC85XX_FEC      1
 281 #define CONFIG_MPC85XX_FEC_NAME         "FEC"
 282 #define FEC_PHY_ADDR            3
 283 #define FEC_PHYIDX              0
 284 #define FEC_FLAGS               0
 285 #endif
 286
 287 /* Options are: TSEC[0-1], FEC */
 288 #define CONFIG_ETHPRIME         "TSEC0"
 289
 290 #endif  /* CONFIG_TSEC_ENET */
 291
 292 /*
 293  * Environment
 294  */
 295 #ifndef CONFIG_SYS_RAMBOOT
 296   #define CONFIG_ENV_IS_IN_FLASH        1
 297   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE + 0x40000)
 298   #define CONFIG_ENV_SECT_SIZE  0x40000 /* 256K(one sector) for env */
 299   #define CONFIG_ENV_SIZE               0x2000
 300 #else
 301   #define CONFIG_SYS_NO_FLASH           1       /* Flash is not usable now */
 302   #define CONFIG_ENV_IS_NOWHERE 1       /* Store ENV in memory only */
 303   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 304   #define CONFIG_ENV_SIZE               0x2000
 305 #endif
 306
 307 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 308 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 309
 310 /*
 311  * BOOTP options
 312  */
 313 #define CONFIG_BOOTP_BOOTFILESIZE
 314 #define CONFIG_BOOTP_BOOTPATH
 315 #define CONFIG_BOOTP_GATEWAY
 316 #define CONFIG_BOOTP_HOSTNAME
 317
 318 /*
 319  * Command line configuration.
 320  */
 321 #define CONFIG_CMD_IRQ
 322
 323 #if defined(CONFIG_PCI)
 324     #define CONFIG_CMD_PCI
 325 #endif
 326
 327 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 328
 329 /*
 330  * Miscellaneous configurable options
 331  */
 332 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 333 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 334 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 335 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 336
 337 #if defined(CONFIG_CMD_KGDB)
 338     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 339 #else
 340     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 341 #endif
 342
 343 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 344 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 345 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 346
 347 /*
 348  * For booting Linux, the board info and command line data
 349  * have to be in the first 64 MB of memory, since this is
 350  * the maximum mapped by the Linux kernel during initialization.
 351  */
 352 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 353 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 354
 355 #if defined(CONFIG_CMD_KGDB)
 356 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 357 #endif
 358
 359 /*
 360  * Environment Configuration
 361  */
 362
 363 /* The mac addresses for all ethernet interface */
 364 #if defined(CONFIG_TSEC_ENET)
 365 #define CONFIG_HAS_ETH0
 366 #define CONFIG_HAS_ETH1
 367 #define CONFIG_HAS_ETH2
 368 #endif
 369
 370 #define CONFIG_IPADDR    192.168.1.253
 371
 372 #define CONFIG_HOSTNAME         unknown
 373 #define CONFIG_ROOTPATH         "/nfsroot"
 374 #define CONFIG_BOOTFILE         "your.uImage"
 375
 376 #define CONFIG_SERVERIP  192.168.1.1
 377 #define CONFIG_GATEWAYIP 192.168.1.1
 378 #define CONFIG_NETMASK   255.255.255.0
 379
 380 #define CONFIG_LOADADDR  200000 /* default location for tftp and bootm */
 381
 382 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 383
 384 #define CONFIG_BAUDRATE 115200
 385
 386 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 387    "netdev=eth0\0"                                                      \
 388    "consoledev=ttyS0\0"                                                 \
 389    "ramdiskaddr=1000000\0"                                              \
 390    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 391    "fdtaddr=400000\0"                                                   \
 392    "fdtfile=your.fdt.dtb\0"
 393
 394 #define CONFIG_NFSBOOTCOMMAND                                           \
 395    "setenv bootargs root=/dev/nfs rw "                                  \
 396       "nfsroot=$serverip:$rootpath "                                    \
 397       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 398       "console=$consoledev,$baudrate $othbootargs;"                     \
 399    "tftp $loadaddr $bootfile;"                                          \
 400    "tftp $fdtaddr $fdtfile;"                                            \
 401    "bootm $loadaddr - $fdtaddr"
 402
 403 #define CONFIG_RAMBOOTCOMMAND \
 404    "setenv bootargs root=/dev/ram rw "                                  \
 405       "console=$consoledev,$baudrate $othbootargs;"                     \
 406    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 407    "tftp $loadaddr $bootfile;"                                          \
 408    "tftp $fdtaddr $fdtfile;"                                            \
 409    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 410
 411 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 412
 413 #endif  /* __CONFIG_H */