include/configs/MPC8540ADS.h

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003 Motorola,Inc.
   4  * Xianghua Xiao <X.Xiao@motorola.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * mpc8540ads board configuration file
  27  *
  28  * Please refer to doc/README.mpc85xx for more info.
  29  *
  30  * Make sure you change the MAC address and other network params first,
  31  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /* High Level Configuration Options */
  38 #define CONFIG_BOOKE            1       /* BOOKE */
  39 #define CONFIG_E500             1       /* BOOKE e500 family */
  40 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560 */
  41 #define CONFIG_MPC8540          1       /* MPC8540 specific */
  42 #define CONFIG_MPC8540ADS       1       /* MPC8540ADS board specific */
  43
  44 #ifndef CONFIG_HAS_FEC
  45 #define CONFIG_HAS_FEC          1       /* 8540 has FEC */
  46 #endif
  47
  48 #define CONFIG_PCI
  49 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  50 #define CONFIG_ENV_OVERWRITE
  51 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  52 #define CONFIG_DDR_DLL                  /* possible DLL fix needed */
  53 #define CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
  54
  55 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  56 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  57
  58 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  59
  60 /*
  61  * sysclk for MPC85xx
  62  *
  63  * Two valid values are:
  64  *    33000000
  65  *    66000000
  66  *
  67  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  68  * is likely the desired value here, so that is now the default.
  69  * The board, however, can run at 66MHz.  In any event, this value
  70  * must match the settings of some switches.  Details can be found
  71  * in the README.mpc85xxads.
  72  *
  73  * XXX -- Can't we run at 66 MHz, anyway?  PCI should drop to
  74  * 33MHz to accommodate, based on a PCI pin.
  75  * Note that PCI-X won't work at 33MHz.
  76  */
  77
  78 #ifndef CONFIG_SYS_CLK_FREQ
  79 #define CONFIG_SYS_CLK_FREQ     33000000
  80 #endif
  81
  82
  83 /*
  84  * These can be toggled for performance analysis, otherwise use default.
  85  */
  86 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  87 #define CONFIG_BTB                      /* toggle branch predition */
  88 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
  89
  90 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  91
  92 #undef  CFG_DRAM_TEST                   /* memory test, takes time */
  93 #define CFG_MEMTEST_START       0x00200000      /* memtest region */
  94 #define CFG_MEMTEST_END         0x00400000
  95
  96
  97 /*
  98  * Base addresses -- Note these are effective addresses where the
  99  * actual resources get mapped (not physical addresses)
 100  */
 101 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
 102 #define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR */
 103 #define CFG_CCSRBAR_PHYS        CFG_CCSRBAR     /* physical addr of CCSRBAR */
 104 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR */
 105
 106
 107 /*
 108  * DDR Setup
 109  */
 110 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory*/
 111 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 112
 113 #if defined(CONFIG_SPD_EEPROM)
 114     /*
 115      * Determine DDR configuration from I2C interface.
 116      */
 117     #define SPD_EEPROM_ADDRESS  0x51            /* DDR DIMM */
 118
 119 #else
 120     /*
 121      * Manually set up DDR parameters
 122      */
 123     #define CFG_SDRAM_SIZE      128             /* DDR is 128MB */
 124     #define CFG_DDR_CS0_BNDS    0x00000007      /* 0-128MB */
 125     #define CFG_DDR_CS0_CONFIG  0x80000002
 126     #define CFG_DDR_TIMING_1    0x37344321
 127     #define CFG_DDR_TIMING_2    0x00000800      /* P9-45,may need tuning */
 128     #define CFG_DDR_CONTROL     0xc2000000      /* unbuffered,no DYN_PWR */
 129     #define CFG_DDR_MODE        0x00000062      /* DLL,normal,seq,4/2.5 */
 130     #define CFG_DDR_INTERVAL    0x05200100      /* autocharge,no open page */
 131 #endif
 132
 133
 134 /*
 135  * SDRAM on the Local Bus
 136  */
 137 #define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
 138 #define CFG_LBC_SDRAM_SIZE      64              /* LBC SDRAM is 64MB */
 139
 140 #define CFG_FLASH_BASE          0xff000000      /* start of FLASH 16M */
 141 #define CFG_BR0_PRELIM          0xff001801      /* port size 32bit */
 142
 143 #define CFG_OR0_PRELIM          0xff006ff7      /* 16MB Flash */
 144 #define CFG_MAX_FLASH_BANKS     1               /* number of banks */
 145 #define CFG_MAX_FLASH_SECT      64              /* sectors per device */
 146 #undef  CFG_FLASH_CHECKSUM
 147 #define CFG_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 148 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
 149
 150 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 151
 152 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 153 #define CFG_RAMBOOT
 154 #else
 155 #undef  CFG_RAMBOOT
 156 #endif
 157
 158 #define CFG_FLASH_CFI_DRIVER
 159 #define CFG_FLASH_CFI
 160 #define CFG_FLASH_EMPTY_INFO
 161
 162 #undef CONFIG_CLOCKS_IN_MHZ
 163
 164
 165 /*
 166  * Local Bus Definitions
 167  */
 168
 169 /*
 170  * Base Register 2 and Option Register 2 configure SDRAM.
 171  * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
 172  *
 173  * For BR2, need:
 174  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 175  *    port-size = 32-bits = BR2[19:20] = 11
 176  *    no parity checking = BR2[21:22] = 00
 177  *    SDRAM for MSEL = BR2[24:26] = 011
 178  *    Valid = BR[31] = 1
 179  *
 180  * 0    4    8    12   16   20   24   28
 181  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 182  *
 183  * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
 184  * FIXME: the top 17 bits of BR2.
 185  */
 186
 187 #define CFG_BR2_PRELIM          0xf0001861
 188
 189 /*
 190  * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
 191  *
 192  * For OR2, need:
 193  *    64MB mask for AM, OR2[0:7] = 1111 1100
 194  *                 XAM, OR2[17:18] = 11
 195  *    9 columns OR2[19-21] = 010
 196  *    13 rows   OR2[23-25] = 100
 197  *    EAD set for extra time OR[31] = 1
 198  *
 199  * 0    4    8    12   16   20   24   28
 200  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 201  */
 202
 203 #define CFG_OR2_PRELIM          0xfc006901
 204
 205 #define CFG_LBC_LCRR            0x00030004    /* LB clock ratio reg */
 206 #define CFG_LBC_LBCR            0x00000000    /* LB config reg */
 207 #define CFG_LBC_LSRT            0x20000000    /* LB sdram refresh timer */
 208 #define CFG_LBC_MRTPR           0x20000000    /* LB refresh timer prescal*/
 209
 210 /*
 211  * LSDMR masks
 212  */
 213 #define CFG_LBC_LSDMR_RFEN      (1 << (31 -  1))
 214 #define CFG_LBC_LSDMR_BSMA1516  (3 << (31 - 10))
 215 #define CFG_LBC_LSDMR_BSMA1617  (4 << (31 - 10))
 216 #define CFG_LBC_LSDMR_RFCR5     (3 << (31 - 16))
 217 #define CFG_LBC_LSDMR_RFCR16    (7 << (31 - 16))
 218 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
 219 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
 220 #define CFG_LBC_LSDMR_ACTTORW3  (3 << (31 - 22))
 221 #define CFG_LBC_LSDMR_ACTTORW7  (7 << (31 - 22))
 222 #define CFG_LBC_LSDMR_ACTTORW6  (6 << (31 - 22))
 223 #define CFG_LBC_LSDMR_BL8       (1 << (31 - 23))
 224 #define CFG_LBC_LSDMR_WRC2      (2 << (31 - 27))
 225 #define CFG_LBC_LSDMR_WRC4      (0 << (31 - 27))
 226 #define CFG_LBC_LSDMR_BUFCMD    (1 << (31 - 29))
 227 #define CFG_LBC_LSDMR_CL3       (3 << (31 - 31))
 228
 229 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
 230 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
 231 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
 232 #define CFG_LBC_LSDMR_OP_MRW    (3 << (31 - 4))
 233 #define CFG_LBC_LSDMR_OP_PRECH  (4 << (31 - 4))
 234 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
 235 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
 236 #define CFG_LBC_LSDMR_OP_RWINV  (7 << (31 - 4))
 237
 238 #define CFG_LBC_LSDMR_COMMON    ( CFG_LBC_LSDMR_BSMA1516        \
 239                                 | CFG_LBC_LSDMR_RFCR5           \
 240                                 | CFG_LBC_LSDMR_PRETOACT3       \
 241                                 | CFG_LBC_LSDMR_ACTTORW3        \
 242                                 | CFG_LBC_LSDMR_BL8             \
 243                                 | CFG_LBC_LSDMR_WRC2            \
 244                                 | CFG_LBC_LSDMR_CL3             \
 245                                 | CFG_LBC_LSDMR_RFEN            \
 246                                 )
 247
 248 /*
 249  * SDRAM Controller configuration sequence.
 250  */
 251 #define CFG_LBC_LSDMR_1         ( CFG_LBC_LSDMR_COMMON \
 252                                 | CFG_LBC_LSDMR_OP_PCHALL)
 253 #define CFG_LBC_LSDMR_2         ( CFG_LBC_LSDMR_COMMON \
 254                                 | CFG_LBC_LSDMR_OP_ARFRSH)
 255 #define CFG_LBC_LSDMR_3         ( CFG_LBC_LSDMR_COMMON \
 256                                 | CFG_LBC_LSDMR_OP_ARFRSH)
 257 #define CFG_LBC_LSDMR_4         ( CFG_LBC_LSDMR_COMMON \
 258                                 | CFG_LBC_LSDMR_OP_MRW)
 259 #define CFG_LBC_LSDMR_5         ( CFG_LBC_LSDMR_COMMON \
 260                                 | CFG_LBC_LSDMR_OP_NORMAL)
 261
 262
 263 /*
 264  * 32KB, 8-bit wide for ADS config reg
 265  */
 266 #define CFG_BR4_PRELIM          0xf8000801
 267 #define CFG_OR4_PRELIM          0xffffe1f1
 268 #define CFG_BCSR                (CFG_BR4_PRELIM & 0xffff8000)
 269
 270 #define CONFIG_L1_INIT_RAM
 271 #define CFG_INIT_RAM_LOCK       1
 272 #define CFG_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
 273 #define CFG_INIT_RAM_END        0x4000          /* End of used area in RAM */
 274
 275 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data */
 276 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 277 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 278
 279 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon */
 280 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
 281
 282 /* Serial Port */
 283 #define CONFIG_CONS_INDEX     1
 284 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 285 #define CFG_NS16550
 286 #define CFG_NS16550_SERIAL
 287 #define CFG_NS16550_REG_SIZE    1
 288 #define CFG_NS16550_CLK         get_bus_freq(0)
 289
 290 #define CFG_BAUDRATE_TABLE  \
 291         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 292
 293 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 294 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 295
 296 /* Use the HUSH parser */
 297 #define CFG_HUSH_PARSER
 298 #ifdef  CFG_HUSH_PARSER
 299 #define CFG_PROMPT_HUSH_PS2 "> "
 300 #endif
 301
 302 /* pass open firmware flat tree */
 303 #define CONFIG_OF_LIBFDT                1
 304 #define CONFIG_OF_BOARD_SETUP           1
 305 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 306
 307 #define CFG_64BIT_VSPRINTF      1
 308 #define CFG_64BIT_STRTOUL       1
 309
 310 /*
 311  * I2C
 312  */
 313 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 314 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 315 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 316 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 317 #define CFG_I2C_SLAVE           0x7F
 318 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
 319 #define CFG_I2C_OFFSET          0x3000
 320
 321 /* RapidIO MMU */
 322 #define CFG_RIO_MEM_BASE        0xc0000000      /* base address */
 323 #define CFG_RIO_MEM_PHYS        CFG_RIO_MEM_BASE
 324 #define CFG_RIO_MEM_SIZE        0x20000000      /* 128M */
 325
 326 /*
 327  * General PCI
 328  * Memory space is mapped 1-1, but I/O space must start from 0.
 329  */
 330 #define CFG_PCI1_MEM_BASE       0x80000000
 331 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 332 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
 333 #define CFG_PCI1_IO_BASE        0x00000000
 334 #define CFG_PCI1_IO_PHYS        0xe2000000
 335 #define CFG_PCI1_IO_SIZE        0x100000        /* 1M */
 336
 337 #if defined(CONFIG_PCI)
 338
 339 #define CONFIG_NET_MULTI
 340 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 341
 342 #undef CONFIG_EEPRO100
 343 #undef CONFIG_TULIP
 344
 345 #if !defined(CONFIG_PCI_PNP)
 346     #define PCI_ENET0_IOADDR    0xe0000000
 347     #define PCI_ENET0_MEMADDR   0xe0000000
 348     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 349 #endif
 350
 351 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 352 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 353
 354 #endif  /* CONFIG_PCI */
 355
 356
 357 #if defined(CONFIG_TSEC_ENET)
 358
 359 #ifndef CONFIG_NET_MULTI
 360 #define CONFIG_NET_MULTI        1
 361 #endif
 362
 363 #define CONFIG_MII              1       /* MII PHY management */
 364 #define CONFIG_TSEC1    1
 365 #define CONFIG_TSEC1_NAME       "TSEC0"
 366 #define CONFIG_TSEC2    1
 367 #define CONFIG_TSEC2_NAME       "TSEC1"
 368 #define TSEC1_PHY_ADDR          0
 369 #define TSEC2_PHY_ADDR          1
 370 #define TSEC1_PHYIDX            0
 371 #define TSEC2_PHYIDX            0
 372 #define TSEC1_FLAGS             TSEC_GIGABIT
 373 #define TSEC2_FLAGS             TSEC_GIGABIT
 374
 375
 376 #if CONFIG_HAS_FEC
 377 #define CONFIG_MPC85XX_FEC      1
 378 #define CONFIG_MPC85XX_FEC_NAME         "FEC"
 379 #define FEC_PHY_ADDR            3
 380 #define FEC_PHYIDX              0
 381 #define FEC_FLAGS               0
 382 #endif
 383
 384 /* Options are: TSEC[0-1], FEC */
 385 #define CONFIG_ETHPRIME         "TSEC0"
 386
 387 #endif  /* CONFIG_TSEC_ENET */
 388
 389
 390 /*
 391  * Environment
 392  */
 393 #ifndef CFG_RAMBOOT
 394   #define CFG_ENV_IS_IN_FLASH   1
 395   #define CFG_ENV_ADDR          (CFG_MONITOR_BASE + 0x40000)
 396   #define CFG_ENV_SECT_SIZE     0x40000 /* 256K(one sector) for env */
 397   #define CFG_ENV_SIZE          0x2000
 398 #else
 399   #define CFG_NO_FLASH          1       /* Flash is not usable now */
 400   #define CFG_ENV_IS_NOWHERE    1       /* Store ENV in memory only */
 401   #define CFG_ENV_ADDR          (CFG_MONITOR_BASE - 0x1000)
 402   #define CFG_ENV_SIZE          0x2000
 403 #endif
 404
 405 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 406 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 407
 408
 409 /*
 410  * BOOTP options
 411  */
 412 #define CONFIG_BOOTP_BOOTFILESIZE
 413 #define CONFIG_BOOTP_BOOTPATH
 414 #define CONFIG_BOOTP_GATEWAY
 415 #define CONFIG_BOOTP_HOSTNAME
 416
 417
 418 /*
 419  * Command line configuration.
 420  */
 421 #include <config_cmd_default.h>
 422
 423 #define CONFIG_CMD_PING
 424 #define CONFIG_CMD_I2C
 425 #define CONFIG_CMD_ELF
 426
 427 #if defined(CONFIG_PCI)
 428     #define CONFIG_CMD_PCI
 429 #endif
 430
 431 #if defined(CFG_RAMBOOT)
 432     #undef CONFIG_CMD_ENV
 433     #undef CONFIG_CMD_LOADS
 434 #endif
 435
 436
 437 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 438
 439 /*
 440  * Miscellaneous configurable options
 441  */
 442 #define CFG_LONGHELP                    /* undef to save memory */
 443 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 444 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 445 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 446
 447 #if defined(CONFIG_CMD_KGDB)
 448     #define CFG_CBSIZE  1024            /* Console I/O Buffer Size */
 449 #else
 450     #define CFG_CBSIZE  256             /* Console I/O Buffer Size */
 451 #endif
 452
 453 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 454 #define CFG_MAXARGS     16              /* max number of command args */
 455 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 456 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 457
 458 /*
 459  * For booting Linux, the board info and command line data
 460  * have to be in the first 8 MB of memory, since this is
 461  * the maximum mapped by the Linux kernel during initialization.
 462  */
 463 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 464
 465 /*
 466  * Internal Definitions
 467  *
 468  * Boot Flags
 469  */
 470 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 471 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 472
 473 #if defined(CONFIG_CMD_KGDB)
 474 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 475 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 476 #endif
 477
 478
 479 /*
 480  * Environment Configuration
 481  */
 482
 483 /* The mac addresses for all ethernet interface */
 484 #if defined(CONFIG_TSEC_ENET)
 485 #define CONFIG_HAS_ETH0
 486 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 487 #define CONFIG_HAS_ETH1
 488 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 489 #define CONFIG_HAS_ETH2
 490 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 491 #endif
 492
 493 #define CONFIG_IPADDR    192.168.1.253
 494
 495 #define CONFIG_HOSTNAME         unknown
 496 #define CONFIG_ROOTPATH         /nfsroot
 497 #define CONFIG_BOOTFILE         your.uImage
 498
 499 #define CONFIG_SERVERIP  192.168.1.1
 500 #define CONFIG_GATEWAYIP 192.168.1.1
 501 #define CONFIG_NETMASK   255.255.255.0
 502
 503 #define CONFIG_LOADADDR  200000 /* default location for tftp and bootm */
 504
 505 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 506 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 507
 508 #define CONFIG_BAUDRATE 115200
 509
 510 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 511    "netdev=eth0\0"                                                      \
 512    "consoledev=ttyS0\0"                                                 \
 513    "ramdiskaddr=1000000\0"                                              \
 514    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 515    "fdtaddr=400000\0"                                                   \
 516    "fdtfile=your.fdt.dtb\0"
 517
 518 #define CONFIG_NFSBOOTCOMMAND                                           \
 519    "setenv bootargs root=/dev/nfs rw "                                  \
 520       "nfsroot=$serverip:$rootpath "                                    \
 521       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 522       "console=$consoledev,$baudrate $othbootargs;"                     \
 523    "tftp $loadaddr $bootfile;"                                          \
 524    "tftp $fdtaddr $fdtfile;"                                            \
 525    "bootm $loadaddr - $fdtaddr"
 526
 527 #define CONFIG_RAMBOOTCOMMAND \
 528    "setenv bootargs root=/dev/ram rw "                                  \
 529       "console=$consoledev,$baudrate $othbootargs;"                     \
 530    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 531    "tftp $loadaddr $bootfile;"                                          \
 532    "tftp $fdtaddr $fdtfile;"                                            \
 533    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 534
 535 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 536
 537 #endif  /* __CONFIG_H */