include/configs/MPC8540ADS.h

   1 /*
   2  * Copyright 2004, 2011 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003 Motorola,Inc.
   4  * Xianghua Xiao <X.Xiao@motorola.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * mpc8540ads board configuration file
  27  *
  28  * Please refer to doc/README.mpc85xx for more info.
  29  *
  30  * Make sure you change the MAC address and other network params first,
  31  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /* High Level Configuration Options */
  38 #define CONFIG_BOOKE            1       /* BOOKE */
  39 #define CONFIG_E500             1       /* BOOKE e500 family */
  40 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560 */
  41 #define CONFIG_MPC8540          1       /* MPC8540 specific */
  42 #define CONFIG_MPC8540ADS       1       /* MPC8540ADS board specific */
  43
  44 /*
  45  * default CCARBAR is at 0xff700000
  46  * assume U-Boot is less than 0.5MB
  47  */
  48 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  49
  50 #ifndef CONFIG_HAS_FEC
  51 #define CONFIG_HAS_FEC          1       /* 8540 has FEC */
  52 #endif
  53
  54 #define CONFIG_PCI
  55 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  56 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  57 #define CONFIG_ENV_OVERWRITE
  58 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  59
  60 /*
  61  * sysclk for MPC85xx
  62  *
  63  * Two valid values are:
  64  *    33000000
  65  *    66000000
  66  *
  67  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  68  * is likely the desired value here, so that is now the default.
  69  * The board, however, can run at 66MHz.  In any event, this value
  70  * must match the settings of some switches.  Details can be found
  71  * in the README.mpc85xxads.
  72  *
  73  * XXX -- Can't we run at 66 MHz, anyway?  PCI should drop to
  74  * 33MHz to accommodate, based on a PCI pin.
  75  * Note that PCI-X won't work at 33MHz.
  76  */
  77
  78 #ifndef CONFIG_SYS_CLK_FREQ
  79 #define CONFIG_SYS_CLK_FREQ     33000000
  80 #endif
  81
  82
  83 /*
  84  * These can be toggled for performance analysis, otherwise use default.
  85  */
  86 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  87 #define CONFIG_BTB                      /* toggle branch predition */
  88
  89 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  90 #define CONFIG_SYS_MEMTEST_END          0x00400000
  91
  92
  93 /*
  94  * Base addresses -- Note these are effective addresses where the
  95  * actual resources get mapped (not physical addresses)
  96  */
  97 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  98 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  99 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
 100 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
 101
 102 /* DDR Setup */
 103 #define CONFIG_FSL_DDR1
 104 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
 105 #define CONFIG_DDR_SPD
 106 #undef CONFIG_FSL_DDR_INTERACTIVE
 107
 108 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 109
 110 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 111 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 112
 113 #define CONFIG_NUM_DDR_CONTROLLERS      1
 114 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 115 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 116
 117 /* I2C addresses of SPD EEPROMs */
 118 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 119
 120 /* These are used when DDR doesn't use SPD. */
 121 #define CONFIG_SYS_SDRAM_SIZE   128             /* DDR is 128MB */
 122 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007      /* 0-128MB */
 123 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80000002
 124 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
 125 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 126 #define CONFIG_SYS_DDR_CONTROL          0xc2000000      /* unbuffered,no DYN_PWR */
 127 #define CONFIG_SYS_DDR_MODE             0x00000062      /* DLL,normal,seq,4/2.5 */
 128 #define CONFIG_SYS_DDR_INTERVAL 0x05200100      /* autocharge,no open page */
 129
 130 /*
 131  * SDRAM on the Local Bus
 132  */
 133 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 134 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 135
 136 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 16M */
 137 #define CONFIG_SYS_BR0_PRELIM           0xff001801      /* port size 32bit */
 138
 139 #define CONFIG_SYS_OR0_PRELIM           0xff006ff7      /* 16MB Flash */
 140 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 141 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* sectors per device */
 142 #undef  CONFIG_SYS_FLASH_CHECKSUM
 143 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 144 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 145
 146 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 147
 148 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 149 #define CONFIG_SYS_RAMBOOT
 150 #else
 151 #undef  CONFIG_SYS_RAMBOOT
 152 #endif
 153
 154 #define CONFIG_FLASH_CFI_DRIVER
 155 #define CONFIG_SYS_FLASH_CFI
 156 #define CONFIG_SYS_FLASH_EMPTY_INFO
 157
 158 #undef CONFIG_CLOCKS_IN_MHZ
 159
 160
 161 /*
 162  * Local Bus Definitions
 163  */
 164
 165 /*
 166  * Base Register 2 and Option Register 2 configure SDRAM.
 167  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 168  *
 169  * For BR2, need:
 170  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 171  *    port-size = 32-bits = BR2[19:20] = 11
 172  *    no parity checking = BR2[21:22] = 00
 173  *    SDRAM for MSEL = BR2[24:26] = 011
 174  *    Valid = BR[31] = 1
 175  *
 176  * 0    4    8    12   16   20   24   28
 177  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 178  *
 179  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 180  * FIXME: the top 17 bits of BR2.
 181  */
 182
 183 #define CONFIG_SYS_BR2_PRELIM           0xf0001861
 184
 185 /*
 186  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 187  *
 188  * For OR2, need:
 189  *    64MB mask for AM, OR2[0:7] = 1111 1100
 190  *                 XAM, OR2[17:18] = 11
 191  *    9 columns OR2[19-21] = 010
 192  *    13 rows   OR2[23-25] = 100
 193  *    EAD set for extra time OR[31] = 1
 194  *
 195  * 0    4    8    12   16   20   24   28
 196  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 197  */
 198
 199 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 200
 201 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 202 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 203 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
 204 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer prescal*/
 205
 206 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_BSMA1516        \
 207                                 | LSDMR_RFCR5           \
 208                                 | LSDMR_PRETOACT3       \
 209                                 | LSDMR_ACTTORW3        \
 210                                 | LSDMR_BL8             \
 211                                 | LSDMR_WRC2            \
 212                                 | LSDMR_CL3             \
 213                                 | LSDMR_RFEN            \
 214                                 )
 215
 216 /*
 217  * SDRAM Controller configuration sequence.
 218  */
 219 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 220 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 221 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 222 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 223 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 224
 225
 226 /*
 227  * 32KB, 8-bit wide for ADS config reg
 228  */
 229 #define CONFIG_SYS_BR4_PRELIM          0xf8000801
 230 #define CONFIG_SYS_OR4_PRELIM           0xffffe1f1
 231 #define CONFIG_SYS_BCSR         (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 232
 233 #define CONFIG_SYS_INIT_RAM_LOCK        1
 234 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 235 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 236
 237 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 238 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 239
 240 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 241 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 242
 243 /* Serial Port */
 244 #define CONFIG_CONS_INDEX     1
 245 #define CONFIG_SYS_NS16550
 246 #define CONFIG_SYS_NS16550_SERIAL
 247 #define CONFIG_SYS_NS16550_REG_SIZE    1
 248 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 249
 250 #define CONFIG_SYS_BAUDRATE_TABLE  \
 251         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 252
 253 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 254 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 255
 256 /* Use the HUSH parser */
 257 #define CONFIG_SYS_HUSH_PARSER
 258 #ifdef  CONFIG_SYS_HUSH_PARSER
 259 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 260 #endif
 261
 262 /* pass open firmware flat tree */
 263 #define CONFIG_OF_LIBFDT                1
 264 #define CONFIG_OF_BOARD_SETUP           1
 265 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 266
 267 /*
 268  * I2C
 269  */
 270 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 271 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 272 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 273 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 274 #define CONFIG_SYS_I2C_SLAVE            0x7F
 275 #define CONFIG_SYS_I2C_NOPROBES        {0x69}   /* Don't probe these addrs */
 276 #define CONFIG_SYS_I2C_OFFSET           0x3000
 277
 278 /* RapidIO MMU */
 279 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000      /* base address */
 280 #define CONFIG_SYS_RIO_MEM_BUS  0xc0000000      /* base address */
 281 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
 282 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 283
 284 /*
 285  * General PCI
 286  * Memory space is mapped 1-1, but I/O space must start from 0.
 287  */
 288 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 289 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 290 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 291 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 292 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 293 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 294 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 295 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000        /* 1M */
 296
 297 #if defined(CONFIG_PCI)
 298
 299 #define CONFIG_NET_MULTI
 300 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 301
 302 #undef CONFIG_EEPRO100
 303 #undef CONFIG_TULIP
 304
 305 #if !defined(CONFIG_PCI_PNP)
 306     #define PCI_ENET0_IOADDR    0xe0000000
 307     #define PCI_ENET0_MEMADDR   0xe0000000
 308     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 309 #endif
 310
 311 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 312 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 313
 314 #endif  /* CONFIG_PCI */
 315
 316
 317 #if defined(CONFIG_TSEC_ENET)
 318
 319 #ifndef CONFIG_NET_MULTI
 320 #define CONFIG_NET_MULTI        1
 321 #endif
 322
 323 #define CONFIG_MII              1       /* MII PHY management */
 324 #define CONFIG_TSEC1    1
 325 #define CONFIG_TSEC1_NAME       "TSEC0"
 326 #define CONFIG_TSEC2    1
 327 #define CONFIG_TSEC2_NAME       "TSEC1"
 328 #define TSEC1_PHY_ADDR          0
 329 #define TSEC2_PHY_ADDR          1
 330 #define TSEC1_PHYIDX            0
 331 #define TSEC2_PHYIDX            0
 332 #define TSEC1_FLAGS             TSEC_GIGABIT
 333 #define TSEC2_FLAGS             TSEC_GIGABIT
 334
 335
 336 #if CONFIG_HAS_FEC
 337 #define CONFIG_MPC85XX_FEC      1
 338 #define CONFIG_MPC85XX_FEC_NAME         "FEC"
 339 #define FEC_PHY_ADDR            3
 340 #define FEC_PHYIDX              0
 341 #define FEC_FLAGS               0
 342 #endif
 343
 344 /* Options are: TSEC[0-1], FEC */
 345 #define CONFIG_ETHPRIME         "TSEC0"
 346
 347 #endif  /* CONFIG_TSEC_ENET */
 348
 349
 350 /*
 351  * Environment
 352  */
 353 #ifndef CONFIG_SYS_RAMBOOT
 354   #define CONFIG_ENV_IS_IN_FLASH        1
 355   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE + 0x40000)
 356   #define CONFIG_ENV_SECT_SIZE  0x40000 /* 256K(one sector) for env */
 357   #define CONFIG_ENV_SIZE               0x2000
 358 #else
 359   #define CONFIG_SYS_NO_FLASH           1       /* Flash is not usable now */
 360   #define CONFIG_ENV_IS_NOWHERE 1       /* Store ENV in memory only */
 361   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 362   #define CONFIG_ENV_SIZE               0x2000
 363 #endif
 364
 365 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 366 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 367
 368
 369 /*
 370  * BOOTP options
 371  */
 372 #define CONFIG_BOOTP_BOOTFILESIZE
 373 #define CONFIG_BOOTP_BOOTPATH
 374 #define CONFIG_BOOTP_GATEWAY
 375 #define CONFIG_BOOTP_HOSTNAME
 376
 377
 378 /*
 379  * Command line configuration.
 380  */
 381 #include <config_cmd_default.h>
 382
 383 #define CONFIG_CMD_PING
 384 #define CONFIG_CMD_I2C
 385 #define CONFIG_CMD_ELF
 386 #define CONFIG_CMD_IRQ
 387 #define CONFIG_CMD_SETEXPR
 388
 389 #if defined(CONFIG_PCI)
 390     #define CONFIG_CMD_PCI
 391 #endif
 392
 393 #if defined(CONFIG_SYS_RAMBOOT)
 394     #undef CONFIG_CMD_SAVEENV
 395     #undef CONFIG_CMD_LOADS
 396 #endif
 397
 398
 399 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 400
 401 /*
 402  * Miscellaneous configurable options
 403  */
 404 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 405 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 406 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 407 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 408 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 409
 410 #if defined(CONFIG_CMD_KGDB)
 411     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 412 #else
 413     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 414 #endif
 415
 416 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 417 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 418 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 419 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 420
 421 /*
 422  * For booting Linux, the board info and command line data
 423  * have to be in the first 16 MB of memory, since this is
 424  * the maximum mapped by the Linux kernel during initialization.
 425  */
 426 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 427 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
 428
 429 #if defined(CONFIG_CMD_KGDB)
 430 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 431 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 432 #endif
 433
 434
 435 /*
 436  * Environment Configuration
 437  */
 438
 439 /* The mac addresses for all ethernet interface */
 440 #if defined(CONFIG_TSEC_ENET)
 441 #define CONFIG_HAS_ETH0
 442 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 443 #define CONFIG_HAS_ETH1
 444 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 445 #define CONFIG_HAS_ETH2
 446 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 447 #endif
 448
 449 #define CONFIG_IPADDR    192.168.1.253
 450
 451 #define CONFIG_HOSTNAME         unknown
 452 #define CONFIG_ROOTPATH         /nfsroot
 453 #define CONFIG_BOOTFILE         your.uImage
 454
 455 #define CONFIG_SERVERIP  192.168.1.1
 456 #define CONFIG_GATEWAYIP 192.168.1.1
 457 #define CONFIG_NETMASK   255.255.255.0
 458
 459 #define CONFIG_LOADADDR  200000 /* default location for tftp and bootm */
 460
 461 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 462 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 463
 464 #define CONFIG_BAUDRATE 115200
 465
 466 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 467    "netdev=eth0\0"                                                      \
 468    "consoledev=ttyS0\0"                                                 \
 469    "ramdiskaddr=1000000\0"                                              \
 470    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 471    "fdtaddr=400000\0"                                                   \
 472    "fdtfile=your.fdt.dtb\0"
 473
 474 #define CONFIG_NFSBOOTCOMMAND                                           \
 475    "setenv bootargs root=/dev/nfs rw "                                  \
 476       "nfsroot=$serverip:$rootpath "                                    \
 477       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 478       "console=$consoledev,$baudrate $othbootargs;"                     \
 479    "tftp $loadaddr $bootfile;"                                          \
 480    "tftp $fdtaddr $fdtfile;"                                            \
 481    "bootm $loadaddr - $fdtaddr"
 482
 483 #define CONFIG_RAMBOOTCOMMAND \
 484    "setenv bootargs root=/dev/ram rw "                                  \
 485       "console=$consoledev,$baudrate $othbootargs;"                     \
 486    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 487    "tftp $loadaddr $bootfile;"                                          \
 488    "tftp $fdtaddr $fdtfile;"                                            \
 489    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 490
 491 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 492
 493 #endif  /* __CONFIG_H */